diff --git a/arch/arm/src/imxrt/hardware/imxrt_lpspi.h b/arch/arm/src/imxrt/hardware/imxrt_lpspi.h
index 6585316a996..11ff130c273 100644
--- a/arch/arm/src/imxrt/hardware/imxrt_lpspi.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_lpspi.h
@@ -47,6 +47,10 @@
 #define IMXRT_LPSPI_DMR0_OFFSET        0x0030  /* Data Match Register 0 offset */
 #define IMXRT_LPSPI_DMR1_OFFSET        0x0034  /* Data Match Register 1 offset */
 #define IMXRT_LPSPI_CCR_OFFSET         0x0040  /* Clock Configuration Register offset */
+#define IMXRT_LPSPI_CCR_SCKDIV_OFFSET  0x0040  /* SCK divider byte offset */
+#define IMXRT_LPSPI_CCR_DBT_OFFSET     0x0041  /* Delay between transfers byte offset */
+#define IMXRT_LPSPI_CCR_PCSSCK_OFFSET  0x0042  /* PCS-to-SCK delay byte offset */
+#define IMXRT_LPSPI_CCR_SCKPCS_OFFSET  0x0043  /* SCK-to-PCS delay byte offset */
 #define IMXRT_LPSPI_FCR_OFFSET         0x0058  /* FIFO Control Register offset */
 #define IMXRT_LPSPI_FSR_OFFSET         0x005C  /* FIFO Status Register offset */
 #define IMXRT_LPSPI_TCR_OFFSET         0x0060  /* Transmit Command Register offset */
diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c
index 087582ae040..4ffb7050f66 100644
--- a/arch/arm/src/imxrt/imxrt_lpspi.c
+++ b/arch/arm/src/imxrt/imxrt_lpspi.c
@@ -684,28 +684,43 @@ static inline void imxrt_lpspi_master_set_delay_scaler(
     {
       case LPSPI_PCS_TO_SCK:
         {
+#ifdef CONFIG_ARCH_FAMILY_IMXRT118x
+          putreg8((uint8_t)scaler,
+                  priv->spibase + IMXRT_LPSPI_CCR_PCSSCK_OFFSET);
+#else
           imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
                                   LPSPI_CCR_PCSSCK_MASK, 0);
           imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
                                   LPSPI_CCR_PCSSCK(scaler));
+#endif
           break;
         }
 
       case LPSPI_LAST_SCK_TO_PCS:
         {
+#ifdef CONFIG_ARCH_FAMILY_IMXRT118x
+          putreg8((uint8_t)scaler,
+                  priv->spibase + IMXRT_LPSPI_CCR_SCKPCS_OFFSET);
+#else
           imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
                                   LPSPI_CCR_SCKPCS_MASK, 0);
           imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
                                   LPSPI_CCR_SCKPCS(scaler));
+#endif
           break;
         }
 
       case LPSPI_BETWEEN_TRANSFER:
         {
+#ifdef CONFIG_ARCH_FAMILY_IMXRT118x
+          putreg8((uint8_t)scaler,
+                  priv->spibase + IMXRT_LPSPI_CCR_DBT_OFFSET);
+#else
           imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
                                   LPSPI_CCR_DBT_MASK, 0);
           imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
                                   LPSPI_CCR_DBT(scaler));
+#endif
           break;
         }
     }
@@ -1064,9 +1079,14 @@ static uint32_t imxrt_lpspi_setfrequency(struct spi_dev_s *dev,
 
       /* Write the best values in the CCR register */
 
+#ifdef CONFIG_ARCH_FAMILY_IMXRT118x
+      putreg8((uint8_t)best_scaler,
+              priv->spibase + IMXRT_LPSPI_CCR_SCKDIV_OFFSET);
+#else
       imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
                               LPSPI_CCR_SCKDIV_MASK,
                               LPSPI_CCR_SCKDIV(best_scaler));
+#endif
 
       imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET,
                               LPSPI_TCR_PRESCALE_MASK,