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Fix for SAMv7 SPI: DLYBS value wass calculated, but never written to any registers. This led to incorrect timings on the bus.

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Spahlinger, Michael 2017-02-16 07:42:37 -06:00 • committed by Gregory Nutt
parent c3bfccf293
commit 42e8b12ec3
1 changed files with 1 additions and 0 deletions
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arch/arm/src/samv7/sam_spi.c
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@ -1158,6 +1158,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
regval = spi_getreg(spi, offset);
regval &= ~SPI_CSR_DLYBS_MASK;
regval |= (uint32_t) dlybs << SPI_CSR_DLYBS_SHIFT;
spi_putreg(spi, regval, offset);
/* stopdelay = DLYBCT: Delay Between Consecutive Transfers.
* This field defines the delay between two consecutive transfers with the