From 42e8b12ec30a0343d7fd084553cdafba9aa306a2 Mon Sep 17 00:00:00 2001 From: "Spahlinger, Michael" Date: Thu, 16 Feb 2017 07:42:37 -0600 Subject: [PATCH] Fix for SAMv7 SPI: DLYBS value wass calculated, but never written to any registers. This led to incorrect timings on the bus. --- arch/arm/src/samv7/sam_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index d0b40e8694f..de1dec16150 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -1158,6 +1158,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay, regval = spi_getreg(spi, offset); regval &= ~SPI_CSR_DLYBS_MASK; regval |= (uint32_t) dlybs << SPI_CSR_DLYBS_SHIFT; + spi_putreg(spi, regval, offset); /* stopdelay = DLYBCT: Delay Between Consecutive Transfers. * This field defines the delay between two consecutive transfers with the