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arch/arm/ra8m1: Add Renesas RA8M1 chip support

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Add initial architecture support for the Renesas RA8M1 (Cortex-M85)
family: clock configuration, GPIO, ICU/IRQ handling, SCI serial,
system timer, option setting and start-up code, plus the Kconfig and
build system integration.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Signed-off-by: leocafonso <leocafonso@gmail.com>
This commit is contained in:
leocafonso 2026-09-25 11:08:56 -07:00 • committed by Alan C. Assis
parent 0fafd0bc7f
commit 1515b3fafd
35 changed files with 10760 additions and 0 deletions
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11
arch/arm/Kconfig
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@ -382,6 +382,13 @@ config ARCH_CHIP_RA4
---help---
Renesas RA4 Architecture (ARM Cortex-M4F/M33).
config ARCH_CHIP_RA8M1
bool "Renesas RA8M1"
select ARCH_CORTEXM85
select ARCH_HAVE_FPU
---help---
Renesas RA8M1 Family (ARM Cortex-M85).
config ARCH_CHIP_RP2040
bool "Raspberry Pi RP2040"
select ARCH_CORTEXM0
@ -1358,6 +1365,7 @@ config ARCH_CHIP
default "nrf91" if ARCH_CHIP_NRF91
default "nuc1xx" if ARCH_CHIP_NUC1XX
default "ra4" if ARCH_CHIP_RA4
default "ra8m1" if ARCH_CHIP_RA8M1
default "rp2040" if ARCH_CHIP_RP2040
default "rp23xx" if ARCH_CHIP_RP23XX
default "s32k1xx" if ARCH_CHIP_S32K1XX
@ -1869,6 +1877,9 @@ endif
if ARCH_CHIP_RA4
source "arch/arm/src/ra4/Kconfig"
endif
if ARCH_CHIP_RA8M1
source "arch/arm/src/ra8m1/Kconfig"
endif
if ARCH_CHIP_RP2040
source "arch/arm/src/rp2040/Kconfig"
endif

235
arch/arm/include/ra8m1/chip.h Normal file
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@ -0,0 +1,235 @@
/****************************************************************************
* arch/arm/include/ra8m1/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_RA8M1_CHIP_H
#define __ARCH_ARM_INCLUDE_RA8M1_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_R7FA8M1AFECAM)
# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */
# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
# if defined(CONFIG_ARMV8M_HAVE_ITCM)
# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
# else
# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
# endif
# if defined(CONFIG_ARMV8M_HAVE_DTCM)
# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
# else
# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
# endif
#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECBD)
# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */
# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
# if defined(CONFIG_ARMV8M_HAVE_ITCM)
# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
# else
# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
# endif
# if defined(CONFIG_ARMV8M_HAVE_DTCM)
# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
# else
# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
# endif
#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFB)
# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */
# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
# if defined(CONFIG_ARMV8M_HAVE_ITCM)
# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
# else
# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
# endif
# if defined(CONFIG_ARMV8M_HAVE_DTCM)
# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
# else
# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
# endif
#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFC)
# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */
# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
# if defined(CONFIG_ARMV8M_HAVE_ITCM)
# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
# else
# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
# endif
# if defined(CONFIG_ARMV8M_HAVE_DTCM)
# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
# else
# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
# endif
#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFP)
# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */
# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
# if defined(CONFIG_ARMV8M_HAVE_ITCM)
# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
# else
# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
# endif
# if defined(CONFIG_ARMV8M_HAVE_DTCM)
# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
# else
# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
# endif
#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECAM)
# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */
# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
# if defined(CONFIG_ARMV8M_HAVE_ITCM)
# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
# else
# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
# endif
# if defined(CONFIG_ARMV8M_HAVE_DTCM)
# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
# else
# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
# endif
#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECBD)
# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */
# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
# if defined(CONFIG_ARMV8M_HAVE_ITCM)
# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
# else
# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
# endif
# if defined(CONFIG_ARMV8M_HAVE_DTCM)
# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
# else
# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
# endif
#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFB)
# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */
# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
# if defined(CONFIG_ARMV8M_HAVE_ITCM)
# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
# else
# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
# endif
# if defined(CONFIG_ARMV8M_HAVE_DTCM)
# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
# else
# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
# endif
#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFC)
# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */
# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
# if defined(CONFIG_ARMV8M_HAVE_ITCM)
# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
# else
# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
# endif
# if defined(CONFIG_ARMV8M_HAVE_DTCM)
# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
# else
# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
# endif
#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFP)
# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */
# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
# if defined(CONFIG_ARMV8M_HAVE_ITCM)
# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
# else
# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
# endif
# if defined(CONFIG_ARMV8M_HAVE_DTCM)
# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
# else
# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
# endif
#else
# error "Unsupported RA8M1 chip"
#endif
/* NVIC Priority Levels *****************************************************/
/* Each priority field holds a priority value, 0-15. The lower
* the value, the greater the priority of the corresponding
* interrupt. The processor implements only bits[7:4] of each
* field, bits[3:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_RA8M1_CHIP_H */

103
arch/arm/include/ra8m1/irq.h Normal file
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@ -0,0 +1,103 @@
/****************************************************************************
* arch/arm/include/ra8m1/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_RA8M1_IRQ_H
#define __ARCH_ARM_INCLUDE_RA8M1_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/ra8m1/chip.h>
#if defined(CONFIG_RA8M1_FAMILY)
# include <arch/ra8m1/ra8m1_irq.h>
#else
# error Unrecognized RA architecture
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers.
* The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in
* the IRQ to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define RA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define RA_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define RA_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define RA_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define RA_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define RA_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define RA_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define RA_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define RA_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define RA_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* Chip-Specific External interrupts */
#define RA_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#define NR_IRQS (RA_IRQ_FIRST + RA_IRQ_NEXTINT)
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_RA8M1_IRQ_H */

222
arch/arm/include/ra8m1/ra8m1_irq.h Normal file
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@ -0,0 +1,222 @@
/****************************************************************************
* arch/arm/include/ra8m1/ra8m1_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_RA8M1_RA8M1_IRQ_H
#define __ARCH_ARM_INCLUDE_RA8M1_RA8M1_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/ra8m1/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Total number of IRQ numbers.
*
* Every ICU IELSR slot is runtime-configurable -- any peripheral event
* can be routed to any slot -- so RA_IRQ_IELSRn below are just the raw
* vector numbers; RA_IRQ_NEXTINT is the total slot count. Both come
* directly from this chip's .rzone <processor DnumInterrupts>.
*/
#define RA_IRQ_IELSR0 (RA_IRQ_FIRST + 0) /* 0: Event selected in the ICU.IELSR0 register */
#define RA_IRQ_IELSR1 (RA_IRQ_FIRST + 1) /* 1: Event selected in the ICU.IELSR1 register */
#define RA_IRQ_IELSR2 (RA_IRQ_FIRST + 2) /* 2: Event selected in the ICU.IELSR2 register */
#define RA_IRQ_IELSR3 (RA_IRQ_FIRST + 3) /* 3: Event selected in the ICU.IELSR3 register */
#define RA_IRQ_IELSR4 (RA_IRQ_FIRST + 4) /* 4: Event selected in the ICU.IELSR4 register */
#define RA_IRQ_IELSR5 (RA_IRQ_FIRST + 5) /* 5: Event selected in the ICU.IELSR5 register */
#define RA_IRQ_IELSR6 (RA_IRQ_FIRST + 6) /* 6: Event selected in the ICU.IELSR6 register */
#define RA_IRQ_IELSR7 (RA_IRQ_FIRST + 7) /* 7: Event selected in the ICU.IELSR7 register */
#define RA_IRQ_IELSR8 (RA_IRQ_FIRST + 8) /* 8: Event selected in the ICU.IELSR8 register */
#define RA_IRQ_IELSR9 (RA_IRQ_FIRST + 9) /* 9: Event selected in the ICU.IELSR9 register */
#define RA_IRQ_IELSR10 (RA_IRQ_FIRST + 10) /* 10: Event selected in the ICU.IELSR10 register */
#define RA_IRQ_IELSR11 (RA_IRQ_FIRST + 11) /* 11: Event selected in the ICU.IELSR11 register */
#define RA_IRQ_IELSR12 (RA_IRQ_FIRST + 12) /* 12: Event selected in the ICU.IELSR12 register */
#define RA_IRQ_IELSR13 (RA_IRQ_FIRST + 13) /* 13: Event selected in the ICU.IELSR13 register */
#define RA_IRQ_IELSR14 (RA_IRQ_FIRST + 14) /* 14: Event selected in the ICU.IELSR14 register */
#define RA_IRQ_IELSR15 (RA_IRQ_FIRST + 15) /* 15: Event selected in the ICU.IELSR15 register */
#define RA_IRQ_IELSR16 (RA_IRQ_FIRST + 16) /* 16: Event selected in the ICU.IELSR16 register */
#define RA_IRQ_IELSR17 (RA_IRQ_FIRST + 17) /* 17: Event selected in the ICU.IELSR17 register */
#define RA_IRQ_IELSR18 (RA_IRQ_FIRST + 18) /* 18: Event selected in the ICU.IELSR18 register */
#define RA_IRQ_IELSR19 (RA_IRQ_FIRST + 19) /* 19: Event selected in the ICU.IELSR19 register */
#define RA_IRQ_IELSR20 (RA_IRQ_FIRST + 20) /* 20: Event selected in the ICU.IELSR20 register */
#define RA_IRQ_IELSR21 (RA_IRQ_FIRST + 21) /* 21: Event selected in the ICU.IELSR21 register */
#define RA_IRQ_IELSR22 (RA_IRQ_FIRST + 22) /* 22: Event selected in the ICU.IELSR22 register */
#define RA_IRQ_IELSR23 (RA_IRQ_FIRST + 23) /* 23: Event selected in the ICU.IELSR23 register */
#define RA_IRQ_IELSR24 (RA_IRQ_FIRST + 24) /* 24: Event selected in the ICU.IELSR24 register */
#define RA_IRQ_IELSR25 (RA_IRQ_FIRST + 25) /* 25: Event selected in the ICU.IELSR25 register */
#define RA_IRQ_IELSR26 (RA_IRQ_FIRST + 26) /* 26: Event selected in the ICU.IELSR26 register */
#define RA_IRQ_IELSR27 (RA_IRQ_FIRST + 27) /* 27: Event selected in the ICU.IELSR27 register */
#define RA_IRQ_IELSR28 (RA_IRQ_FIRST + 28) /* 28: Event selected in the ICU.IELSR28 register */
#define RA_IRQ_IELSR29 (RA_IRQ_FIRST + 29) /* 29: Event selected in the ICU.IELSR29 register */
#define RA_IRQ_IELSR30 (RA_IRQ_FIRST + 30) /* 30: Event selected in the ICU.IELSR30 register */
#define RA_IRQ_IELSR31 (RA_IRQ_FIRST + 31) /* 31: Event selected in the ICU.IELSR31 register */
#define RA_IRQ_IELSR32 (RA_IRQ_FIRST + 32) /* 32: Event selected in the ICU.IELSR32 register */
#define RA_IRQ_IELSR33 (RA_IRQ_FIRST + 33) /* 33: Event selected in the ICU.IELSR33 register */
#define RA_IRQ_IELSR34 (RA_IRQ_FIRST + 34) /* 34: Event selected in the ICU.IELSR34 register */
#define RA_IRQ_IELSR35 (RA_IRQ_FIRST + 35) /* 35: Event selected in the ICU.IELSR35 register */
#define RA_IRQ_IELSR36 (RA_IRQ_FIRST + 36) /* 36: Event selected in the ICU.IELSR36 register */
#define RA_IRQ_IELSR37 (RA_IRQ_FIRST + 37) /* 37: Event selected in the ICU.IELSR37 register */
#define RA_IRQ_IELSR38 (RA_IRQ_FIRST + 38) /* 38: Event selected in the ICU.IELSR38 register */
#define RA_IRQ_IELSR39 (RA_IRQ_FIRST + 39) /* 39: Event selected in the ICU.IELSR39 register */
#define RA_IRQ_IELSR40 (RA_IRQ_FIRST + 40) /* 40: Event selected in the ICU.IELSR40 register */
#define RA_IRQ_IELSR41 (RA_IRQ_FIRST + 41) /* 41: Event selected in the ICU.IELSR41 register */
#define RA_IRQ_IELSR42 (RA_IRQ_FIRST + 42) /* 42: Event selected in the ICU.IELSR42 register */
#define RA_IRQ_IELSR43 (RA_IRQ_FIRST + 43) /* 43: Event selected in the ICU.IELSR43 register */
#define RA_IRQ_IELSR44 (RA_IRQ_FIRST + 44) /* 44: Event selected in the ICU.IELSR44 register */
#define RA_IRQ_IELSR45 (RA_IRQ_FIRST + 45) /* 45: Event selected in the ICU.IELSR45 register */
#define RA_IRQ_IELSR46 (RA_IRQ_FIRST + 46) /* 46: Event selected in the ICU.IELSR46 register */
#define RA_IRQ_IELSR47 (RA_IRQ_FIRST + 47) /* 47: Event selected in the ICU.IELSR47 register */
#define RA_IRQ_IELSR48 (RA_IRQ_FIRST + 48) /* 48: Event selected in the ICU.IELSR48 register */
#define RA_IRQ_IELSR49 (RA_IRQ_FIRST + 49) /* 49: Event selected in the ICU.IELSR49 register */
#define RA_IRQ_IELSR50 (RA_IRQ_FIRST + 50) /* 50: Event selected in the ICU.IELSR50 register */
#define RA_IRQ_IELSR51 (RA_IRQ_FIRST + 51) /* 51: Event selected in the ICU.IELSR51 register */
#define RA_IRQ_IELSR52 (RA_IRQ_FIRST + 52) /* 52: Event selected in the ICU.IELSR52 register */
#define RA_IRQ_IELSR53 (RA_IRQ_FIRST + 53) /* 53: Event selected in the ICU.IELSR53 register */
#define RA_IRQ_IELSR54 (RA_IRQ_FIRST + 54) /* 54: Event selected in the ICU.IELSR54 register */
#define RA_IRQ_IELSR55 (RA_IRQ_FIRST + 55) /* 55: Event selected in the ICU.IELSR55 register */
#define RA_IRQ_IELSR56 (RA_IRQ_FIRST + 56) /* 56: Event selected in the ICU.IELSR56 register */
#define RA_IRQ_IELSR57 (RA_IRQ_FIRST + 57) /* 57: Event selected in the ICU.IELSR57 register */
#define RA_IRQ_IELSR58 (RA_IRQ_FIRST + 58) /* 58: Event selected in the ICU.IELSR58 register */
#define RA_IRQ_IELSR59 (RA_IRQ_FIRST + 59) /* 59: Event selected in the ICU.IELSR59 register */
#define RA_IRQ_IELSR60 (RA_IRQ_FIRST + 60) /* 60: Event selected in the ICU.IELSR60 register */
#define RA_IRQ_IELSR61 (RA_IRQ_FIRST + 61) /* 61: Event selected in the ICU.IELSR61 register */
#define RA_IRQ_IELSR62 (RA_IRQ_FIRST + 62) /* 62: Event selected in the ICU.IELSR62 register */
#define RA_IRQ_IELSR63 (RA_IRQ_FIRST + 63) /* 63: Event selected in the ICU.IELSR63 register */
#define RA_IRQ_IELSR64 (RA_IRQ_FIRST + 64) /* 64: Event selected in the ICU.IELSR64 register */
#define RA_IRQ_IELSR65 (RA_IRQ_FIRST + 65) /* 65: Event selected in the ICU.IELSR65 register */
#define RA_IRQ_IELSR66 (RA_IRQ_FIRST + 66) /* 66: Event selected in the ICU.IELSR66 register */
#define RA_IRQ_IELSR67 (RA_IRQ_FIRST + 67) /* 67: Event selected in the ICU.IELSR67 register */
#define RA_IRQ_IELSR68 (RA_IRQ_FIRST + 68) /* 68: Event selected in the ICU.IELSR68 register */
#define RA_IRQ_IELSR69 (RA_IRQ_FIRST + 69) /* 69: Event selected in the ICU.IELSR69 register */
#define RA_IRQ_IELSR70 (RA_IRQ_FIRST + 70) /* 70: Event selected in the ICU.IELSR70 register */
#define RA_IRQ_IELSR71 (RA_IRQ_FIRST + 71) /* 71: Event selected in the ICU.IELSR71 register */
#define RA_IRQ_IELSR72 (RA_IRQ_FIRST + 72) /* 72: Event selected in the ICU.IELSR72 register */
#define RA_IRQ_IELSR73 (RA_IRQ_FIRST + 73) /* 73: Event selected in the ICU.IELSR73 register */
#define RA_IRQ_IELSR74 (RA_IRQ_FIRST + 74) /* 74: Event selected in the ICU.IELSR74 register */
#define RA_IRQ_IELSR75 (RA_IRQ_FIRST + 75) /* 75: Event selected in the ICU.IELSR75 register */
#define RA_IRQ_IELSR76 (RA_IRQ_FIRST + 76) /* 76: Event selected in the ICU.IELSR76 register */
#define RA_IRQ_IELSR77 (RA_IRQ_FIRST + 77) /* 77: Event selected in the ICU.IELSR77 register */
#define RA_IRQ_IELSR78 (RA_IRQ_FIRST + 78) /* 78: Event selected in the ICU.IELSR78 register */
#define RA_IRQ_IELSR79 (RA_IRQ_FIRST + 79) /* 79: Event selected in the ICU.IELSR79 register */
#define RA_IRQ_IELSR80 (RA_IRQ_FIRST + 80) /* 80: Event selected in the ICU.IELSR80 register */
#define RA_IRQ_IELSR81 (RA_IRQ_FIRST + 81) /* 81: Event selected in the ICU.IELSR81 register */
#define RA_IRQ_IELSR82 (RA_IRQ_FIRST + 82) /* 82: Event selected in the ICU.IELSR82 register */
#define RA_IRQ_IELSR83 (RA_IRQ_FIRST + 83) /* 83: Event selected in the ICU.IELSR83 register */
#define RA_IRQ_IELSR84 (RA_IRQ_FIRST + 84) /* 84: Event selected in the ICU.IELSR84 register */
#define RA_IRQ_IELSR85 (RA_IRQ_FIRST + 85) /* 85: Event selected in the ICU.IELSR85 register */
#define RA_IRQ_IELSR86 (RA_IRQ_FIRST + 86) /* 86: Event selected in the ICU.IELSR86 register */
#define RA_IRQ_IELSR87 (RA_IRQ_FIRST + 87) /* 87: Event selected in the ICU.IELSR87 register */
#define RA_IRQ_IELSR88 (RA_IRQ_FIRST + 88) /* 88: Event selected in the ICU.IELSR88 register */
#define RA_IRQ_IELSR89 (RA_IRQ_FIRST + 89) /* 89: Event selected in the ICU.IELSR89 register */
#define RA_IRQ_IELSR90 (RA_IRQ_FIRST + 90) /* 90: Event selected in the ICU.IELSR90 register */
#define RA_IRQ_IELSR91 (RA_IRQ_FIRST + 91) /* 91: Event selected in the ICU.IELSR91 register */
#define RA_IRQ_IELSR92 (RA_IRQ_FIRST + 92) /* 92: Event selected in the ICU.IELSR92 register */
#define RA_IRQ_IELSR93 (RA_IRQ_FIRST + 93) /* 93: Event selected in the ICU.IELSR93 register */
#define RA_IRQ_IELSR94 (RA_IRQ_FIRST + 94) /* 94: Event selected in the ICU.IELSR94 register */
#define RA_IRQ_IELSR95 (RA_IRQ_FIRST + 95) /* 95: Event selected in the ICU.IELSR95 register */
#define RA_IRQ_NEXTINT (96)
/* SCI_B interrupt events.
*
* The ICU routes any peripheral event to any of the IELSR slots, so the
* SCI_B events are simply given fixed slots: four per channel (receive data
* full, transmit data empty, transmit end, receive error). The numbers do
* not depend on which channels a build enables, so every file that uses
* them (ra_serial.c, ra_icu.c) sees the same value. Only RA_IRQ_IELSR0 to
* RA_IRQ_IELSR23 are used; ra_attach_icu() routes the events of the enabled
* channels to their slots.
*
* RA8M1 has SCI_B0-4 and SCI_B9 (no SCI_B5-8), named SCI0-4 and SCI9 here.
*/
#define SCI0_RXI (RA_IRQ_FIRST + 0) /* Receive data full */
#define SCI0_TXI (RA_IRQ_FIRST + 1) /* Transmit data empty */
#define SCI0_TEI (RA_IRQ_FIRST + 2) /* Transmit end */
#define SCI0_ERI (RA_IRQ_FIRST + 3) /* Receive error */
#define SCI1_RXI (RA_IRQ_FIRST + 4) /* Receive data full */
#define SCI1_TXI (RA_IRQ_FIRST + 5) /* Transmit data empty */
#define SCI1_TEI (RA_IRQ_FIRST + 6) /* Transmit end */
#define SCI1_ERI (RA_IRQ_FIRST + 7) /* Receive error */
#define SCI2_RXI (RA_IRQ_FIRST + 8) /* Receive data full */
#define SCI2_TXI (RA_IRQ_FIRST + 9) /* Transmit data empty */
#define SCI2_TEI (RA_IRQ_FIRST + 10) /* Transmit end */
#define SCI2_ERI (RA_IRQ_FIRST + 11) /* Receive error */
#define SCI3_RXI (RA_IRQ_FIRST + 12) /* Receive data full */
#define SCI3_TXI (RA_IRQ_FIRST + 13) /* Transmit data empty */
#define SCI3_TEI (RA_IRQ_FIRST + 14) /* Transmit end */
#define SCI3_ERI (RA_IRQ_FIRST + 15) /* Receive error */
#define SCI4_RXI (RA_IRQ_FIRST + 16) /* Receive data full */
#define SCI4_TXI (RA_IRQ_FIRST + 17) /* Transmit data empty */
#define SCI4_TEI (RA_IRQ_FIRST + 18) /* Transmit end */
#define SCI4_ERI (RA_IRQ_FIRST + 19) /* Receive error */
#define SCI9_RXI (RA_IRQ_FIRST + 20) /* Receive data full */
#define SCI9_TXI (RA_IRQ_FIRST + 21) /* Transmit data empty */
#define SCI9_TEI (RA_IRQ_FIRST + 22) /* Transmit end */
#define SCI9_ERI (RA_IRQ_FIRST + 23) /* Receive error */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_RA8M1_RA8M1_IRQ_H */

10
arch/arm/src/cmake/armv8-m.cmake
View file

@ -76,6 +76,16 @@ elseif(CONFIG_ARCH_CORTEXM55)
if(CONFIG_ARCH_FPU)
list(APPEND PLATFORM_FLAGS -mfpu=fpv5-d16)
endif()
elseif(CONFIG_ARCH_CORTEXM85)
list(APPEND PLATFORM_FLAGS -mtune=cortex-m85)
if(CONFIG_ARM_HAVE_MVE)
list(APPEND PLATFORM_FLAGS -march=armv8.1-m.main${EXTCPUFLAGS}+mve.fp+fp.dp)
else()
list(APPEND PLATFORM_FLAGS -march=armv8.1-m.main${EXTCPUFLAGS})
endif()
if(CONFIG_ARCH_FPU)
list(APPEND PLATFORM_FLAGS -mfpu=fpv5-d16)
endif()
endif()
if(CONFIG_ARCH_FPU)

2
arch/arm/src/cmake/platform.cmake
View file

@ -38,6 +38,8 @@ elseif(CONFIG_ARCH_CORTEXM35P)
set(CMAKE_SYSTEM_PROCESSOR cortex-m35p)
elseif(CONFIG_ARCH_CORTEXM55)
set(CMAKE_SYSTEM_PROCESSOR cortex-m55)
elseif(CONFIG_ARCH_CORTEXM85)
set(CMAKE_SYSTEM_PROCESSOR cortex-m85)
elseif(CONFIG_ARCH_CORTEXA5)
set(CMAKE_SYSTEM_PROCESSOR cortex-a5)
elseif(CONFIG_ARCH_CORTEXA7)

33
arch/arm/src/ra8m1/CMakeLists.txt Normal file
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@ -0,0 +1,33 @@
# ##############################################################################
# arch/arm/src/ra8m1/CMakeLists.txt
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
set(SRCS
ra_start.c
ra_serial.c
ra_timerisr.c
ra_clockconfig.c
ra_option_setting.c
ra_irq.c
ra_lowputc.c
ra_icu.c
ra_gpio.c
ra_allocateheap.c)
target_sources(arch PRIVATE ${SRCS})

186
arch/arm/src/ra8m1/Kconfig Normal file
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@ -0,0 +1,186 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "RA Configuration Options"
choice
prompt "RA Chip Selection"
default ARCH_CHIP_R7FA8M1AHECFC
depends on ARCH_CHIP_RA8M1
config ARCH_CHIP_R7FA8M1AFECAM
bool "R7FA8M1AFECAM"
select RA_HAVE_SCI_B0
select RA_HAVE_SCI_B1
select RA_HAVE_SCI_B2
select RA_HAVE_SCI_B3
select RA_HAVE_SCI_B4
select RA_HAVE_SCI_B9
select RA8M1_FAMILY
config ARCH_CHIP_R7FA8M1AFECBD
bool "R7FA8M1AFECBD"
select RA_HAVE_SCI_B0
select RA_HAVE_SCI_B1
select RA_HAVE_SCI_B2
select RA_HAVE_SCI_B3
select RA_HAVE_SCI_B4
select RA_HAVE_SCI_B9
select RA8M1_FAMILY
config ARCH_CHIP_R7FA8M1AFECFB
bool "R7FA8M1AFECFB"
select RA_HAVE_SCI_B0
select RA_HAVE_SCI_B1
select RA_HAVE_SCI_B2
select RA_HAVE_SCI_B3
select RA_HAVE_SCI_B4
select RA_HAVE_SCI_B9
select RA8M1_FAMILY
config ARCH_CHIP_R7FA8M1AFECFC
bool "R7FA8M1AFECFC"
select RA_HAVE_SCI_B0
select RA_HAVE_SCI_B1
select RA_HAVE_SCI_B2
select RA_HAVE_SCI_B3
select RA_HAVE_SCI_B4
select RA_HAVE_SCI_B9
select RA8M1_FAMILY
config ARCH_CHIP_R7FA8M1AFECFP
bool "R7FA8M1AFECFP"
select RA_HAVE_SCI_B0
select RA_HAVE_SCI_B1
select RA_HAVE_SCI_B2
select RA_HAVE_SCI_B3
select RA_HAVE_SCI_B4
select RA_HAVE_SCI_B9
select RA8M1_FAMILY
config ARCH_CHIP_R7FA8M1AHECAM
bool "R7FA8M1AHECAM"
select RA_HAVE_SCI_B0
select RA_HAVE_SCI_B1
select RA_HAVE_SCI_B2
select RA_HAVE_SCI_B3
select RA_HAVE_SCI_B4
select RA_HAVE_SCI_B9
select RA8M1_FAMILY
config ARCH_CHIP_R7FA8M1AHECBD
bool "R7FA8M1AHECBD"
select RA_HAVE_SCI_B0
select RA_HAVE_SCI_B1
select RA_HAVE_SCI_B2
select RA_HAVE_SCI_B3
select RA_HAVE_SCI_B4
select RA_HAVE_SCI_B9
select RA8M1_FAMILY
config ARCH_CHIP_R7FA8M1AHECFB
bool "R7FA8M1AHECFB"
select RA_HAVE_SCI_B0
select RA_HAVE_SCI_B1
select RA_HAVE_SCI_B2
select RA_HAVE_SCI_B3
select RA_HAVE_SCI_B4
select RA_HAVE_SCI_B9
select RA8M1_FAMILY
config ARCH_CHIP_R7FA8M1AHECFC
bool "R7FA8M1AHECFC"
select RA_HAVE_SCI_B0
select RA_HAVE_SCI_B1
select RA_HAVE_SCI_B2
select RA_HAVE_SCI_B3
select RA_HAVE_SCI_B4
select RA_HAVE_SCI_B9
select RA8M1_FAMILY
config ARCH_CHIP_R7FA8M1AHECFP
bool "R7FA8M1AHECFP"
select RA_HAVE_SCI_B0
select RA_HAVE_SCI_B1
select RA_HAVE_SCI_B2
select RA_HAVE_SCI_B3
select RA_HAVE_SCI_B4
select RA_HAVE_SCI_B9
select RA8M1_FAMILY
endchoice # RA Chip Selection
config RA8M1_FAMILY
bool
default n
select ARCH_CORTEXM85
menu "RA8M1 Peripheral Support"
config RA_HAVE_SCI_B0
bool
default n
config RA_HAVE_SCI_B1
bool
default n
config RA_HAVE_SCI_B2
bool
default n
config RA_HAVE_SCI_B3
bool
default n
config RA_HAVE_SCI_B4
bool
default n
config RA_HAVE_SCI_B9
bool
default n
# TODO: user-facing enable options go here, one per
# RA_HAVE_* above (prompt, depends on RA_HAVE_*, select
# the driver it wires up -- see README "Kconfig draft").
config RA_SCI0_UART
bool "UART 0"
default n
depends on RA_HAVE_SCI_B0
select SCI0_SERIALDRIVER
config RA_SCI1_UART
bool "UART 1"
default n
depends on RA_HAVE_SCI_B1
select SCI1_SERIALDRIVER
config RA_SCI2_UART
bool "UART 2"
default n
depends on RA_HAVE_SCI_B2
select SCI2_SERIALDRIVER
config RA_SCI3_UART
bool "UART 3"
default n
depends on RA_HAVE_SCI_B3
select SCI3_SERIALDRIVER
config RA_SCI4_UART
bool "UART 4"
default n
depends on RA_HAVE_SCI_B4
select SCI4_SERIALDRIVER
config RA_SCI9_UART
bool "UART 9"
default n
depends on RA_HAVE_SCI_B9
select SCI9_SERIALDRIVER
endmenu # RA8M1 Peripheral Support

38
arch/arm/src/ra8m1/Make.defs Normal file
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@ -0,0 +1,38 @@
############################################################################
# arch/arm/src/ra8m1/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# The start-up, "head", file
# Common ARM and Cortex-M85 (ARMv8-M) files
include armv8-m/Make.defs
# Required RA files
CHIP_CSRCS += ra_start.c
CHIP_CSRCS += ra_clockconfig.c
CHIP_CSRCS += ra_option_setting.c
CHIP_CSRCS += ra_irq.c
CHIP_CSRCS += ra_icu.c
CHIP_CSRCS += ra_gpio.c
CHIP_CSRCS += ra_serial.c
CHIP_CSRCS += ra_lowputc.c
CHIP_CSRCS += ra_allocateheap.c
CHIP_CSRCS += ra_timerisr.c

59
arch/arm/src/ra8m1/chip.h Normal file
View file

@ -0,0 +1,59 @@
/****************************************************************************
* arch/arm/src/ra8m1/chip.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_CHIP_H
#define __ARCH_ARM_SRC_RA8M1_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip
* hardware files should then include this file for the proper setup.
*/
#include <arch/ra8m1/chip.h>
#include "hardware/ra8m1_memorymap.h"
/* Include the chip interrupt definition file */
#include <arch/ra8m1/irq.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The common ARMv8-M vector handling logic expects the number of external
* interrupts here. RA_IRQ_NEXTINT comes from the chip IRQ header (one NVIC
* vector per ICU IELSR slot).
*/
#define ARMV8M_PERIPHERAL_INTERRUPTS RA_IRQ_NEXTINT
/* The Cortex-M85 caches have 32 byte lines */
#define ARMV8M_ICACHE_LINESIZE 32
#define ARMV8M_DCACHE_LINESIZE 32
#endif /* __ARCH_ARM_SRC_RA8M1_CHIP_H */

367
arch/arm/src/ra8m1/hardware/ra8m1_elc.h Normal file
View file

@ -0,0 +1,367 @@
/****************************************************************************
* arch/arm/src/ra8m1/hardware/ra8m1_elc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ELC_H
#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ELC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define EVENT_NONE (0x000) /* Link disabled */
#define EVENT_ICU_IRQ0 (0x001) /* External pin interrupt 0 */
#define EVENT_ICU_IRQ1 (0x002) /* External pin interrupt 1 */
#define EVENT_ICU_IRQ2 (0x003) /* External pin interrupt 2 */
#define EVENT_ICU_IRQ3 (0x004) /* External pin interrupt 3 */
#define EVENT_ICU_IRQ4 (0x005) /* External pin interrupt 4 */
#define EVENT_ICU_IRQ5 (0x006) /* External pin interrupt 5 */
#define EVENT_ICU_IRQ6 (0x007) /* External pin interrupt 6 */
#define EVENT_ICU_IRQ7 (0x008) /* External pin interrupt 7 */
#define EVENT_ICU_IRQ8 (0x009) /* External pin interrupt 8 */
#define EVENT_ICU_IRQ9 (0x00A) /* External pin interrupt 9 */
#define EVENT_ICU_IRQ10 (0x00B) /* External pin interrupt 10 */
#define EVENT_ICU_IRQ11 (0x00C) /* External pin interrupt 11 */
#define EVENT_ICU_IRQ12 (0x00D) /* External pin interrupt 12 */
#define EVENT_ICU_IRQ13 (0x00E) /* External pin interrupt 13 */
#define EVENT_ICU_IRQ14 (0x00F) /* External pin interrupt 14 */
#define EVENT_ICU_IRQ15 (0x010) /* External pin interrupt 15 */
#define EVENT_DMAC0_INT (0x011) /* DMAC0 transfer end */
#define EVENT_DMAC1_INT (0x012) /* DMAC1 transfer end */
#define EVENT_DMAC2_INT (0x013) /* DMAC2 transfer end */
#define EVENT_DMAC3_INT (0x014) /* DMAC3 transfer end */
#define EVENT_DMAC4_INT (0x015) /* DMAC4 transfer end */
#define EVENT_DMAC5_INT (0x016) /* DMAC5 transfer end */
#define EVENT_DMAC6_INT (0x017) /* DMAC6 transfer end */
#define EVENT_DMAC7_INT (0x018) /* DMAC7 transfer end */
#define EVENT_DTC_END (0x021) /* DTC transfer end */
#define EVENT_DTC_COMPLETE (0x022) /* DTC transfer complete */
#define EVENT_DMA_TRANSERR (0x027) /* DMA/DTC transfer error */
#define EVENT_DBG_CTIIRQ0 (0x029) /* Coresight Crosstrigger Event */
#define EVENT_DBG_CTIIRQ1 (0x02A) /* Coresight Crosstrigger Event */
#define EVENT_DBG_JBRXI (0x02B) /* JB RXI */
#define EVENT_FCU_FIFERR (0x030) /* Flash access error interrupt */
#define EVENT_FCU_FRDYI (0x031) /* Flash ready interrupt */
#define EVENT_LVD_LVD1 (0x038) /* Voltage monitor 1 interrupt */
#define EVENT_LVD_LVD2 (0x039) /* Voltage monitor 2 interrupt */
#define EVENT_VBATT_TADI (0x03D) /* VBATT Tamper Detection */
#define EVENT_CGC_MOSC_STOP (0x03E) /* Main Clock oscillation stop */
#define EVENT_ULPT0_INT (0x040) /* ULPT0 Underflow */
#define EVENT_ULPT0_COMPARE_A (0x041) /* ULPT0 Compare match A */
#define EVENT_ULPT0_COMPARE_B (0x042) /* ULPT0 Compare match B */
#define EVENT_ULPT1_INT (0x043) /* ULPT1 Underflow */
#define EVENT_ULPT1_COMPARE_A (0x044) /* ULPT1 Compare match A */
#define EVENT_ULPT1_COMPARE_B (0x045) /* ULPT1 Compare match B */
#define EVENT_AGT0_INT (0x046) /* AGT interrupt */
#define EVENT_AGT0_COMPARE_A (0x047) /* Compare match A */
#define EVENT_AGT0_COMPARE_B (0x048) /* Compare match B */
#define EVENT_AGT1_INT (0x049) /* AGT interrupt */
#define EVENT_AGT1_COMPARE_A (0x04A) /* Compare match A */
#define EVENT_AGT1_COMPARE_B (0x04B) /* Compare match B */
#define EVENT_IWDT_UNDERFLOW (0x052) /* IWDT underflow */
#define EVENT_WDT0_UNDERFLOW (0x053) /* WDT0 underflow */
#define EVENT_RTC_ALARM (0x055) /* Alarm interrupt */
#define EVENT_RTC_PERIOD (0x056) /* Periodic interrupt */
#define EVENT_RTC_CARRY (0x057) /* Carry interrupt */
#define EVENT_USBFS_FIFO_0 (0x058) /* DMA/DTC transfer request 0 */
#define EVENT_USBFS_FIFO_1 (0x059) /* DMA/DTC transfer request 1 */
#define EVENT_USBFS_INT (0x05A) /* USBFS interrupt */
#define EVENT_USBFS_RESUME (0x05B) /* USBFS resume interrupt */
#define EVENT_IIC0_RXI (0x05C) /* Receive data full */
#define EVENT_IIC0_TXI (0x05D) /* Transmit data empty */
#define EVENT_IIC0_TEI (0x05E) /* Transmit end */
#define EVENT_IIC0_ERI (0x05F) /* Transfer error */
#define EVENT_IIC0_WUI (0x060) /* Wakeup interrupt */
#define EVENT_IIC1_RXI (0x061) /* Receive data full */
#define EVENT_IIC1_TXI (0x062) /* Transmit data empty */
#define EVENT_IIC1_TEI (0x063) /* Transmit end */
#define EVENT_IIC1_ERI (0x064) /* Transfer error */
#define EVENT_SDHIMMC0_ACCS (0x06B) /* Card access */
#define EVENT_SDHIMMC0_SDIO (0x06C) /* SDIO access */
#define EVENT_SDHIMMC0_CARD (0x06D) /* Card detect */
#define EVENT_SDHIMMC0_DMA_REQ (0x06E) /* DMA transfer request */
#define EVENT_SDHIMMC1_ACCS (0x06F) /* Card access */
#define EVENT_SDHIMMC1_SDIO (0x070) /* SDIO access */
#define EVENT_SDHIMMC1_CARD (0x071) /* Card detect */
#define EVENT_SDHIMMC1_DMA_REQ (0x072) /* DMA transfer request */
#define EVENT_SSI0_TXI (0x073) /* Transmit data empty */
#define EVENT_SSI0_RXI (0x074) /* Receive data full */
#define EVENT_SSI0_INT (0x076) /* Error interrupt */
#define EVENT_SSI1_TXI (0x079) /* Receive data full/Transmit data empty */
#define EVENT_SSI1_RXI (0x079) /* Receive data full/Transmit data empty */
#define EVENT_SSI1_INT (0x07A) /* Error interrupt */
#define EVENT_ACMPHS0_INT (0x07B) /* High Speed Comparator channel 0 interrupt */
#define EVENT_ACMPHS1_INT (0x07C) /* High Speed Comparator channel 1 interrupt */
#define EVENT_ELC_SOFTWARE_EVENT_0 (0x083) /* Software event 0 */
#define EVENT_ELC_SOFTWARE_EVENT_1 (0x084) /* Software event 1 */
#define EVENT_IOPORT_EVENT_1 (0x088) /* Port 1 event */
#define EVENT_IOPORT_EVENT_2 (0x089) /* Port 2 event */
#define EVENT_IOPORT_EVENT_3 (0x08A) /* Port 3 event */
#define EVENT_IOPORT_EVENT_4 (0x08B) /* Port 4 event */
#define EVENT_CAC_FREQUENCY_ERROR (0x08C) /* Frequency error interrupt */
#define EVENT_CAC_MEASUREMENT_END (0x08D) /* Measurement end interrupt */
#define EVENT_CAC_OVERFLOW (0x08E) /* Overflow interrupt */
#define EVENT_POEG0_EVENT (0x08F) /* Port Output disable 0 interrupt */
#define EVENT_POEG1_EVENT (0x090) /* Port Output disable 1 interrupt */
#define EVENT_POEG2_EVENT (0x091) /* Port Output disable 2 interrupt */
#define EVENT_POEG3_EVENT (0x092) /* Port Output disable 3 interrupt */
#define EVENT_OPS_UVW_EDGE (0x0A0) /* UVW edge event */
#define EVENT_GPT0_CAPTURE_COMPARE_A (0x0A1) /* Capture/Compare match A */
#define EVENT_GPT0_CAPTURE_COMPARE_B (0x0A2) /* Capture/Compare match B */
#define EVENT_GPT0_COMPARE_C (0x0A3) /* Compare match C */
#define EVENT_GPT0_COMPARE_D (0x0A4) /* Compare match D */
#define EVENT_GPT0_COMPARE_E (0x0A5) /* Compare match E */
#define EVENT_GPT0_COMPARE_F (0x0A6) /* Compare match F */
#define EVENT_GPT0_COUNTER_OVERFLOW (0x0A7) /* Overflow */
#define EVENT_GPT0_COUNTER_UNDERFLOW (0x0A8) /* Underflow */
#define EVENT_GPT0_PC (0x0A9) /* Period count function finish */
#define EVENT_GPT1_CAPTURE_COMPARE_A (0x0AA) /* Capture/Compare match A */
#define EVENT_GPT1_CAPTURE_COMPARE_B (0x0AB) /* Capture/Compare match B */
#define EVENT_GPT1_COMPARE_C (0x0AC) /* Compare match C */
#define EVENT_GPT1_COMPARE_D (0x0AD) /* Compare match D */
#define EVENT_GPT1_COMPARE_E (0x0AE) /* Compare match E */
#define EVENT_GPT1_COMPARE_F (0x0AF) /* Compare match F */
#define EVENT_GPT1_COUNTER_OVERFLOW (0x0B0) /* Overflow */
#define EVENT_GPT1_COUNTER_UNDERFLOW (0x0B1) /* Underflow */
#define EVENT_GPT1_PC (0x0B2) /* Period count function finish */
#define EVENT_GPT2_CAPTURE_COMPARE_A (0x0B3) /* Capture/Compare match A */
#define EVENT_GPT2_CAPTURE_COMPARE_B (0x0B4) /* Capture/Compare match B */
#define EVENT_GPT2_COMPARE_C (0x0B5) /* Compare match C */
#define EVENT_GPT2_COMPARE_D (0x0B6) /* Compare match D */
#define EVENT_GPT2_COMPARE_E (0x0B7) /* Compare match E */
#define EVENT_GPT2_COMPARE_F (0x0B8) /* Compare match F */
#define EVENT_GPT2_COUNTER_OVERFLOW (0x0B9) /* Overflow */
#define EVENT_GPT2_COUNTER_UNDERFLOW (0x0BA) /* Underflow */
#define EVENT_GPT2_PC (0x0BB) /* Period count function finish */
#define EVENT_GPT3_CAPTURE_COMPARE_A (0x0BC) /* Capture/Compare match A */
#define EVENT_GPT3_CAPTURE_COMPARE_B (0x0BD) /* Capture/Compare match B */
#define EVENT_GPT3_COMPARE_C (0x0BE) /* Compare match C */
#define EVENT_GPT3_COMPARE_D (0x0BF) /* Compare match D */
#define EVENT_GPT3_COMPARE_E (0x0C0) /* Compare match E */
#define EVENT_GPT3_COMPARE_F (0x0C1) /* Compare match F */
#define EVENT_GPT3_COUNTER_OVERFLOW (0x0C2) /* Overflow */
#define EVENT_GPT3_COUNTER_UNDERFLOW (0x0C3) /* Underflow */
#define EVENT_GPT3_PC (0x0C4) /* Period count function finish */
#define EVENT_GPT4_CAPTURE_COMPARE_A (0x0C5) /* Capture/Compare match A */
#define EVENT_GPT4_CAPTURE_COMPARE_B (0x0C6) /* Capture/Compare match B */
#define EVENT_GPT4_COMPARE_C (0x0C7) /* Compare match C */
#define EVENT_GPT4_COMPARE_D (0x0C8) /* Compare match D */
#define EVENT_GPT4_COMPARE_E (0x0C9) /* Compare match E */
#define EVENT_GPT4_COMPARE_F (0x0CA) /* Compare match F */
#define EVENT_GPT4_COUNTER_OVERFLOW (0x0CB) /* Overflow */
#define EVENT_GPT4_COUNTER_UNDERFLOW (0x0CC) /* Underflow */
#define EVENT_GPT5_CAPTURE_COMPARE_A (0x0CE) /* Capture/Compare match A */
#define EVENT_GPT5_CAPTURE_COMPARE_B (0x0CF) /* Capture/Compare match B */
#define EVENT_GPT5_COMPARE_C (0x0D0) /* Compare match C */
#define EVENT_GPT5_COMPARE_D (0x0D1) /* Compare match D */
#define EVENT_GPT5_COMPARE_E (0x0D2) /* Compare match E */
#define EVENT_GPT5_COMPARE_F (0x0D3) /* Compare match F */
#define EVENT_GPT5_COUNTER_OVERFLOW (0x0D4) /* Overflow */
#define EVENT_GPT5_COUNTER_UNDERFLOW (0x0D5) /* Underflow */
#define EVENT_GPT6_CAPTURE_COMPARE_A (0x0D7) /* Capture/Compare match A */
#define EVENT_GPT6_CAPTURE_COMPARE_B (0x0D8) /* Capture/Compare match B */
#define EVENT_GPT6_COMPARE_C (0x0D9) /* Compare match C */
#define EVENT_GPT6_COMPARE_D (0x0DA) /* Compare match D */
#define EVENT_GPT6_COMPARE_E (0x0DB) /* Compare match E */
#define EVENT_GPT6_COMPARE_F (0x0DC) /* Compare match F */
#define EVENT_GPT6_COUNTER_OVERFLOW (0x0DD) /* Overflow */
#define EVENT_GPT6_COUNTER_UNDERFLOW (0x0DE) /* Underflow */
#define EVENT_GPT7_CAPTURE_COMPARE_A (0x0E0) /* Capture/Compare match A */
#define EVENT_GPT7_CAPTURE_COMPARE_B (0x0E1) /* Capture/Compare match B */
#define EVENT_GPT7_COMPARE_C (0x0E2) /* Compare match C */
#define EVENT_GPT7_COMPARE_D (0x0E3) /* Compare match D */
#define EVENT_GPT7_COMPARE_E (0x0E4) /* Compare match E */
#define EVENT_GPT7_COMPARE_F (0x0E5) /* Compare match F */
#define EVENT_GPT7_COUNTER_OVERFLOW (0x0E6) /* Overflow */
#define EVENT_GPT7_COUNTER_UNDERFLOW (0x0E7) /* Underflow */
#define EVENT_GPT8_CAPTURE_COMPARE_A (0x0E9) /* Capture/Compare match A */
#define EVENT_GPT8_CAPTURE_COMPARE_B (0x0EA) /* Capture/Compare match B */
#define EVENT_GPT8_COMPARE_C (0x0EB) /* Compare match C */
#define EVENT_GPT8_COMPARE_D (0x0EC) /* Compare match D */
#define EVENT_GPT8_COMPARE_E (0x0ED) /* Compare match E */
#define EVENT_GPT8_COMPARE_F (0x0EE) /* Compare match F */
#define EVENT_GPT8_COUNTER_OVERFLOW (0x0EF) /* Overflow */
#define EVENT_GPT8_COUNTER_UNDERFLOW (0x0F0) /* Underflow */
#define EVENT_GPT8_PC (0x0F1) /* Period count function finish */
#define EVENT_GPT9_CAPTURE_COMPARE_A (0x0F2) /* Capture/Compare match A */
#define EVENT_GPT9_CAPTURE_COMPARE_B (0x0F3) /* Capture/Compare match B */
#define EVENT_GPT9_COMPARE_C (0x0F4) /* Compare match C */
#define EVENT_GPT9_COMPARE_D (0x0F5) /* Compare match D */
#define EVENT_GPT9_COMPARE_E (0x0F6) /* Compare match E */
#define EVENT_GPT9_COMPARE_F (0x0F7) /* Compare match F */
#define EVENT_GPT9_COUNTER_OVERFLOW (0x0F8) /* Overflow */
#define EVENT_GPT9_COUNTER_UNDERFLOW (0x0F9) /* Underflow */
#define EVENT_GPT9_PC (0x0FA) /* Period count function finish */
#define EVENT_GPT10_CAPTURE_COMPARE_A (0x0FB) /* Capture/Compare match A */
#define EVENT_GPT10_CAPTURE_COMPARE_B (0x0FC) /* Capture/Compare match B */
#define EVENT_GPT10_COMPARE_C (0x0FD) /* Compare match C */
#define EVENT_GPT10_COMPARE_D (0x0FE) /* Compare match D */
#define EVENT_GPT10_COMPARE_E (0x0FF) /* Compare match E */
#define EVENT_GPT10_COMPARE_F (0x100) /* Compare match F */
#define EVENT_GPT10_COUNTER_OVERFLOW (0x101) /* Overflow */
#define EVENT_GPT10_COUNTER_UNDERFLOW (0x102) /* Underflow */
#define EVENT_GPT10_PC (0x103) /* Period count function finish */
#define EVENT_GPT11_CAPTURE_COMPARE_A (0x104) /* Capture/Compare match A */
#define EVENT_GPT11_CAPTURE_COMPARE_B (0x105) /* Capture/Compare match B */
#define EVENT_GPT11_COMPARE_C (0x106) /* Compare match C */
#define EVENT_GPT11_COMPARE_D (0x107) /* Compare match D */
#define EVENT_GPT11_COMPARE_E (0x108) /* Compare match E */
#define EVENT_GPT11_COMPARE_F (0x109) /* Compare match F */
#define EVENT_GPT11_COUNTER_OVERFLOW (0x10A) /* Overflow */
#define EVENT_GPT11_COUNTER_UNDERFLOW (0x10B) /* Underflow */
#define EVENT_GPT12_CAPTURE_COMPARE_A (0x10D) /* Capture/Compare match A */
#define EVENT_GPT12_CAPTURE_COMPARE_B (0x10E) /* Capture/Compare match B */
#define EVENT_GPT12_COMPARE_C (0x10F) /* Compare match C */
#define EVENT_GPT12_COMPARE_D (0x110) /* Compare match D */
#define EVENT_GPT12_COMPARE_E (0x111) /* Compare match E */
#define EVENT_GPT12_COMPARE_F (0x112) /* Compare match F */
#define EVENT_GPT12_COUNTER_OVERFLOW (0x113) /* Overflow */
#define EVENT_GPT12_COUNTER_UNDERFLOW (0x114) /* Underflow */
#define EVENT_GPT13_CAPTURE_COMPARE_A (0x116) /* Capture/Compare match A */
#define EVENT_GPT13_CAPTURE_COMPARE_B (0x117) /* Capture/Compare match B */
#define EVENT_GPT13_COMPARE_C (0x118) /* Compare match C */
#define EVENT_GPT13_COMPARE_D (0x119) /* Compare match D */
#define EVENT_GPT13_COMPARE_E (0x11A) /* Compare match E */
#define EVENT_GPT13_COMPARE_F (0x11B) /* Compare match F */
#define EVENT_GPT13_COUNTER_OVERFLOW (0x11C) /* Overflow */
#define EVENT_GPT13_COUNTER_UNDERFLOW (0x11D) /* Underflow */
#define EVENT_EDMAC0_EINT (0x120) /* EDMAC 0 interrupt */
#define EVENT_USBHS_FIFO_0 (0x121) /* DMA transfer request 0 */
#define EVENT_USBHS_FIFO_1 (0x122) /* DMA transfer request 1 */
#define EVENT_USBHS_USB_INT_RESUME (0x123) /* USBHS interrupt */
#define EVENT_SCI0_RXI (0x124) /* Receive data full */
#define EVENT_SCI0_TXI (0x125) /* Transmit data empty */
#define EVENT_SCI0_TEI (0x126) /* Transmit end */
#define EVENT_SCI0_ERI (0x127) /* Receive error */
#define EVENT_SCI0_AED (0x128) /* Active edge detection */
#define EVENT_SCI0_BFD (0x129) /* Break field detection */
#define EVENT_SCI0_AM (0x12A) /* Address match event */
#define EVENT_SCI1_RXI (0x12B) /* Receive data full */
#define EVENT_SCI1_TXI (0x12C) /* Transmit data empty */
#define EVENT_SCI1_TEI (0x12D) /* Transmit end */
#define EVENT_SCI1_ERI (0x12E) /* Receive error */
#define EVENT_SCI1_AED (0x12F) /* Active edge detection */
#define EVENT_SCI1_BFD (0x130) /* Break field detection */
#define EVENT_SCI1_AM (0x131) /* Address match event */
#define EVENT_SCI2_RXI (0x132) /* Receive data full */
#define EVENT_SCI2_TXI (0x133) /* Transmit data empty */
#define EVENT_SCI2_TEI (0x134) /* Transmit end */
#define EVENT_SCI2_ERI (0x135) /* Receive error */
#define EVENT_SCI2_AM (0x138) /* Address match event */
#define EVENT_SCI3_RXI (0x139) /* Receive data full */
#define EVENT_SCI3_TXI (0x13A) /* Transmit data empty */
#define EVENT_SCI3_TEI (0x13B) /* Transmit end */
#define EVENT_SCI3_ERI (0x13C) /* Receive error */
#define EVENT_SCI3_AM (0x13F) /* Address match event */
#define EVENT_SCI4_RXI (0x140) /* Receive data full */
#define EVENT_SCI4_TXI (0x141) /* Transmit data empty */
#define EVENT_SCI4_TEI (0x142) /* Transmit end */
#define EVENT_SCI4_ERI (0x143) /* Receive error */
#define EVENT_SCI4_AM (0x146) /* Address match event */
#define EVENT_SCI9_RXI (0x163) /* Receive data full */
#define EVENT_SCI9_TXI (0x164) /* Transmit data empty */
#define EVENT_SCI9_TEI (0x165) /* Transmit end */
#define EVENT_SCI9_ERI (0x166) /* Receive error */
#define EVENT_SCI9_AM (0x169) /* Address match event */
#define EVENT_SPI0_RXI (0x178) /* Receive buffer full */
#define EVENT_SPI0_TXI (0x179) /* Transmit buffer empty */
#define EVENT_SPI0_IDLE (0x17A) /* Idle */
#define EVENT_SPI0_ERI (0x17B) /* Error */
#define EVENT_SPI0_TEI (0x17C) /* Transmission complete event */
#define EVENT_SPI1_RXI (0x17D) /* Receive buffer full */
#define EVENT_SPI1_TXI (0x17E) /* Transmit buffer empty */
#define EVENT_SPI1_IDLE (0x17F) /* Idle */
#define EVENT_SPI1_ERI (0x180) /* Error */
#define EVENT_SPI1_TEI (0x181) /* Transmission complete event */
#define EVENT_XSPI_ERR (0x182) /* xSPI Error */
#define EVENT_XSPI_CMP (0x183) /* xSPI Complete */
#define EVENT_CAN_RXF (0x185) /* Global receive FIFO interrupt */
#define EVENT_CAN_GLERR (0x186) /* Global error */
#define EVENT_CAN0_DMAREQ0 (0x187) /* RX fifo DMA request 0 */
#define EVENT_CAN0_DMAREQ1 (0x188) /* RX fifo DMA request 1 */
#define EVENT_CAN1_DMAREQ0 (0x18B) /* RX fifo DMA request 0 */
#define EVENT_CAN1_DMAREQ1 (0x18C) /* RX fifo DMA request 1 */
#define EVENT_CAN0_TX (0x18F) /* Transmit interrupt */
#define EVENT_CAN0_CHERR (0x190) /* Channel error */
#define EVENT_CAN0_COMFRX (0x191) /* Common FIFO receive interrupt */
#define EVENT_CAN0_CF_DMAREQ (0x192) /* Channel DMA request */
#define EVENT_CAN0_RXMB (0x193) /* Receive message buffer interrupt */
#define EVENT_CAN1_TX (0x194) /* Transmit interrupt */
#define EVENT_CAN1_CHERR (0x195) /* Channel error */
#define EVENT_CAN1_COMFRX (0x196) /* Common FIFO receive interrupt */
#define EVENT_CAN1_CF_DMAREQ (0x197) /* Channel DMA request */
#define EVENT_CAN1_RXMB (0x198) /* Receive message buffer interrupt */
#define EVENT_CAN0_MRAM_ERI (0x19B) /* CANFD0 ECC error */
#define EVENT_CAN1_MRAM_ERI (0x19C) /* CANFD1 ECC error */
#define EVENT_I3C0_RESPONSE (0x19D) /* Response status buffer full */
#define EVENT_I3C0_COMMAND (0x19E) /* Command buffer empty */
#define EVENT_I3C0_IBI (0x19F) /* IBI status buffer full */
#define EVENT_I3C0_RX (0x1A0) /* Receive */
#define EVENT_IICB0_RXI (0x1A0) /* Receive */
#define EVENT_I3C0_TX (0x1A1) /* Transmit */
#define EVENT_IICB0_TXI (0x1A1) /* Transmit */
#define EVENT_I3C0_RCV_STATUS (0x1A2) /* Receive status buffer full */
#define EVENT_I3C0_HRESP (0x1A3) /* High priority response queue full */
#define EVENT_I3C0_HCMD (0x1A4) /* High priority command queue empty */
#define EVENT_I3C0_HRX (0x1A5) /* High priority rx data buffer full */
#define EVENT_I3C0_HTX (0x1A6) /* High priority tx data buffer empty */
#define EVENT_I3C0_TEND (0x1A7) /* Transmit end */
#define EVENT_IICB0_TEI (0x1A7) /* Transmit end */
#define EVENT_I3C0_EEI (0x1A8) /* Error */
#define EVENT_IICB0_ERI (0x1A8) /* Error */
#define EVENT_I3C0_STEV (0x1A9) /* Synchronous timing */
#define EVENT_I3C0_MREFOVF (0x1AA) /* MREF counter overflow */
#define EVENT_I3C0_MREFCPT (0x1AB) /* MREF capture */
#define EVENT_I3C0_AMEV (0x1AC) /* Additional master-initiated bus event */
#define EVENT_I3C0_WU (0x1AD) /* Wake-up Condition Detection interrupt */
#define EVENT_ADC0_SCAN_END (0x1AE) /* End of A/D scanning operation */
#define EVENT_ADC0_SCAN_END_B (0x1AF) /* A/D scan end interrupt for group B */
#define EVENT_ADC0_WINDOW_A (0x1B0) /* Window A Compare match interrupt */
#define EVENT_ADC0_WINDOW_B (0x1B1) /* Window B Compare match interrupt */
#define EVENT_ADC0_COMPARE_MATCH (0x1B2) /* Compare match */
#define EVENT_ADC0_COMPARE_MISMATCH (0x1B3) /* Compare mismatch */
#define EVENT_ADC1_SCAN_END (0x1B4) /* End of A/D scanning operation */
#define EVENT_ADC1_SCAN_END_B (0x1B5) /* A/D scan end interrupt for group B */
#define EVENT_ADC1_WINDOW_A (0x1B6) /* Window A Compare match interrupt */
#define EVENT_ADC1_WINDOW_B (0x1B7) /* Window B Compare match interrupt */
#define EVENT_ADC1_COMPARE_MATCH (0x1B8) /* Compare match */
#define EVENT_ADC1_COMPARE_MISMATCH (0x1B9) /* Compare mismatch */
#define EVENT_DOC_INT (0x1BA) /* Data operation circuit interrupt */
#define EVENT_RSIP_TADI (0x1BC) /* RSIP Tamper Detection */
#define EVENT_CEU_CEUI (0x1DA) /* CEU interrupt */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ELC_H */

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/****************************************************************************
* arch/arm/src/ra8m1/hardware/ra8m1_fcache.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_FCACHE_H
#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_FCACHE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/ra8m1_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define R_FCACHE_FCACHEE_OFFSET 0x0000 /* Flash Cache Enable Register (16-bits) */
#define R_FCACHE_FCACHEIV_OFFSET 0x0004 /* Flash Cache Invalidate Register (16-bits) */
#define R_FCACHE_FLWT_OFFSET 0x001c /* Flash Wait Cycle Register (8-bits) */
#define R_FCACHE_FSAR_OFFSET 0x0040 /* Flash Security Attribution Register (16-bits) */
/* Register Addresses *******************************************************/
/* FCACHE Registers */
#define R_FCACHE_FCACHEE (R_FCACHE_BASE + R_FCACHE_FCACHEE_OFFSET)
#define R_FCACHE_FCACHEIV (R_FCACHE_BASE + R_FCACHE_FCACHEIV_OFFSET)
#define R_FCACHE_FLWT (R_FCACHE_BASE + R_FCACHE_FLWT_OFFSET)
#define R_FCACHE_FSAR (R_FCACHE_BASE + R_FCACHE_FSAR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Flash Cache Enable Register (16-bits) ************************************/
#define R_FCACHE_FCACHEE_FCACHEEN (1 << 0) /* 01: Flash Cache Enable */
/* Flash Cache Invalidate Register (16-bits) ********************************/
#define R_FCACHE_FCACHEIV_FCACHEIV (1 << 0) /* 01: Flash Cache Invalidate */
/* Flash Wait Cycle Register (8-bits) ***************************************/
#define R_FCACHE_FLWT_FLWT_SHIFT (0)
#define R_FCACHE_FLWT_FLWT_MASK (0x7)
# define R_FCACHE_FLWT_FLWT_V0_WAIT_ICLK_48MHZ (0 << R_FCACHE_FLWT_FLWT_SHIFT) /* 0 wait (ICLK <= 48MHz) */
# define R_FCACHE_FLWT_FLWT_V001 (1 << R_FCACHE_FLWT_FLWT_SHIFT) /* 1 wait (48MHz < ICLK <= 96MHz) */
# define R_FCACHE_FLWT_FLWT_V010 (2 << R_FCACHE_FLWT_FLWT_SHIFT) /* 2 waits (96MHz < ICLK <= 144MHz) */
# define R_FCACHE_FLWT_FLWT_V011 (3 << R_FCACHE_FLWT_FLWT_SHIFT) /* 3 waits (144Hz < ICLK <= 192MHz) */
# define R_FCACHE_FLWT_FLWT_V100 (4 << R_FCACHE_FLWT_FLWT_SHIFT) /* 4 waits (192Hz < ICLK <= 240MHz) */
/* Flash Security Attribution Register (16-bits) ****************************/
#define R_FCACHE_FSAR_FLWTSA (1 << 0) /* 01: FLWT Security Attribution */
#define R_FCACHE_FSAR_FCACHEENSA (1 << 1) /* 02: FCHACHEEN Security Attribution */
#define R_FCACHE_FSAR_FCKMHZSA (1 << 8) /* 100: FCKMHZ Security Attribution */
#define R_FCACHE_FSAR_FACICOMISA (1 << 9) /* 200: FACI command Issuing Security Attribution */
#define R_FCACHE_FSAR_FACICOMRSA (1 << 10) /* 400: FACI command Registers Security Attribution */
#define R_FCACHE_FSAR_FACITRSA (1 << 11) /* 800: FACI transfer Security Attribution */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_FCACHE_H */

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/****************************************************************************
* arch/arm/src/ra8m1/hardware/ra8m1_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_GPIO_H
#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/ra8m1_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define R_GPIO_PCNTR1_OFFSET 0x0000 /* Port Control Register 1 (32-bits) */
#define R_GPIO_PDR_OFFSET 0x0000 /* Data direction register (16-bits) */
#define R_GPIO_PODR_OFFSET 0x0002 /* Output data register (16-bits) */
#define R_GPIO_PCNTR2_OFFSET 0x0004 /* Port Control Register 2 (32-bits) */
#define R_GPIO_PIDR_OFFSET 0x0004 /* Input data register (16-bits) */
#define R_GPIO_EIDR_OFFSET 0x0006 /* Port Event Input Data register (16-bits) */
#define R_GPIO_PCNTR3_OFFSET 0x0008 /* Port Control Register 3 (32-bits) */
#define R_GPIO_POSR_OFFSET 0x0008 /* Output set register (16-bits) */
#define R_GPIO_PORR_OFFSET 0x000a /* Output reset register (16-bits) */
#define R_GPIO_PCNTR4_OFFSET 0x000c /* Port Control Register 4 (32-bits) */
#define R_GPIO_EOSR_OFFSET 0x000c /* Event output reset register (16-bits) */
#define R_GPIO_EORR_OFFSET 0x000e /* Event output set register (16-bits) */
/* Register Addresses *******************************************************/
/* PORT0 Registers (subset: 9 of 12 registers) */
#define R_PORT0_PCNTR1 (R_PORT0_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORT0_PDR (R_PORT0_BASE + R_GPIO_PDR_OFFSET)
#define R_PORT0_PODR (R_PORT0_BASE + R_GPIO_PODR_OFFSET)
#define R_PORT0_PCNTR2 (R_PORT0_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORT0_PIDR (R_PORT0_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORT0_EIDR (R_PORT0_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORT0_PCNTR3 (R_PORT0_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORT0_POSR (R_PORT0_BASE + R_GPIO_POSR_OFFSET)
#define R_PORT0_PORR (R_PORT0_BASE + R_GPIO_PORR_OFFSET)
/* PORT1 Registers */
#define R_PORT1_PCNTR1 (R_PORT1_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORT1_PDR (R_PORT1_BASE + R_GPIO_PDR_OFFSET)
#define R_PORT1_PODR (R_PORT1_BASE + R_GPIO_PODR_OFFSET)
#define R_PORT1_PCNTR2 (R_PORT1_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORT1_PIDR (R_PORT1_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORT1_EIDR (R_PORT1_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORT1_PCNTR3 (R_PORT1_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORT1_POSR (R_PORT1_BASE + R_GPIO_POSR_OFFSET)
#define R_PORT1_PORR (R_PORT1_BASE + R_GPIO_PORR_OFFSET)
#define R_PORT1_PCNTR4 (R_PORT1_BASE + R_GPIO_PCNTR4_OFFSET)
#define R_PORT1_EOSR (R_PORT1_BASE + R_GPIO_EOSR_OFFSET)
#define R_PORT1_EORR (R_PORT1_BASE + R_GPIO_EORR_OFFSET)
/* PORT2 Registers */
#define R_PORT2_PCNTR1 (R_PORT2_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORT2_PDR (R_PORT2_BASE + R_GPIO_PDR_OFFSET)
#define R_PORT2_PODR (R_PORT2_BASE + R_GPIO_PODR_OFFSET)
#define R_PORT2_PCNTR2 (R_PORT2_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORT2_PIDR (R_PORT2_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORT2_EIDR (R_PORT2_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORT2_PCNTR3 (R_PORT2_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORT2_POSR (R_PORT2_BASE + R_GPIO_POSR_OFFSET)
#define R_PORT2_PORR (R_PORT2_BASE + R_GPIO_PORR_OFFSET)
#define R_PORT2_PCNTR4 (R_PORT2_BASE + R_GPIO_PCNTR4_OFFSET)
#define R_PORT2_EOSR (R_PORT2_BASE + R_GPIO_EOSR_OFFSET)
#define R_PORT2_EORR (R_PORT2_BASE + R_GPIO_EORR_OFFSET)
/* PORT3 Registers */
#define R_PORT3_PCNTR1 (R_PORT3_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORT3_PDR (R_PORT3_BASE + R_GPIO_PDR_OFFSET)
#define R_PORT3_PODR (R_PORT3_BASE + R_GPIO_PODR_OFFSET)
#define R_PORT3_PCNTR2 (R_PORT3_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORT3_PIDR (R_PORT3_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORT3_EIDR (R_PORT3_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORT3_PCNTR3 (R_PORT3_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORT3_POSR (R_PORT3_BASE + R_GPIO_POSR_OFFSET)
#define R_PORT3_PORR (R_PORT3_BASE + R_GPIO_PORR_OFFSET)
#define R_PORT3_PCNTR4 (R_PORT3_BASE + R_GPIO_PCNTR4_OFFSET)
#define R_PORT3_EOSR (R_PORT3_BASE + R_GPIO_EOSR_OFFSET)
#define R_PORT3_EORR (R_PORT3_BASE + R_GPIO_EORR_OFFSET)
/* PORT4 Registers */
#define R_PORT4_PCNTR1 (R_PORT4_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORT4_PDR (R_PORT4_BASE + R_GPIO_PDR_OFFSET)
#define R_PORT4_PODR (R_PORT4_BASE + R_GPIO_PODR_OFFSET)
#define R_PORT4_PCNTR2 (R_PORT4_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORT4_PIDR (R_PORT4_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORT4_EIDR (R_PORT4_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORT4_PCNTR3 (R_PORT4_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORT4_POSR (R_PORT4_BASE + R_GPIO_POSR_OFFSET)
#define R_PORT4_PORR (R_PORT4_BASE + R_GPIO_PORR_OFFSET)
#define R_PORT4_PCNTR4 (R_PORT4_BASE + R_GPIO_PCNTR4_OFFSET)
#define R_PORT4_EOSR (R_PORT4_BASE + R_GPIO_EOSR_OFFSET)
#define R_PORT4_EORR (R_PORT4_BASE + R_GPIO_EORR_OFFSET)
/* PORT5 Registers (subset: 9 of 12 registers) */
#define R_PORT5_PCNTR1 (R_PORT5_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORT5_PDR (R_PORT5_BASE + R_GPIO_PDR_OFFSET)
#define R_PORT5_PODR (R_PORT5_BASE + R_GPIO_PODR_OFFSET)
#define R_PORT5_PCNTR2 (R_PORT5_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORT5_PIDR (R_PORT5_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORT5_EIDR (R_PORT5_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORT5_PCNTR3 (R_PORT5_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORT5_POSR (R_PORT5_BASE + R_GPIO_POSR_OFFSET)
#define R_PORT5_PORR (R_PORT5_BASE + R_GPIO_PORR_OFFSET)
/* PORT6 Registers (subset: 9 of 12 registers) */
#define R_PORT6_PCNTR1 (R_PORT6_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORT6_PDR (R_PORT6_BASE + R_GPIO_PDR_OFFSET)
#define R_PORT6_PODR (R_PORT6_BASE + R_GPIO_PODR_OFFSET)
#define R_PORT6_PCNTR2 (R_PORT6_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORT6_PIDR (R_PORT6_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORT6_EIDR (R_PORT6_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORT6_PCNTR3 (R_PORT6_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORT6_POSR (R_PORT6_BASE + R_GPIO_POSR_OFFSET)
#define R_PORT6_PORR (R_PORT6_BASE + R_GPIO_PORR_OFFSET)
/* PORT7 Registers (subset: 9 of 12 registers) */
#define R_PORT7_PCNTR1 (R_PORT7_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORT7_PDR (R_PORT7_BASE + R_GPIO_PDR_OFFSET)
#define R_PORT7_PODR (R_PORT7_BASE + R_GPIO_PODR_OFFSET)
#define R_PORT7_PCNTR2 (R_PORT7_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORT7_PIDR (R_PORT7_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORT7_EIDR (R_PORT7_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORT7_PCNTR3 (R_PORT7_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORT7_POSR (R_PORT7_BASE + R_GPIO_POSR_OFFSET)
#define R_PORT7_PORR (R_PORT7_BASE + R_GPIO_PORR_OFFSET)
/* PORT8 Registers (subset: 9 of 12 registers) */
#define R_PORT8_PCNTR1 (R_PORT8_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORT8_PDR (R_PORT8_BASE + R_GPIO_PDR_OFFSET)
#define R_PORT8_PODR (R_PORT8_BASE + R_GPIO_PODR_OFFSET)
#define R_PORT8_PCNTR2 (R_PORT8_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORT8_PIDR (R_PORT8_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORT8_EIDR (R_PORT8_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORT8_PCNTR3 (R_PORT8_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORT8_POSR (R_PORT8_BASE + R_GPIO_POSR_OFFSET)
#define R_PORT8_PORR (R_PORT8_BASE + R_GPIO_PORR_OFFSET)
/* PORT9 Registers (subset: 9 of 12 registers) */
#define R_PORT9_PCNTR1 (R_PORT9_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORT9_PDR (R_PORT9_BASE + R_GPIO_PDR_OFFSET)
#define R_PORT9_PODR (R_PORT9_BASE + R_GPIO_PODR_OFFSET)
#define R_PORT9_PCNTR2 (R_PORT9_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORT9_PIDR (R_PORT9_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORT9_EIDR (R_PORT9_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORT9_PCNTR3 (R_PORT9_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORT9_POSR (R_PORT9_BASE + R_GPIO_POSR_OFFSET)
#define R_PORT9_PORR (R_PORT9_BASE + R_GPIO_PORR_OFFSET)
/* PORTA Registers (subset: 9 of 12 registers) */
#define R_PORTA_PCNTR1 (R_PORTA_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORTA_PDR (R_PORTA_BASE + R_GPIO_PDR_OFFSET)
#define R_PORTA_PODR (R_PORTA_BASE + R_GPIO_PODR_OFFSET)
#define R_PORTA_PCNTR2 (R_PORTA_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORTA_PIDR (R_PORTA_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORTA_EIDR (R_PORTA_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORTA_PCNTR3 (R_PORTA_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORTA_POSR (R_PORTA_BASE + R_GPIO_POSR_OFFSET)
#define R_PORTA_PORR (R_PORTA_BASE + R_GPIO_PORR_OFFSET)
/* PORTB Registers (subset: 9 of 12 registers) */
#define R_PORTB_PCNTR1 (R_PORTB_BASE + R_GPIO_PCNTR1_OFFSET)
#define R_PORTB_PDR (R_PORTB_BASE + R_GPIO_PDR_OFFSET)
#define R_PORTB_PODR (R_PORTB_BASE + R_GPIO_PODR_OFFSET)
#define R_PORTB_PCNTR2 (R_PORTB_BASE + R_GPIO_PCNTR2_OFFSET)
#define R_PORTB_PIDR (R_PORTB_BASE + R_GPIO_PIDR_OFFSET)
#define R_PORTB_EIDR (R_PORTB_BASE + R_GPIO_EIDR_OFFSET)
#define R_PORTB_PCNTR3 (R_PORTB_BASE + R_GPIO_PCNTR3_OFFSET)
#define R_PORTB_POSR (R_PORTB_BASE + R_GPIO_POSR_OFFSET)
#define R_PORTB_PORR (R_PORTB_BASE + R_GPIO_PORR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Port Control Register 1 (32-bits) ****************************************/
#define R_GPIO_PCNTR1_PDR_SHIFT (0)
#define R_GPIO_PCNTR1_PDR_MASK (0xffff)
# define R_GPIO_PCNTR1_PDR_V0 (0 << R_GPIO_PCNTR1_PDR_SHIFT) /* Input (functions as an input pin) */
# define R_GPIO_PCNTR1_PDR_V1 (1 << R_GPIO_PCNTR1_PDR_SHIFT) /* Output (functions as an output pin). */
#define R_GPIO_PCNTR1_PODR_SHIFT (16)
#define R_GPIO_PCNTR1_PODR_MASK (0xffff)
# define R_GPIO_PCNTR1_PODR_LOW_OUTPUT (0 << R_GPIO_PCNTR1_PODR_SHIFT) /* Low output */
# define R_GPIO_PCNTR1_PODR_HIGH_OUTPUT (1 << R_GPIO_PCNTR1_PODR_SHIFT) /* High output. */
/* Data direction register (16-bits) ****************************************/
#define R_GPIO_PDR_PDR_SHIFT (0)
#define R_GPIO_PDR_PDR_MASK (0xffff)
# define R_GPIO_PDR_PDR_V0 (0 << R_GPIO_PDR_PDR_SHIFT) /* Input (functions as an input pin) */
# define R_GPIO_PDR_PDR_V1 (1 << R_GPIO_PDR_PDR_SHIFT) /* Output (functions as an output pin). */
/* Output data register (16-bits) *******************************************/
#define R_GPIO_PODR_PODR_SHIFT (0)
#define R_GPIO_PODR_PODR_MASK (0xffff)
# define R_GPIO_PODR_PODR_LOW_OUTPUT (0 << R_GPIO_PODR_PODR_SHIFT) /* Low output */
# define R_GPIO_PODR_PODR_HIGH_OUTPUT (1 << R_GPIO_PODR_PODR_SHIFT) /* High output. */
/* Port Control Register 2 (32-bits) ****************************************/
#define R_GPIO_PCNTR2_PIDR_SHIFT (0)
#define R_GPIO_PCNTR2_PIDR_MASK (0xffff)
# define R_GPIO_PCNTR2_PIDR_LOW_INPUT (0 << R_GPIO_PCNTR2_PIDR_SHIFT) /* Low input */
# define R_GPIO_PCNTR2_PIDR_HIGH_INPUT (1 << R_GPIO_PCNTR2_PIDR_SHIFT) /* High input. */
#define R_GPIO_PCNTR2_EIDR_SHIFT (16)
#define R_GPIO_PCNTR2_EIDR_MASK (0xffff)
# define R_GPIO_PCNTR2_EIDR_LOW_INPUT (0 << R_GPIO_PCNTR2_EIDR_SHIFT) /* Low input */
# define R_GPIO_PCNTR2_EIDR_HIGH_INPUT (1 << R_GPIO_PCNTR2_EIDR_SHIFT) /* High input. */
/* Input data register (16-bits) ********************************************/
#define R_GPIO_PIDR_PIDR_SHIFT (0)
#define R_GPIO_PIDR_PIDR_MASK (0xffff)
# define R_GPIO_PIDR_PIDR_LOW_LEVEL (0 << R_GPIO_PIDR_PIDR_SHIFT) /* Low level */
# define R_GPIO_PIDR_PIDR_HIGH_LEVEL (1 << R_GPIO_PIDR_PIDR_SHIFT) /* high level. */
/* Port Event Input Data register (16-bits) *********************************/
#define R_GPIO_EIDR_EIDR_SHIFT (0)
#define R_GPIO_EIDR_EIDR_MASK (0xffff)
# define R_GPIO_EIDR_EIDR_LOW_INPUT (0 << R_GPIO_EIDR_EIDR_SHIFT) /* Low input */
# define R_GPIO_EIDR_EIDR_HIGH_INPUT (1 << R_GPIO_EIDR_EIDR_SHIFT) /* High input. */
/* Port Control Register 3 (32-bits) ****************************************/
#define R_GPIO_PCNTR3_POSR_SHIFT (0)
#define R_GPIO_PCNTR3_POSR_MASK (0xffff)
# define R_GPIO_PCNTR3_POSR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_PCNTR3_POSR_SHIFT) /* No affect to output */
# define R_GPIO_PCNTR3_POSR_HIGH_OUTPUT (1 << R_GPIO_PCNTR3_POSR_SHIFT) /* High output. */
#define R_GPIO_PCNTR3_PORR_SHIFT (16)
#define R_GPIO_PCNTR3_PORR_MASK (0xffff)
# define R_GPIO_PCNTR3_PORR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_PCNTR3_PORR_SHIFT) /* No affect to output */
# define R_GPIO_PCNTR3_PORR_LOW_OUTPUT (1 << R_GPIO_PCNTR3_PORR_SHIFT) /* Low output. */
/* Output set register (16-bits) ********************************************/
#define R_GPIO_POSR_POSR_SHIFT (0)
#define R_GPIO_POSR_POSR_MASK (0xffff)
# define R_GPIO_POSR_POSR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_POSR_POSR_SHIFT) /* No affect to output */
# define R_GPIO_POSR_POSR_HIGH_OUTPUT (1 << R_GPIO_POSR_POSR_SHIFT) /* High output. */
/* Output reset register (16-bits) ******************************************/
#define R_GPIO_PORR_PORR_SHIFT (0)
#define R_GPIO_PORR_PORR_MASK (0xffff)
# define R_GPIO_PORR_PORR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_PORR_PORR_SHIFT) /* No affect to output */
# define R_GPIO_PORR_PORR_LOW_OUTPUT (1 << R_GPIO_PORR_PORR_SHIFT) /* Low output. */
/* Port Control Register 4 (32-bits) ****************************************/
#define R_GPIO_PCNTR4_EOSR_SHIFT (0)
#define R_GPIO_PCNTR4_EOSR_MASK (0xffff)
# define R_GPIO_PCNTR4_EOSR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_PCNTR4_EOSR_SHIFT) /* No affect to output */
# define R_GPIO_PCNTR4_EOSR_HIGH_OUTPUT (1 << R_GPIO_PCNTR4_EOSR_SHIFT) /* High output. */
#define R_GPIO_PCNTR4_EORR_SHIFT (16)
#define R_GPIO_PCNTR4_EORR_MASK (0xffff)
# define R_GPIO_PCNTR4_EORR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_PCNTR4_EORR_SHIFT) /* No affect to output */
# define R_GPIO_PCNTR4_EORR_LOW_OUTPUT (1 << R_GPIO_PCNTR4_EORR_SHIFT) /* Low output */
/* Event output reset register (16-bits) ************************************/
#define R_GPIO_EOSR_EOSR_SHIFT (0)
#define R_GPIO_EOSR_EOSR_MASK (0xffff)
# define R_GPIO_EOSR_EOSR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_EOSR_EOSR_SHIFT) /* No affect to output */
# define R_GPIO_EOSR_EOSR_HIGH_OUTPUT (1 << R_GPIO_EOSR_EOSR_SHIFT) /* High output. */
/* Event output set register (16-bits) **************************************/
#define R_GPIO_EORR_EORR_SHIFT (0)
#define R_GPIO_EORR_EORR_MASK (0xffff)
# define R_GPIO_EORR_EORR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_EORR_EORR_SHIFT) /* No affect to output */
# define R_GPIO_EORR_EORR_LOW_OUTPUT (1 << R_GPIO_EORR_EORR_SHIFT) /* Low output */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_GPIO_H */

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/****************************************************************************
* arch/arm/src/ra8m1/hardware/ra8m1_icu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ICU_H
#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ICU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/ra8m1_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define R_ICU_IRQCR_OFFSET 0x0000 /* IRQ Control Register %s (8-bits) */
#define R_ICU_NMICR_OFFSET 0x0010 /* NMI Pin Interrupt Control Register (8-bits) */
#define R_ICU_SWIRQ_S_OFFSET 0x6010 /* Software Interrupt Request Register for Secure Interrupt (8-bits) */
#define R_ICU_SWIRQ_NS_OFFSET 0x6020 /* Software Interrupt Request Register for Non-secure Interrupt (8-bits) */
#define R_ICU_IENMIER_OFFSET 0x6060 /* Integrated Error NMI Interrupt Enable Register for CPU (16-bits) */
#define R_ICU_NMIER_OFFSET 0x6100 /* Non-Maskable Interrupt Enable Register (16-bits) */
#define R_ICU_NMICLR_OFFSET 0x6110 /* Non-Maskable Interrupt Status Clear Register (16-bits) */
#define R_ICU_NMISR_OFFSET 0x6120 /* Non-Maskable Interrupt Status Register (16-bits) */
#define R_ICU_WUPEN0_OFFSET 0x61a0 /* Wake Up Interrupt Enable Register 0 (32-bits) */
#define R_ICU_WUPEN1_OFFSET 0x61a4 /* Wake Up Interrupt Enable Register 1 (32-bits) */
#define R_ICU_SELSR0_OFFSET 0x6200 /* SYS Event Link Setting Register (16-bits) */
#define R_ICU_IELSR_OFFSET 0x6300 /* ICU Event Link Setting Register %s (32-bits) */
/* Register Addresses *******************************************************/
/* ICU Registers */
#define R_ICU_IRQCR(p) (R_ICU_BASE + R_ICU_IRQCR_OFFSET + (p)*0x0001)
#define R_ICU_NMICR (R_ICU_BASE + R_ICU_NMICR_OFFSET)
#define R_ICU_SWIRQ_S (R_ICU_BASE + R_ICU_SWIRQ_S_OFFSET)
#define R_ICU_SWIRQ_NS (R_ICU_BASE + R_ICU_SWIRQ_NS_OFFSET)
#define R_ICU_IENMIER (R_ICU_BASE + R_ICU_IENMIER_OFFSET)
#define R_ICU_NMIER (R_ICU_BASE + R_ICU_NMIER_OFFSET)
#define R_ICU_NMICLR (R_ICU_BASE + R_ICU_NMICLR_OFFSET)
#define R_ICU_NMISR (R_ICU_BASE + R_ICU_NMISR_OFFSET)
#define R_ICU_WUPEN0 (R_ICU_BASE + R_ICU_WUPEN0_OFFSET)
#define R_ICU_WUPEN1 (R_ICU_BASE + R_ICU_WUPEN1_OFFSET)
#define R_ICU_SELSR0 (R_ICU_BASE + R_ICU_SELSR0_OFFSET)
#define R_ICU_IELSR(p) (R_ICU_BASE + R_ICU_IELSR_OFFSET + (p)*0x0004)
/* Register Bitfield Definitions ********************************************/
/* IRQ Control Register %s (8-bits) *****************************************/
#define R_ICU_IRQCR_SIZE 16
#define R_ICU_IRQCR_IRQMD_SHIFT (0)
#define R_ICU_IRQCR_IRQMD_MASK (0x3)
# define R_ICU_IRQCR_IRQMD_FALLING_EDGE (0 << R_ICU_IRQCR_IRQMD_SHIFT) /* Falling edge */
# define R_ICU_IRQCR_IRQMD_RISING_EDGE (1 << R_ICU_IRQCR_IRQMD_SHIFT) /* Rising edge */
# define R_ICU_IRQCR_IRQMD_RISING_AND_FALLING_EDGES (2 << R_ICU_IRQCR_IRQMD_SHIFT) /* Rising and falling edges */
# define R_ICU_IRQCR_IRQMD_LOW_LEVEL (3 << R_ICU_IRQCR_IRQMD_SHIFT) /* Low level */
#define R_ICU_IRQCR_FCLKSEL_SHIFT (4)
#define R_ICU_IRQCR_FCLKSEL_MASK (0x3)
# define R_ICU_IRQCR_FCLKSEL_PCLKB (0 << R_ICU_IRQCR_FCLKSEL_SHIFT) /* PCLKB */
# define R_ICU_IRQCR_FCLKSEL_PCLKB_8 (1 << R_ICU_IRQCR_FCLKSEL_SHIFT) /* PCLKB/8 */
# define R_ICU_IRQCR_FCLKSEL_PCLKB_32 (2 << R_ICU_IRQCR_FCLKSEL_SHIFT) /* PCLKB/32 */
# define R_ICU_IRQCR_FCLKSEL_PCLKB_64 (3 << R_ICU_IRQCR_FCLKSEL_SHIFT) /* PCLKB/64 */
#define R_ICU_IRQCR_FLTEN (1 << 7) /* 80: IRQ Digital Filter Enable */
/* NMI Pin Interrupt Control Register (8-bits) ******************************/
#define R_ICU_NMICR_NMIMD (1 << 0) /* 01: NMI Detection Set */
#define R_ICU_NMICR_NFCLKSEL_SHIFT (4)
#define R_ICU_NMICR_NFCLKSEL_MASK (0x3)
# define R_ICU_NMICR_NFCLKSEL_PCLKB (0 << R_ICU_NMICR_NFCLKSEL_SHIFT) /* PCLKB */
# define R_ICU_NMICR_NFCLKSEL_PCLKB_8 (1 << R_ICU_NMICR_NFCLKSEL_SHIFT) /* PCLKB/8 */
# define R_ICU_NMICR_NFCLKSEL_PCLKB_32 (2 << R_ICU_NMICR_NFCLKSEL_SHIFT) /* PCLKB/32 */
# define R_ICU_NMICR_NFCLKSEL_PCLKB_64 (3 << R_ICU_NMICR_NFCLKSEL_SHIFT) /* PCLKB/64 */
#define R_ICU_NMICR_NFLTEN (1 << 7) /* 80: NMI Digital Filter Enable */
/* Software Interrupt Request Register for Secure Interrupt (8-bits) ********/
#define R_ICU_SWIRQ_S_SWIRQS (1 << 0) /* 01: Generates an interrupt for the other CPU subsystem. */
/* Software Interrupt Request Register for Non-secure Interrupt (8-bits) ****/
#define R_ICU_SWIRQ_NS_SWIRQNS (1 << 0) /* 01: Generates an interrupt for the other CPU subsystem. */
/* Integrated Error NMI Interrupt Enable Register for CPU (16-bits) *********/
#define R_ICU_IENMIER_CMEN (1 << 0) /* 01: Integrated Common Memory error nmi Enable */
#define R_ICU_IENMIER_LMEN (1 << 1) /* 02: Integrated Local Memory error nmi Enable */
#define R_ICU_IENMIER_BUSEN (1 << 2) /* 04: Integrated BUS error nmi Enable */
/* Non-Maskable Interrupt Enable Register (16-bits) *************************/
#define R_ICU_NMIER_IWDTEN (1 << 0) /* 01: IWDT Underflow/Refresh Error Interrupt Enable */
#define R_ICU_NMIER_WDTEN (1 << 1) /* 02: WDT Underflow/Refresh Error Interrupt Enable */
#define R_ICU_NMIER_PVD1EN (1 << 2) /* 04: Voltage-Monitoring 1 Interrupt Enable */
#define R_ICU_NMIER_PVD2EN (1 << 3) /* 08: Voltage-Monitoring 2 Interrupt Enable */
#define R_ICU_NMIER_OSTEN (1 << 6) /* 40: Oscillation Stop Detection Interrupt Enable */
#define R_ICU_NMIER_NMIEN (1 << 7) /* 80: NMI Pin Interrupt Enable */
#define R_ICU_NMIER_BUSEN (1 << 12) /* 1000: BUS error Interrupt Enable */
#define R_ICU_NMIER_CMEN (1 << 13) /* 2000: Common Memory error Interrupt Enable */
#define R_ICU_NMIER_LUEN (1 << 15) /* 8000: LockUp Interrupt Enable */
/* Non-Maskable Interrupt Status Clear Register (16-bits) *******************/
#define R_ICU_NMICLR_IWDTCLR (1 << 0) /* 01: IWDT Clear */
#define R_ICU_NMICLR_WDTCLR (1 << 1) /* 02: WDT Clear */
#define R_ICU_NMICLR_PVD1CLR (1 << 2) /* 04: PVD1 Clear */
#define R_ICU_NMICLR_PVD2CLR (1 << 3) /* 08: PVD2 Clear */
#define R_ICU_NMICLR_OSTCLR (1 << 6) /* 40: OST Clear */
#define R_ICU_NMICLR_NMICLR (1 << 7) /* 80: NMI Clear */
#define R_ICU_NMICLR_BUSCLR (1 << 12) /* 1000: Bus Clear */
#define R_ICU_NMICLR_CMCLR (1 << 13) /* 2000: CM Clear */
#define R_ICU_NMICLR_LUCLR (1 << 15) /* 8000: LU Clear */
/* Non-Maskable Interrupt Status Register (16-bits) *************************/
#define R_ICU_NMISR_IWDTST (1 << 0) /* 01: IWDT Underflow/Refresh Error Status Flag */
#define R_ICU_NMISR_WDTST (1 << 1) /* 02: WDT Underflow/Refresh Error Status Flag */
#define R_ICU_NMISR_PVD1ST (1 << 2) /* 04: Voltage-Monitoring 1 Interrupt Status Flag */
#define R_ICU_NMISR_PVD2ST (1 << 3) /* 08: Voltage-Monitoring 2 Interrupt Status Flag */
#define R_ICU_NMISR_OSTST (1 << 6) /* 40: Oscillation Stop Detection Interrupt Status Flag */
#define R_ICU_NMISR_NMIST (1 << 7) /* 80: NMI Status Flag */
#define R_ICU_NMISR_BUSST (1 << 12) /* 1000: BUS error Interrupt Status Flag */
#define R_ICU_NMISR_CMST (1 << 13) /* 2000: Common Memory error Interrupt Status Flag */
#define R_ICU_NMISR_LUST (1 << 15) /* 8000: LockUp Interrupt Status Flag */
/* Wake Up Interrupt Enable Register 0 (32-bits) ****************************/
#define R_ICU_WUPEN0_IRQWUPEN0 (1 << 0) /* 01: IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN1 (1 << 1) /* 02: IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN2 (1 << 2) /* 04: IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN3 (1 << 3) /* 08: IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN4 (1 << 4) /* 10: IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN5 (1 << 5) /* 20: IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN6 (1 << 6) /* 40: IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN7 (1 << 7) /* 80: IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN8 (1 << 8) /* 100: IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN9 (1 << 9) /* 200: IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN10 (1 << 10) /* 400: IRQ10 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN11 (1 << 11) /* 800: IRQ11 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN12 (1 << 12) /* 1000: IRQ12 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN13 (1 << 13) /* 2000: IRQ13 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN14 (1 << 14) /* 4000: IRQ14 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IRQWUPEN15 (1 << 15) /* 8000: IRQ15 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_IWDTWUPEN (1 << 16) /* 10000: IWDT Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_PVD1WUPEN (1 << 18) /* 40000: PVD1 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_PVD2WUPEN (1 << 19) /* 80000: PVD2 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_VBATTWUPEN (1 << 20) /* 100000: VBATT Monitor Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_RTCALMWUPEN (1 << 24) /* 1000000: RTC Alarm Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_RTCPRDWUPEN (1 << 25) /* 2000000: RCT Period Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_USBHSWUPEN (1 << 26) /* 4000000: USBHS Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_USBFSWUPEN (1 << 27) /* 8000000: USBFS0 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_AGT1UDWUPEN (1 << 28) /* 10000000: AGT1 Underflow Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_AGT1CAWUPEN (1 << 29) /* 20000000: AGT1 Compare Match A Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_AGT1CBWUPEN (1 << 30) /* 40000000: AGT1 Compare Match B Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN0_RIIC0WUPEN (1 << 31) /* 80000000: RIIC0 Address Match Interrupt Deep Sleep/Software Standby Returns Enable bit */
/* Wake Up Interrupt Enable Register 1 (32-bits) ****************************/
#define R_ICU_WUPEN1_COMPHS0WUPEN (1 << 3) /* 08: Comparator-HS0 Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN1_ULP0UWUPEN (1 << 8) /* 100: ULPT0 Underflow Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN1_ULP0AWUPEN (1 << 9) /* 200: ULPT0 Compare Match A Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN1_ULP0BWUPEN (1 << 10) /* 400: ULPT0 Compare Match B Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN1_I3CWUPEN (1 << 11) /* 800: I3C Wakeup Condition Detection Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN1_ULP1UWUPEN (1 << 12) /* 1000: ULPT1 Underflow Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN1_ULP1AWUPEN (1 << 13) /* 2000: ULPT1 Compare Match A Interrupt Deep Sleep/Software Standby Returns Enable bit */
#define R_ICU_WUPEN1_ULP1BWUPEN (1 << 14) /* 4000: ULPT1 Compare Match B Interrupt Deep Sleep/Software Standby Returns Enable bit */
/* SYS Event Link Setting Register (16-bits) ********************************/
#define R_ICU_SELSR0_SELS_SHIFT (0)
#define R_ICU_SELSR0_SELS_MASK (0x1ff)
# define R_ICU_SELSR0_SELS_V000000000 (0 << R_ICU_SELSR0_SELS_SHIFT) /* Disable event output to the associated low-power mode module */
/* ICU Event Link Setting Register %s (32-bits) *****************************/
#define R_ICU_IELSR_SIZE 96
#define R_ICU_IELSR_IELS_SHIFT (0)
#define R_ICU_IELSR_IELS_MASK (0x1ff)
# define R_ICU_IELSR_IELS_NOTHING_IS_SELECTED (0 << R_ICU_IELSR_IELS_SHIFT) /* Nothing is selected */
#define R_ICU_IELSR_IR (1 << 16) /* 10000: Interrupt Status Flag */
#define R_ICU_IELSR_DTCE (1 << 24) /* 1000000: DTC Activation Enable */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ICU_H */

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/****************************************************************************
* arch/arm/src/ra8m1/hardware/ra8m1_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MEMORYMAP_H
#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Registers Base Addresses */
#define R_ACMPHS0_BASE 0x40236000UL
#define R_ACMPHS1_BASE 0x40236100UL
#define R_ACMPHS2_BASE 0x40236200UL
#define R_ACMPHS3_BASE 0x40236300UL
#define R_ACMPHS4_BASE 0x40236400UL
#define R_ACMPHS5_BASE 0x40236500UL
#define R_ADC0_BASE 0x40332000UL
#define R_ADC1_BASE 0x40332200UL
#define R_AGTX0_BASE 0x40221000UL
#define R_AGTX1_BASE 0x40221100UL
#define R_AGTX2_BASE 0x40221200UL
#define R_AGTX3_BASE 0x40221300UL
#define R_AGTX4_BASE 0x40221400UL
#define R_AGTX5_BASE 0x40221500UL
#define R_AGTX6_BASE 0x40221600UL
#define R_AGTX7_BASE 0x40221700UL
#define R_AGTX8_BASE 0x40221800UL
#define R_AGTX9_BASE 0x40221900UL
#define R_BUS_BASE 0x40003000UL
#define R_CAC_BASE 0x40202400UL
#define R_CANFD1_BASE 0x40382000UL
#define R_CANFD_BASE 0x40380000UL
#define R_CEU_BASE 0x40348000UL
#define R_CPSCU_BASE 0x40008000UL
#define R_CRC_BASE 0x40310000UL
#define R_DAC_BASE 0x40333000UL
#define R_DEBUG_BASE 0x4001B000UL
#define R_DEBUG_OCD_BASE 0x40011000UL
#define R_DMAC0_BASE 0x4000A000UL
#define R_DMAC1_BASE 0x4000A040UL
#define R_DMAC2_BASE 0x4000A080UL
#define R_DMAC3_BASE 0x4000A0C0UL
#define R_DMAC4_BASE 0x4000A100UL
#define R_DMAC5_BASE 0x4000A140UL
#define R_DMAC6_BASE 0x4000A180UL
#define R_DMAC7_BASE 0x4000A1C0UL
#define R_DMA_BASE 0x4000A800UL
#define R_DOC_BASE 0x40311000UL
#define R_DOC_B_BASE 0x40311000UL
#define R_DOTF1_BASE 0x40268900UL
#define R_DOTF_BASE 0x40268800UL
#define R_DTC_BASE 0x4000AC00UL
#define R_ECCMB0_BASE 0x4036F200UL
#define R_ECCMB1_BASE 0x4036F300UL
#define R_ELC_BASE 0x40201000UL
#define R_ETHERC0_BASE 0x40354100UL
#define R_ETHERC_EDMAC_BASE 0x40354000UL
#define R_FACI_HP_BASE 0x4011E000UL
#define R_FACI_HP_CMD_BASE 0x40100000UL
#define R_FCACHE_BASE 0x4001C100UL
#define R_FLAD_BASE 0x4011C000UL
#define R_GPT0_BASE 0x40322000UL
#define R_GPT10_BASE 0x40322A00UL
#define R_GPT11_BASE 0x40322B00UL
#define R_GPT12_BASE 0x40322C00UL
#define R_GPT13_BASE 0x40322D00UL
#define R_GPT1_BASE 0x40322100UL
#define R_GPT2_BASE 0x40322200UL
#define R_GPT3_BASE 0x40322300UL
#define R_GPT4_BASE 0x40322400UL
#define R_GPT5_BASE 0x40322500UL
#define R_GPT6_BASE 0x40322600UL
#define R_GPT7_BASE 0x40322700UL
#define R_GPT8_BASE 0x40322800UL
#define R_GPT9_BASE 0x40322900UL
#define R_GPT_OPS_BASE 0x40323F00UL
#define R_GPT_POEG0_BASE 0x40212000UL
#define R_GPT_POEG1_BASE 0x40212100UL
#define R_GPT_POEG2_BASE 0x40212200UL
#define R_GPT_POEG3_BASE 0x40212300UL
#define R_I3C0_BASE 0x4035F000UL
#define R_I3C1_BASE 0x4035F100UL
#define R_ICU_BASE 0x40006000UL
#define R_IIC0_BASE 0x4025E000UL
#define R_IIC1_BASE 0x4025E100UL
#define R_IIC2_BASE 0x4025E200UL
#define R_IWDT_BASE 0x40202200UL
#define R_MPU_MMPU_BASE 0x40000000UL
#define R_MPU_SPMON_BASE 0x40000D00UL
#define R_MSTP_BASE 0x40203000UL
#define R_OFS_DATAFLASH_BASE 0x27030000UL
#define R_PFS_BASE 0x40400800UL
#define R_PMISC_BASE 0x40400D00UL
#define R_PORT0_BASE 0x40400000UL
#define R_PORT10_BASE 0x40400140UL
#define R_PORT11_BASE 0x40400160UL
#define R_PORT12_BASE 0x40400180UL
#define R_PORT13_BASE 0x404001A0UL
#define R_PORT14_BASE 0x404001C0UL
#define R_PORT1_BASE 0x40400020UL
#define R_PORT2_BASE 0x40400040UL
#define R_PORT3_BASE 0x40400060UL
#define R_PORT4_BASE 0x40400080UL
#define R_PORT5_BASE 0x404000A0UL
#define R_PORT6_BASE 0x404000C0UL
#define R_PORT7_BASE 0x404000E0UL
#define R_PORT8_BASE 0x40400100UL
#define R_PORT9_BASE 0x40400120UL
#define R_PSCU_BASE 0x40204000UL
#define R_RTC_BASE 0x40202000UL
#define R_SCI0_BASE 0x40358000UL
#define R_SCI1_BASE 0x40358100UL
#define R_SCI2_BASE 0x40358200UL
#define R_SCI3_BASE 0x40358300UL
#define R_SCI4_BASE 0x40358400UL
#define R_SCI5_BASE 0x40358500UL
#define R_SCI6_BASE 0x40358600UL
#define R_SCI7_BASE 0x40358700UL
#define R_SCI8_BASE 0x40358800UL
#define R_SCI9_BASE 0x40358900UL
#define R_SCI_B0_BASE 0x40358000UL
#define R_SCI_B1_BASE 0x40358100UL
#define R_SCI_B2_BASE 0x40358200UL
#define R_SCI_B3_BASE 0x40358300UL
#define R_SCI_B4_BASE 0x40358400UL
#define R_SCI_B5_BASE 0x40358500UL
#define R_SCI_B6_BASE 0x40358600UL
#define R_SCI_B7_BASE 0x40358700UL
#define R_SCI_B8_BASE 0x40358800UL
#define R_SCI_B9_BASE 0x40358900UL
#define R_SDHI0_BASE 0x40252000UL
#define R_SDHI1_BASE 0x40252400UL
#define R_SPI0_BASE 0x4035C000UL
#define R_SPI1_BASE 0x4035C100UL
#define R_SPI2_BASE 0x40072200UL
#define R_SPI_B0_BASE 0x4035C000UL
#define R_SPI_B1_BASE 0x4035C100UL
#define R_SRAM_BASE 0x40002000UL
#define R_SSI0_BASE 0x4025D000UL
#define R_SSI1_BASE 0x4025D100UL
#define R_SYSTEM_BASE 0x4001E000UL
#define R_TSN_CAL_BASE 0x4011B17CUL
#define R_TSN_CTRL_BASE 0x40235000UL
#define R_ULPT0_BASE 0x40220000UL
#define R_ULPT1_BASE 0x40220100UL
#define R_USB_FS0_BASE 0x40250000UL
#define R_USB_HS0_BASE 0x40351000UL
#define R_WDT1_BASE 0x40044300UL
#define R_WDT_BASE 0x40202600UL
#define R_XSPI0_BASE 0x40268000UL
#define R_XSPI1_BASE 0x40268400UL
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/ra8m1/hardware/ra8m1_mstp.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MSTP_H
#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MSTP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/ra8m1_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define R_MSTP_MSTPCRA_OFFSET 0x0000 /* Module Stop Control Register A (32-bits) */
#define R_MSTP_MSTPCRB_OFFSET 0x0004 /* Module Stop Control Register B (32-bits) */
#define R_MSTP_MSTPCRC_OFFSET 0x0008 /* Module Stop Control Register C (32-bits) */
#define R_MSTP_MSTPCRD_OFFSET 0x000c /* Module Stop Control Register D (32-bits) */
#define R_MSTP_MSTPCRE_OFFSET 0x0010 /* Module Stop Control Register E (32-bits) */
/* Register Addresses *******************************************************/
/* MSTP Registers */
#define R_MSTP_MSTPCRA (R_MSTP_BASE + R_MSTP_MSTPCRA_OFFSET)
#define R_MSTP_MSTPCRB (R_MSTP_BASE + R_MSTP_MSTPCRB_OFFSET)
#define R_MSTP_MSTPCRC (R_MSTP_BASE + R_MSTP_MSTPCRC_OFFSET)
#define R_MSTP_MSTPCRD (R_MSTP_BASE + R_MSTP_MSTPCRD_OFFSET)
#define R_MSTP_MSTPCRE (R_MSTP_BASE + R_MSTP_MSTPCRE_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Module Stop Control Register A (32-bits) *********************************/
#define R_MSTP_MSTPCRA_MSTPA0 (1 << 0) /* 01: SRAM0 Module Stop */
#define R_MSTP_MSTPCRA_MSTPA1 (1 << 1) /* 02: SRAM1 Module Stop */
#define R_MSTP_MSTPCRA_MSTPA15 (1 << 15) /* 8000: Standby SRAM Module Module Stop */
#define R_MSTP_MSTPCRA_MSTPA22 (1 << 22) /* 400000: DMA Controller/Data Transfer Controller unit0 Module Stop */
/* Module Stop Control Register B (32-bits) *********************************/
#define R_MSTP_MSTPCRB_MSTPB4 (1 << 4) /* 10: I3C Bus Interface Module Stop */
#define R_MSTP_MSTPCRB_MSTPB8 (1 << 8) /* 100: I2C Bus Interface 1 Module Stop */
#define R_MSTP_MSTPCRB_MSTPB9 (1 << 9) /* 200: I2C Bus Interface 0 Module Stop */
#define R_MSTP_MSTPCRB_MSTPB11 (1 << 11) /* 800: Universal Serial Bus 2.0 FS0 Interface Module Stop */
#define R_MSTP_MSTPCRB_MSTPB12 (1 << 12) /* 1000: Universal Serial Bus 2.0 HS Interface Module Stop */
#define R_MSTP_MSTPCRB_MSTPB15 (1 << 15) /* 8000: ETHERC0 and EDMAC0 Module Stop */
#define R_MSTP_MSTPCRB_MSTPB16 (1 << 16) /* 10000: Octa Memory Controller Module Stop */
#define R_MSTP_MSTPCRB_MSTPB18 (1 << 18) /* 40000: Serial Peripheral Interface 1 Module Stop */
#define R_MSTP_MSTPCRB_MSTPB19 (1 << 19) /* 80000: Serial Peripheral Interface 0 Module Stop */
#define R_MSTP_MSTPCRB_MSTPB22 (1 << 22) /* 400000: Serial Communication Interface 9 Module Stop */
#define R_MSTP_MSTPCRB_MSTPB27 (1 << 27) /* 8000000: Serial Communication Interface 4 Module Stop */
#define R_MSTP_MSTPCRB_MSTPB28 (1 << 28) /* 10000000: Serial Communication Interface 3 Module Stop */
#define R_MSTP_MSTPCRB_MSTPB29 (1 << 29) /* 20000000: Serial Communication Interface 2 Module Stop */
#define R_MSTP_MSTPCRB_MSTPB30 (1 << 30) /* 40000000: Serial Communication Interface 1 Module Stop */
#define R_MSTP_MSTPCRB_MSTPB31 (1 << 31) /* 80000000: Serial Communication Interface 0 Module Stop */
/* Module Stop Control Register C (32-bits) *********************************/
#define R_MSTP_MSTPCRC_MSTPC0 (1 << 0) /* 01: Clock Frequency Accuracy Measurement Circuit Module Stop */
#define R_MSTP_MSTPCRC_MSTPC1 (1 << 1) /* 02: Cyclic Redundancy Check Calculator Module Stop */
#define R_MSTP_MSTPCRC_MSTPC4 (1 << 4) /* 10: Graphics LCD Controller Module Stop */
#define R_MSTP_MSTPCRC_MSTPC6 (1 << 6) /* 40: 2D Drawing Engine Module Stop */
#define R_MSTP_MSTPCRC_MSTPC7 (1 << 7) /* 80: Serial Sound Interface1 Enhanced Module Stop */
#define R_MSTP_MSTPCRC_MSTPC8 (1 << 8) /* 100: Serial Sound Interface0 Enhanced Module Stop */
#define R_MSTP_MSTPCRC_MSTPC10 (1 << 10) /* 400: MIPI Display Serial Interface Module Stop */
#define R_MSTP_MSTPCRC_MSTPC11 (1 << 11) /* 800: Secure Digital Host IF 1 Module Stop */
#define R_MSTP_MSTPCRC_MSTPC12 (1 << 12) /* 1000: Secure Digital Host IF 0 Module Stop */
#define R_MSTP_MSTPCRC_MSTPC13 (1 << 13) /* 2000: Data Operation Circuit Module Stop */
#define R_MSTP_MSTPCRC_MSTPC14 (1 << 14) /* 4000: Event Link Controller Module Stop */
#define R_MSTP_MSTPCRC_MSTPC16 (1 << 16) /* 10000: CEU Module Stop */
#define R_MSTP_MSTPCRC_MSTPC26 (1 << 26) /* 4000000: Controller Area Network with Flexible Data-Rate 1 Module Stop */
#define R_MSTP_MSTPCRC_MSTPC27 (1 << 27) /* 8000000: Controller Area Network with Flexible Data-Rate 0 Module Stop */
#define R_MSTP_MSTPCRC_MSTPC31 (1 << 31) /* 80000000: SHIP Module Stop */
/* Module Stop Control Register D (32-bits) *********************************/
#define R_MSTP_MSTPCRD_MSTPD4 (1 << 4) /* 10: Asynchronous General Purpose Timer 1 Module Stop */
#define R_MSTP_MSTPCRD_MSTPD5 (1 << 5) /* 20: Asynchronous General Purpose Timer 0 Module Stop */
#define R_MSTP_MSTPCRD_MSTPD11 (1 << 11) /* 800: Port Output Enable for GPT3 Module Stop */
#define R_MSTP_MSTPCRD_MSTPD12 (1 << 12) /* 1000: Port Output Enable for GPT2 Module Stop */
#define R_MSTP_MSTPCRD_MSTPD13 (1 << 13) /* 2000: Port Output Enable for GPT1 Module Stop */
#define R_MSTP_MSTPCRD_MSTPD14 (1 << 14) /* 4000: Port Output Enable for GPT0 Module Stop */
#define R_MSTP_MSTPCRD_MSTPD15 (1 << 15) /* 8000: 12-bit A/D Converter 1 Module Stop */
#define R_MSTP_MSTPCRD_MSTPD16 (1 << 16) /* 10000: 12-bit A/D Converter 0 Module Stop */
#define R_MSTP_MSTPCRD_MSTPD20 (1 << 20) /* 100000: 12-Bit D/A Converter Module Stop */
#define R_MSTP_MSTPCRD_MSTPD22 (1 << 22) /* 400000: Temperature Sensor Module Stop */
#define R_MSTP_MSTPCRD_MSTPD27 (1 << 27) /* 8000000: High-Speed Analog Com-parator 1 Module Stop */
#define R_MSTP_MSTPCRD_MSTPD28 (1 << 28) /* 10000000: High-Speed Analog Com-parator 0 Module Stop */
/* Module Stop Control Register E (32-bits) *********************************/
#define R_MSTP_MSTPCRE_MSTPE8 (1 << 8) /* 100: Ultra-Low Power Timer 1 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE9 (1 << 9) /* 200: Ultra-Low Power Timer 0 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE18 (1 << 18) /* 40000: General PWM Timer 13 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE19 (1 << 19) /* 80000: General PWM Timer 12 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE20 (1 << 20) /* 100000: General PWM Timer 11 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE21 (1 << 21) /* 200000: General PWM Timer 10 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE22 (1 << 22) /* 400000: General PWM Timer 9 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE23 (1 << 23) /* 800000: General PWM Timer 8 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE24 (1 << 24) /* 1000000: General PWM Timer 7 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE25 (1 << 25) /* 2000000: General PWM Timer 6 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE26 (1 << 26) /* 4000000: General PWM Timer 5 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE27 (1 << 27) /* 8000000: General PWM Timer 4 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE28 (1 << 28) /* 10000000: General PWM Timer 3 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE29 (1 << 29) /* 20000000: General PWM Timer 2 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE30 (1 << 30) /* 40000000: General PWM Timer 1 Module Stop */
#define R_MSTP_MSTPCRE_MSTPE31 (1 << 31) /* 80000000: General PWM Timer 0 Module Stop */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MSTP_H */

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/****************************************************************************
* arch/arm/src/ra8m1/hardware/ra8m1_option_setting.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_OPTION_SETTING_H
#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_OPTION_SETTING_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Option-setting memory registers (RA8M1 User's Manual, chapter 6).
*
* These are not peripheral registers: they are words in the code-flash
* configuration area that the MCU samples at reset, programmed together
* with the image (FACI command / debugger), and read-only at run time.
* The linker script places each one by section name; there are no run-time
* addresses here.
*
* This is a flat (no TrustZone) image, so only the secure-region registers
* are used. OFS1 below is the register at 0x0300_A200 (called OFS1_SEC in
* the manual); the non-secure OFS1 at 0x1300_A180 is not used.
*
* Bits documented as "The program value is read from this bit" are
* reserved: they must be programmed as 1 (note 2 of each register).
*/
/* Option Function Select Register 0 (OFS0) -- address 0x0300_A100 **********/
#define R_OFS0_RESERVED 0xa001a001 /* Bits 31, 29, 16, 15, 13, 0 */
/* Independent Watchdog Timer (IWDT) ****************************************/
#define R_OFS0_IWDTSTRT (1 << 1) /* 0: Auto start after reset, 1: Register start (stopped) */
#define R_OFS0_IWDTTOPS_SHIFT (2) /* Bits 3-2: Timeout period select */
#define R_OFS0_IWDTTOPS_MASK (0x3)
# define R_OFS0_IWDTTOPS_128 (0 << R_OFS0_IWDTTOPS_SHIFT) /* 128 cycles */
# define R_OFS0_IWDTTOPS_512 (1 << R_OFS0_IWDTTOPS_SHIFT) /* 512 cycles */
# define R_OFS0_IWDTTOPS_1024 (2 << R_OFS0_IWDTTOPS_SHIFT) /* 1024 cycles */
# define R_OFS0_IWDTTOPS_2048 (3 << R_OFS0_IWDTTOPS_SHIFT) /* 2048 cycles */
#define R_OFS0_IWDTCKS_SHIFT (4) /* Bits 7-4: Clock division ratio select */
#define R_OFS0_IWDTCKS_MASK (0xf)
# define R_OFS0_IWDTCKS_DIV1 (0x0 << R_OFS0_IWDTCKS_SHIFT) /* x 1 */
# define R_OFS0_IWDTCKS_DIV16 (0x2 << R_OFS0_IWDTCKS_SHIFT) /* x 1/16 */
# define R_OFS0_IWDTCKS_DIV32 (0x3 << R_OFS0_IWDTCKS_SHIFT) /* x 1/32 */
# define R_OFS0_IWDTCKS_DIV64 (0x4 << R_OFS0_IWDTCKS_SHIFT) /* x 1/64 */
# define R_OFS0_IWDTCKS_DIV128 (0xf << R_OFS0_IWDTCKS_SHIFT) /* x 1/128 */
# define R_OFS0_IWDTCKS_DIV256 (0x5 << R_OFS0_IWDTCKS_SHIFT) /* x 1/256 */
#define R_OFS0_IWDTRPES_SHIFT (8) /* Bits 9-8: Window end position select */
#define R_OFS0_IWDTRPES_MASK (0x3)
# define R_OFS0_IWDTRPES_75 (0 << R_OFS0_IWDTRPES_SHIFT) /* 75% */
# define R_OFS0_IWDTRPES_50 (1 << R_OFS0_IWDTRPES_SHIFT) /* 50% */
# define R_OFS0_IWDTRPES_25 (2 << R_OFS0_IWDTRPES_SHIFT) /* 25% */
# define R_OFS0_IWDTRPES_0 (3 << R_OFS0_IWDTRPES_SHIFT) /* 0% (no window end position) */
#define R_OFS0_IWDTRPSS_SHIFT (10) /* Bits 11-10: Window start position select */
#define R_OFS0_IWDTRPSS_MASK (0x3)
# define R_OFS0_IWDTRPSS_25 (0 << R_OFS0_IWDTRPSS_SHIFT) /* 25% */
# define R_OFS0_IWDTRPSS_50 (1 << R_OFS0_IWDTRPSS_SHIFT) /* 50% */
# define R_OFS0_IWDTRPSS_75 (2 << R_OFS0_IWDTRPSS_SHIFT) /* 75% */
# define R_OFS0_IWDTRPSS_100 (3 << R_OFS0_IWDTRPSS_SHIFT) /* 100% (no window start position) */
#define R_OFS0_IWDTRSTIRQS (1 << 12) /* 0: Interrupt, 1: Reset on underflow/refresh error */
#define R_OFS0_IWDTSTPCTL (1 << 14) /* 0: Continue counting, 1: Stop counting in low power modes */
/* Watchdog Timer (WDT0) ****************************************************/
#define R_OFS0_WDT0STRT (1 << 17) /* 0: Auto start after reset, 1: Register start (stopped) */
#define R_OFS0_WDT0TOPS_SHIFT (18) /* Bits 19-18: Timeout period select */
#define R_OFS0_WDT0TOPS_MASK (0x3)
# define R_OFS0_WDT0TOPS_1024 (0 << R_OFS0_WDT0TOPS_SHIFT) /* 1024 cycles */
# define R_OFS0_WDT0TOPS_4096 (1 << R_OFS0_WDT0TOPS_SHIFT) /* 4096 cycles */
# define R_OFS0_WDT0TOPS_8192 (2 << R_OFS0_WDT0TOPS_SHIFT) /* 8192 cycles */
# define R_OFS0_WDT0TOPS_16384 (3 << R_OFS0_WDT0TOPS_SHIFT) /* 16384 cycles */
#define R_OFS0_WDT0CKS_SHIFT (20) /* Bits 23-20: Clock division ratio select */
#define R_OFS0_WDT0CKS_MASK (0xf)
# define R_OFS0_WDT0CKS_DIV4 (0x1 << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 4 */
# define R_OFS0_WDT0CKS_DIV64 (0x4 << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 64 */
# define R_OFS0_WDT0CKS_DIV128 (0xf << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 128 */
# define R_OFS0_WDT0CKS_DIV512 (0x6 << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 512 */
# define R_OFS0_WDT0CKS_DIV2048 (0x7 << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 2048 */
# define R_OFS0_WDT0CKS_DIV8192 (0x8 << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 8192 */
#define R_OFS0_WDT0RPES_SHIFT (24) /* Bits 25-24: Window end position select */
#define R_OFS0_WDT0RPES_MASK (0x3)
# define R_OFS0_WDT0RPES_75 (0 << R_OFS0_WDT0RPES_SHIFT) /* 75% */
# define R_OFS0_WDT0RPES_50 (1 << R_OFS0_WDT0RPES_SHIFT) /* 50% */
# define R_OFS0_WDT0RPES_25 (2 << R_OFS0_WDT0RPES_SHIFT) /* 25% */
# define R_OFS0_WDT0RPES_0 (3 << R_OFS0_WDT0RPES_SHIFT) /* 0% (no window end position) */
#define R_OFS0_WDT0RPSS_SHIFT (26) /* Bits 27-26: Window start position select */
#define R_OFS0_WDT0RPSS_MASK (0x3)
# define R_OFS0_WDT0RPSS_25 (0 << R_OFS0_WDT0RPSS_SHIFT) /* 25% */
# define R_OFS0_WDT0RPSS_50 (1 << R_OFS0_WDT0RPSS_SHIFT) /* 50% */
# define R_OFS0_WDT0RPSS_75 (2 << R_OFS0_WDT0RPSS_SHIFT) /* 75% */
# define R_OFS0_WDT0RPSS_100 (3 << R_OFS0_WDT0RPSS_SHIFT) /* 100% (no window start position) */
#define R_OFS0_WDT0RSTIRQS (1 << 28) /* 0: Interrupt, 1: Reset on underflow/refresh error */
#define R_OFS0_WDT0STPCTL (1 << 30) /* 0: Continue counting, 1: Stop counting in CPU Sleep/Deep Sleep */
/* Option Function Select Register 1 (OFS1) -- address 0x0300_A200 **********/
/* Called OFS1_SEC in the manual. *******************************************/
#define R_OFS1_RESERVED 0xfcfff0d0 /* Bits 31-26, 23-12, 7-6, 4 */
#define R_OFS1_VDSEL_SHIFT (0) /* Bits 2-0: Voltage detection 0 level select */
#define R_OFS1_VDSEL_MASK (0x7)
# define R_OFS1_VDSEL_2_85V (0 << R_OFS1_VDSEL_SHIFT) /* 2.85 V */
# define R_OFS1_VDSEL_2_58V (1 << R_OFS1_VDSEL_SHIFT) /* 2.58 V */
# define R_OFS1_VDSEL_2_15V (2 << R_OFS1_VDSEL_SHIFT) /* 2.15 V */
# define R_OFS1_VDSEL_2_00V (3 << R_OFS1_VDSEL_SHIFT) /* 2.00 V */
# define R_OFS1_VDSEL_1_90V (4 << R_OFS1_VDSEL_SHIFT) /* 1.90 V */
# define R_OFS1_VDSEL_1_80V (5 << R_OFS1_VDSEL_SHIFT) /* 1.80 V */
# define R_OFS1_VDSEL_1_70V (6 << R_OFS1_VDSEL_SHIFT) /* 1.70 V */
# define R_OFS1_VDSEL_1_60V (7 << R_OFS1_VDSEL_SHIFT) /* 1.60 V */
#define R_OFS1_PVDAS (1 << 3) /* 0: Enable voltage monitor 0 reset after reset, 1: Disable */
#define R_OFS1_PVDLPSEL (1 << 5) /* 0: Enable PVD0 low power function in DSTBY1/2, 1: Disable */
#define R_OFS1_HOCOEN (1 << 8) /* 0: Enable HOCO oscillation after reset, 1: Disable */
#define R_OFS1_HOCOFRQ0_SHIFT (9) /* Bits 11-9: HOCO frequency setting 0 */
#define R_OFS1_HOCOFRQ0_MASK (0x7)
# define R_OFS1_HOCOFRQ0_16MHZ (0 << R_OFS1_HOCOFRQ0_SHIFT) /* 16 MHz */
# define R_OFS1_HOCOFRQ0_18MHZ (1 << R_OFS1_HOCOFRQ0_SHIFT) /* 18 MHz */
# define R_OFS1_HOCOFRQ0_20MHZ (2 << R_OFS1_HOCOFRQ0_SHIFT) /* 20 MHz */
# define R_OFS1_HOCOFRQ0_32MHZ (4 << R_OFS1_HOCOFRQ0_SHIFT) /* 32 MHz */
# define R_OFS1_HOCOFRQ0_48MHZ (7 << R_OFS1_HOCOFRQ0_SHIFT) /* 48 MHz */
#define R_OFS1_SWDBG (1 << 24) /* 0: Enable software debug control, 1: Disable */
#define R_OFS1_INITECCEN (1 << 25) /* 0: Disable TCM/cache ECC, 1: Enable */
/* Option Function Select Register 2 (OFS2) -- address 0x0300_A104 **********/
#define R_OFS2_RESERVED 0xfffffffe /* Bits 31-1 */
#define R_OFS2_DCDCEN (1 << 0) /* 0: Disable DCDC, 1: Enable DCDC */
/* OFS1 Security Attribution Register (OFS1_SEL) -- address 0x0300_A280 *****/
/* Each bit selects whether the matching OFS1 field comes from OFS1_SEC (0)
* or from the non-secure OFS1 (1). A flat image uses only OFS1 above, so
* the whole register is programmed as 0.
*/
#define R_OFS1_SEL_ALL_SECURE 0x00000000
#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_OPTION_SETTING_H */

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/****************************************************************************
* arch/arm/src/ra8m1/hardware/ra8m1_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_PINMAP_H
#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/ra8m1_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define R_PFS_PSEL_PORT_OFFSET 0x40
#define R_PFS_PSEL_PIN_OFFSET 0x04
/* RA8M1 has no PMISC peripheral. Its PFS write-protect register (PWPR)
* lives inside the PFS block itself -- User's Manual section 19.2.8.
*
* This port is a flat (no TrustZone) image, which always runs in the
* secure state and uses the secure aliases of every register, so PWPR is
* the secure instance (offset 0x514 from R_PFS_BASE). The manual also
* defines a non-secure PWPR at a different offset (0x50c from PFS_NS);
* it is deliberately not used here.
*/
#define R_PFS_PWPR_OFFSET 0x0514
/* Port Control Registers (PCNTR1-4): confirmed against sections 19.2.1-
* 19.2.4. RA8M1 packs two 16-bit halves into each 32-bit PCNTRn,
* individually accessible at PCNTRn's own offset (low half) and +2
* (high half).
* PCNTR4/EOSR/EORR only exist on PORT1-4 (ELC port-group function); the
* offsets are still defined generically here since nothing stops issuing
* the access, only the manual limits which ports implement it.
*/
#define R_PORT_PCNTR1_OFFSET 0x0000 /* PDR (low 16) / PODR (high 16) */
#define R_PORT_PDR_OFFSET 0x0000 /* Pmn Direction (16-bit) */
#define R_PORT_PODR_OFFSET 0x0002 /* Pmn Output Data (16-bit) */
#define R_PORT_PCNTR2_OFFSET 0x0004 /* PIDR (low 16) / EIDR (high 16) */
#define R_PORT_PIDR_OFFSET 0x0004 /* Pmn State (16-bit, RO) */
#define R_PORT_EIDR_OFFSET 0x0006 /* Port Event Input Data (16-bit, RO) */
#define R_PORT_PCNTR3_OFFSET 0x0008 /* POSR (low 16) / PORR (high 16) */
#define R_PORT_POSR_OFFSET 0x0008 /* Pmn Output Set (16-bit, WO) */
#define R_PORT_PORR_OFFSET 0x000a /* Pmn Output Reset (16-bit, WO) */
#define R_PORT_PCNTR4_OFFSET 0x000c /* EOSR (low 16) / EORR (high 16), PORT1-4 only */
#define R_PORT_EOSR_OFFSET 0x000c /* Pmn Event Output Set (16-bit) */
#define R_PORT_EORR_OFFSET 0x000e /* Pmn Event Output Reset (16-bit) */
/* Register Addresses *******************************************************/
#define R_PFS(port,pin) (R_PFS_BASE + (port)*R_PFS_PSEL_PORT_OFFSET + (pin)*R_PFS_PSEL_PIN_OFFSET)
#define R_PFS_PWPR (R_PFS_BASE + R_PFS_PWPR_OFFSET)
/* R_PORT0_BASE..R_PORT9_BASE, R_PORT10_BASE (PORTA) and R_PORT11_BASE
* (PORTB) in ra8m1_memorymap.h are all R_PORT0_BASE + port*0x20 -- this
* indexes that uniform stride instead of switching over 12 discrete
* per-instance macros.
*/
#define R_PORT_BASE(port) (R_PORT0_BASE + (port)*0x20)
#define R_PORT_PDR(port) (R_PORT_BASE(port) + R_PORT_PDR_OFFSET)
#define R_PORT_PODR(port) (R_PORT_BASE(port) + R_PORT_PODR_OFFSET)
#define R_PORT_PIDR(port) (R_PORT_BASE(port) + R_PORT_PIDR_OFFSET)
#define R_PORT_EIDR(port) (R_PORT_BASE(port) + R_PORT_EIDR_OFFSET)
#define R_PORT_POSR(port) (R_PORT_BASE(port) + R_PORT_POSR_OFFSET)
#define R_PORT_PORR(port) (R_PORT_BASE(port) + R_PORT_PORR_OFFSET)
#define R_PORT_EOSR(port) (R_PORT_BASE(port) + R_PORT_EOSR_OFFSET)
#define R_PORT_EORR(port) (R_PORT_BASE(port) + R_PORT_EORR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* PmnPFS/PmnPFS_HA/PmnPFS_BY - Port mn Pin Function Select Register.
*
* Bit positions confirmed against the RA8M1 User's Manual (R01UH0994EJ0130
* Rev.1.30), section 19.2.5.
*/
#define R_PFS_PSEL_SHIFT (24) /* 28:24: Peripheral Select. For individual pin functions, see the tables in RA8M1 User's Manual chapter 19.6 */
#define R_PFS_PSEL_MASK (0x1f)
#define R_PFS_PMR (1 << 16) /* Bit 16: Port Mode Control */
#define R_PFS_ASEL (1 << 15) /* Bit 15: Analog Input enable */
#define R_PFS_ISEL (1 << 14) /* Bit 14: IRQ input enable */
#define R_PFS_EOR (1 << 13) /* Bit 13: Event on Rising (EOFR[1:0] upper bit) */
#define R_PFS_EOF (1 << 12) /* Bit 12: Event on Falling (EOFR[1:0] lower bit) */
#define R_PFS_DSCR1 (1 << 11) /* Bit 11: Port Drive Capability 1 */
#define R_PFS_DSCR (1 << 10) /* Bit 10: Port Drive Capability */
#define R_PFS_NCODR (1 << 6) /* Bit 6: N-Channel Open Drain Control */
#define R_PFS_PCR (1 << 4) /* Bit 4: Pull-up Control */
#define R_PFS_PDR (1 << 2) /* Bit 2: Port Direction */
#define R_PFS_PIDR (1 << 1) /* Bit 1: Port Input Data */
#define R_PFS_PODR (1 << 0) /* Bit 0: Port Output Data */
/* PWPR - Write-Protect Register for the PmnPFS registers (section 19.2.8).
* PFSWE can only be set after B0WI has been cleared.
*/
#define R_PFS_PWPR_B0WI (1 << 7) /* Bit 7: PFSWE Bit Write Disable */
#define R_PFS_PWPR_PFSWE (1 << 6) /* Bit 6: PmnPFS Register Write Enable */
/* PSEL[4:0] peripheral-function values.
*
* RA8M1-specific: confirmed against User's Manual chapter 19.6
* ("Peripheral Select Settings for Each Product", Tables 19.6-19.17,
* covering PORT0 through PORTB). PSEL is a per-pin, per-port mux slot --
* the same numeric value means a different peripheral/channel depending on
* which pin it's applied to (e.g. PSEL=00100b is SCI0 on P112/P113 but
* SCI4 on P205/P206) -- so PFS_PSEL_SCI/PFS_PSEL_SCI1 below name the two
* generic "SCI mux slots" a port can offer, not a specific channel; the
* GPIO_RXDn_MISOn_SCLn_x/GPIO_TXDn_MOSIn_SDAn_x macros below already bake
* in which slot each specific pin needs.
*
* Only the SCI slots are defined here -- these are the only PSEL values
* this file's pin macros use, and the only ones confirmed against chapter
* 19.6. Every other peripheral (AGT/GPT/SPI/IIC/CLKOUT/CAN/etc.) has its
* own PSEL value per chapter 19.6 too; add those here once verified the
* same way, rather than guessing.
*/
#define PFS_PSEL_SCI (0x04 << R_PFS_PSEL_SHIFT)
#define PFS_PSEL_SCI1 (0x05 << R_PFS_PSEL_SHIFT)
/* GPIO ports and pins.
*
* RA8M1 has PORT0-PORT9 plus PORTA/PORTB (12 ports total, chapter 19.1
* Table 19.1). PIN0-PIN15 are just the generic 0-15 per-port pin index
* (every RA8M1 port has up to 16 pins, PmnPFS's own n range).
*/
#define PORT0 (0)
#define PORT1 (1)
#define PORT2 (2)
#define PORT3 (3)
#define PORT4 (4)
#define PORT5 (5)
#define PORT6 (6)
#define PORT7 (7)
#define PORT8 (8)
#define PORT9 (9)
#define PORTA (10)
#define PORTB (11)
#define PORT_INVALID (0xff)
#define PIN0 (0)
#define PIN1 (1)
#define PIN2 (2)
#define PIN3 (3)
#define PIN4 (4)
#define PIN5 (5)
#define PIN6 (6)
#define PIN7 (7)
#define PIN8 (8)
#define PIN9 (9)
#define PIN10 (10)
#define PIN11 (11)
#define PIN12 (12)
#define PIN13 (13)
#define PIN14 (14)
#define PIN15 (15)
#define PIN_INVALID (0xff)
/* SCI Alternative *********************************************************
*
* RA8M1 has SCI0-SCI4 and SCI9 (SCI5-8 do not exist). Each channel's RXD/
* TXD pair can be routed to one of three alternate pin groups (the
* manual's "_A"/"_B"/"_C" suffixes, numbered _1/_2/_3 below to match this
* port's existing GPIO_RXDn..._x / GPIO_TXDn..._x convention). RXD shares
* its pin with the simple-SPI MISO and simple-I2C SCL alternate functions;
* TXD shares its pin with simple-SPI MOSI and simple-I2C SDA -- the PFS
* PSEL value only selects "SCI" (or "SCI slot 2"); which of RXD/MISO/SCL
* actually drives the pin depends on the SCI's own mode register, not PFS.
*
* Source: RA8M1 User's Manual chapter 19.6, Tables 19.6-19.17 (PORT0-
* PORTB). SCK/CTS/RTS/DE (RS-485 driver-enable) pins exist for every
* channel/group too but are not defined here: no current RA8M1 SCI driver
* code (ra_serial.c) configures synchronous clock, hardware flow control,
* or RS-485 mode, so there is nothing yet to consume them.
*/
#define GPIO_RXD0_MISO0_SCL0_1 (gpio_pinset_t){ PORT1,PIN13, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_TXD0_MOSI0_SDA0_1 (gpio_pinset_t){ PORT1,PIN12, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_RXD0_MISO0_SCL0_2 (gpio_pinset_t){ PORT6,PIN2, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_TXD0_MOSI0_SDA0_2 (gpio_pinset_t){ PORT6,PIN3, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_RXD0_MISO0_SCL0_3 (gpio_pinset_t){ PORT6,PIN10, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_TXD0_MOSI0_SDA0_3 (gpio_pinset_t){ PORT6,PIN9, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_RXD1_MISO1_SCL1_1 (gpio_pinset_t){ PORT4,PIN1, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_TXD1_MOSI1_SDA1_1 (gpio_pinset_t){ PORT4,PIN0, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_RXD1_MISO1_SCL1_2 (gpio_pinset_t){ PORT7,PIN6, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_TXD1_MOSI1_SDA1_2 (gpio_pinset_t){ PORT7,PIN7, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_RXD1_MISO1_SCL1_3 (gpio_pinset_t){ PORT2,PIN12, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_TXD1_MOSI1_SDA1_3 (gpio_pinset_t){ PORT2,PIN13, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_RXD2_MISO2_SCL2_1 (gpio_pinset_t){ PORT8,PIN2, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_TXD2_MOSI2_SDA2_1 (gpio_pinset_t){ PORT8,PIN1, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_RXD2_MISO2_SCL2_2 (gpio_pinset_t){ PORT7,PIN0, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_TXD2_MOSI2_SDA2_2 (gpio_pinset_t){ PORT4,PIN6, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_RXD2_MISO2_SCL2_3 (gpio_pinset_t){ PORTA,PIN2, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_TXD2_MOSI2_SDA2_3 (gpio_pinset_t){ PORTA,PIN3, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_RXD3_MISO3_SCL3_1 (gpio_pinset_t){ PORT4,PIN8, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_TXD3_MOSI3_SDA3_1 (gpio_pinset_t){ PORT4,PIN9, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_RXD3_MISO3_SCL3_2 (gpio_pinset_t){ PORT3,PIN9, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_TXD3_MOSI3_SDA3_2 (gpio_pinset_t){ PORT3,PIN10, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_RXD3_MISO3_SCL3_3 (gpio_pinset_t){ PORT9,PIN1, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_TXD3_MOSI3_SDA3_3 (gpio_pinset_t){ PORT9,PIN0, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_RXD4_MISO4_SCL4_1 (gpio_pinset_t){ PORT2,PIN6, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_TXD4_MOSI4_SDA4_1 (gpio_pinset_t){ PORT2,PIN5, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_RXD4_MISO4_SCL4_2 (gpio_pinset_t){ PORT4,PIN14, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_TXD4_MOSI4_SDA4_2 (gpio_pinset_t){ PORT4,PIN15, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_RXD4_MISO4_SCL4_3 (gpio_pinset_t){ PORT7,PIN15, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_TXD4_MOSI4_SDA4_3 (gpio_pinset_t){ PORT7,PIN14, (PFS_PSEL_SCI | R_PFS_PMR)}
#define GPIO_RXD9_MISO9_SCL9_1 (gpio_pinset_t){ PORT1,PIN1, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_TXD9_MOSI9_SDA9_1 (gpio_pinset_t){ PORT1,PIN2, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_RXD9_MISO9_SCL9_2 (gpio_pinset_t){ PORT2,PIN8, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_TXD9_MOSI9_SDA9_2 (gpio_pinset_t){ PORT2,PIN9, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_RXD9_MISO9_SCL9_3 (gpio_pinset_t){ PORTA,PIN15, (PFS_PSEL_SCI1 | R_PFS_PMR)}
#define GPIO_TXD9_MOSI9_SDA9_3 (gpio_pinset_t){ PORTA,PIN14, (PFS_PSEL_SCI1 | R_PFS_PMR)}
/* GPIO Configuration */
#define GPIO_OUTPUT R_PFS_PDR
#define GPIO_INPUT ~(R_PFS_PDR | 0xFFFFFFFF)
#define GPIO_LOW_DRIVE ~(R_PFS_DSCR | 0xFFFFFFFF)
#define GPIO_MIDDLE_DRIVE R_PFS_DSCR
#define GPIO_OUTPUT_HIGH R_PFS_PODR
#define GPIO_OUTPUT_LOW ~(R_PFS_PODR | 0xFFFFFFFF)
#define GPIO_PIN_INVALID (gpio_pinset_t){ PORT_INVALID, PIN_INVALID, 0xFFFFFFFF }
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_PINMAP_H */

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/****************************************************************************
* arch/arm/src/ra8m1/ra_allocateheap.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <assert.h>
#include <nuttx/debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/kmalloc.h>
#include <arch/board/board.h>
#include "mpu.h"
#include "arm_internal.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region. Size determined at link time.
* Kernel .bss region Size determined at link time.
* Kernel IDLE thread stack. Size determined by
* CONFIG_IDLETHREAD_STACKSIZE.
* Padding for alignment
* User .data region. Size determined at link time.
* User .bss region Size determined at link time.
* Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
* User heap. Extends to the end of SRAM.
*
****************************************************************************/
void up_allocate_heap(void **heap_start, size_t *heap_size)
{
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

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/****************************************************************************
* arch/arm/src/ra8m1/ra_clockconfig.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Clock generation set-up, from the BOARD_* clock options in board.h.
*
* The sequence follows RA8M1 User's Manual section 8.11 (initial system
* clock setting, oscillator and PLL settings, peripheral module-dedicated
* clock setting) and the FSP reference start-up code:
*
* 1. start the oscillators that are used (HOCO, MOSC); the MOCO is
* already running because the MCU starts from it,
* 2. start the PLLs that are used,
* 3. set the flash wait states for the final ICLK and enable the flash
* cache,
* 4. set the dividers and switch the system clock source,
* 5. configure the SCI clock.
*
* A flat (no TrustZone) image runs in the secure state, so every register
* here is the secure instance and PRCR_S protects them.
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "arm_internal.h"
#include "ra_clockconfig.h"
#include "hardware/ra8m1_fcache.h"
#include "hardware/ra8m1_system.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SCKDIVCR/SCKDIVCR2 divider encoding */
#define RA_SCKDIV_CODE(d) \
((d) == 1 ? 0 : (d) == 2 ? 1 : (d) == 4 ? 2 : (d) == 8 ? 3 : \
(d) == 16 ? 4 : (d) == 32 ? 5 : (d) == 64 ? 6 : (d) == 3 ? 8 : \
(d) == 6 ? 9 : 10)
#define RA_SCKDIVCR_VALUE \
((RA_SCKDIV_CODE(BOARD_FCLK_DIVIDER) << R_SYSTEM_SCKDIVCR_FCK_SHIFT) | \
(RA_SCKDIV_CODE(BOARD_ICLK_DIVIDER) << R_SYSTEM_SCKDIVCR_ICK_SHIFT) | \
(RA_SCKDIV_CODE(BOARD_PCLKE_DIVIDER) << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) | \
(RA_SCKDIV_CODE(BOARD_BCLK_DIVIDER) << R_SYSTEM_SCKDIVCR_BCK_SHIFT) | \
(RA_SCKDIV_CODE(BOARD_PCLKA_DIVIDER) << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) | \
(RA_SCKDIV_CODE(BOARD_PCLKB_DIVIDER) << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) | \
(RA_SCKDIV_CODE(BOARD_PCLKC_DIVIDER) << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) | \
(RA_SCKDIV_CODE(BOARD_PCLKD_DIVIDER) << R_SYSTEM_SCKDIVCR_PCKD_SHIFT))
#define RA_SCKDIVCR2_VALUE \
(RA_SCKDIV_CODE(BOARD_CPUCLK_DIVIDER) << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT)
#define RA_SCKDIVCR2_SWITCH_VALUE \
(RA_SCKDIV_CODE(RA_CPUCLK_SWITCH_DIVIDER) << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT)
/* System clock source: BOARD_SYSCLK_SOURCE is already the SCKSCR.CKSEL
* value (board.h sets it to one of the R_SYSTEM_SCKSCR_CKSEL_* codes), so
* it is written to the register as-is; ra_clockconfig.h has already
* checked it is one of the four this port supports.
*/
#define RA_SCKSCR_VALUE BOARD_SYSCLK_SOURCE
/* MOSC: drive capability by frequency (as FSP), and the wait time. MOMCR
* bit 4 must be written as 1. MOSCWTCR.MSTS counts LOCO based cycles;
* pick the shortest setting that is at least the requested time (in
* tenths of a microsecond, from the manual's table).
*/
#if RA_USE_MOSC
# if RA_MOSC_FREQUENCY >= 24000000
# define RA_MOSC_MODRV0 5
# else
# define RA_MOSC_MODRV0 3
# endif
# if BOARD_MOSC_EXTERNAL_CLOCK
# define RA_MOMCR_VALUE (R_SYSTEM_MOMCR_AGCEN | R_SYSTEM_MOMCR_MOSEL | \
(RA_MOSC_MODRV0 << R_SYSTEM_MOMCR_MODRV0_SHIFT))
# define RA_MOSCWTCR_VALUE 0
# else
# define RA_MOMCR_VALUE (R_SYSTEM_MOMCR_AGCEN | \
(RA_MOSC_MODRV0 << R_SYSTEM_MOMCR_MODRV0_SHIFT))
# define RA_MOSC_WAIT_X10 (BOARD_MOSC_STABILIZATION_US * 10)
# define RA_MOSCWTCR_VALUE \
(RA_MOSC_WAIT_X10 <= 114 ? 0 : RA_MOSC_WAIT_X10 <= 1335 ? 1 : \
RA_MOSC_WAIT_X10 <= 2556 ? 2 : RA_MOSC_WAIT_X10 <= 4997 ? 3 : \
RA_MOSC_WAIT_X10 <= 9880 ? 4 : RA_MOSC_WAIT_X10 <= 20866 ? 5 : \
RA_MOSC_WAIT_X10 <= 40398 ? 6 : RA_MOSC_WAIT_X10 <= 81902 ? 7 : \
RA_MOSC_WAIT_X10 <= 163689 ? 8 : 9)
# endif
#endif
/* PLL1 and PLL2 settings. PLLMUL holds the multiplier minus 1. The
* fraction (PLLMULNF) and the source select bit (PLSRCSEL) are written
* from board.h as-is: BOARD_PLLn_MULTIPLIER_FRACTION and BOARD_PLLn_SOURCE
* are already the real, correctly shifted register field values (see
* board.h and ra_clockconfig.h), not raw codes needing a shift here. The
* output dividers are held as the divider minus 1.
*/
#if RA_USE_PLL1
# define RA_PLLCCR_VALUE \
(((BOARD_PLL1_MULTIPLIER - 1) << R_SYSTEM_PLLCCR_PLLMUL_SHIFT) | \
BOARD_PLL1_MULTIPLIER_FRACTION | BOARD_PLL1_SOURCE | \
((BOARD_PLL1_INPUT_DIVIDER - 1) << R_SYSTEM_PLLCCR_PLIDIV_SHIFT))
# define RA_PLLCCR2_VALUE \
(((BOARD_PLL1_DIVIDER_P - 1) << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) | \
((BOARD_PLL1_DIVIDER_Q - 1) << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) | \
((BOARD_PLL1_DIVIDER_R - 1) << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT))
#endif
#if RA_USE_PLL2
# define RA_PLL2CCR_VALUE \
(((BOARD_PLL2_MULTIPLIER - 1) << R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT) | \
BOARD_PLL2_MULTIPLIER_FRACTION | BOARD_PLL2_SOURCE | \
((BOARD_PLL2_INPUT_DIVIDER - 1) << R_SYSTEM_PLL2CCR_PL2IDIV_SHIFT))
# define RA_PLL2CCR2_VALUE \
(((BOARD_PLL2_DIVIDER_P - 1) << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) | \
((BOARD_PLL2_DIVIDER_Q - 1) << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) | \
((BOARD_PLL2_DIVIDER_R - 1) << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT))
#endif
/* SCICLK: source select codes (SCICKCR.SCICKSEL) and divider codes
* (SCICKDIVCR.SCICKDIV, non-linear like the system clock dividers).
*/
#if RA_USE_SCICLK
# if BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_HOCO
# define RA_SCICKSEL_VALUE 0
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_MOSC
# define RA_SCICKSEL_VALUE 3
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1P
# define RA_SCICKSEL_VALUE 5
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2P
# define RA_SCICKSEL_VALUE 6
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1Q
# define RA_SCICKSEL_VALUE 7
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1R
# define RA_SCICKSEL_VALUE 8
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2Q
# define RA_SCICKSEL_VALUE 9
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2R
# define RA_SCICKSEL_VALUE 10
# else
# define RA_SCICKSEL_VALUE 1
# endif
# define RA_SCICKDIV_VALUE \
(BOARD_SCICLK_DIVIDER == 1 ? 0 : BOARD_SCICLK_DIVIDER == 2 ? 1 : \
BOARD_SCICLK_DIVIDER == 4 ? 2 : BOARD_SCICLK_DIVIDER == 6 ? 3 : \
BOARD_SCICLK_DIVIDER == 8 ? 4 : BOARD_SCICLK_DIVIDER == 3 ? 5 : 6)
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: ra_delay_us
*
* Description:
* Busy wait for at least the given time. No timer is available this
* early, so this counts loop iterations. Each iteration takes at least
* one CPU clock cycle, so assuming one cycle per iteration can only make
* the wait longer than requested, never shorter.
*
* Input Parameters:
* us - Time to wait, in microseconds.
* cpuclk_hz - An upper bound for the CPU clock frequency during the wait.
*
****************************************************************************/
#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_PLL
static void ra_delay_us(uint32_t us, uint32_t cpuclk_hz)
{
uint32_t loops = us * (cpuclk_hz / 1000000);
if (loops == 0)
{
loops = 1;
}
__asm__ __volatile__
(
"1:\n"
"\tsubs %0, %0, #1\n"
"\tbne 1b\n"
: "+r" (loops)
:
: "cc"
);
}
#endif
/****************************************************************************
* Name: ra_wait_stable
*
* Description:
* Wait until the given OSCSF flag is set, meaning that the oscillator or
* PLL is stable and can be used.
*
****************************************************************************/
#if RA_USE_HOCO || RA_USE_MOSC || RA_USE_PLL1 || RA_USE_PLL2
static void ra_wait_stable(uint8_t flag)
{
while ((getreg8(R_SYSTEM_OSCSF) & flag) == 0)
{
}
}
#endif
/****************************************************************************
* Name: ra_hoco_start
****************************************************************************/
#if RA_USE_HOCO
static void ra_hoco_start(void)
{
/* The HOCO is stopped after reset unless OFS1.HOCOEN starts it. Its
* frequency register (HOCOCR2) comes out of reset holding
* OFS1.HOCOFRQ0, the same BOARD_HOCO_FREQUENCY that RA_HOCO_FREQUENCY
* comes from, so only the start is needed here.
*/
if ((getreg8(R_SYSTEM_HOCOCR) & R_SYSTEM_HOCOCR_HCSTP) != 0)
{
putreg8(0, R_SYSTEM_HOCOCR);
}
ra_wait_stable(R_SYSTEM_OSCSF_HOCOSF);
}
#endif
/****************************************************************************
* Name: ra_mosc_start
****************************************************************************/
#if RA_USE_MOSC
static void ra_mosc_start(void)
{
/* MOMCR and MOSCWTCR may only be written while the oscillator is
* stopped. After that, start it and wait for it to stabilize.
*/
if ((getreg8(R_SYSTEM_MOSCCR) & R_SYSTEM_MOSCCR_MOSTP) != 0)
{
putreg8(RA_MOMCR_VALUE, R_SYSTEM_MOMCR);
putreg8(RA_MOSCWTCR_VALUE, R_SYSTEM_MOSCWTCR);
putreg8(0, R_SYSTEM_MOSCCR);
}
ra_wait_stable(R_SYSTEM_OSCSF_MOSCSF);
}
#endif
/****************************************************************************
* Name: ra_pll1_start
****************************************************************************/
#if RA_USE_PLL1
static void ra_pll1_start(void)
{
/* PLL1 is stopped after reset, so its settings can be written */
putreg16(RA_PLLCCR_VALUE, R_SYSTEM_PLLCCR);
putreg16(RA_PLLCCR2_VALUE, R_SYSTEM_PLLCCR2);
putreg8(0, R_SYSTEM_PLLCR);
ra_wait_stable(R_SYSTEM_OSCSF_PLLSF);
}
#endif
/****************************************************************************
* Name: ra_pll2_start
****************************************************************************/
#if RA_USE_PLL2
static void ra_pll2_start(void)
{
putreg16(RA_PLL2CCR_VALUE, R_SYSTEM_PLL2CCR);
putreg16(RA_PLL2CCR2_VALUE, R_SYSTEM_PLL2CCR2);
putreg8(0, R_SYSTEM_PLL2CR);
ra_wait_stable(R_SYSTEM_OSCSF_PLL2SF);
}
#endif
/****************************************************************************
* Name: ra_sysclk_switch
*
* Description:
* Set the dividers and switch the system clock source, keeping the
* frequencies inside their limits at every step.
*
* The MCU starts from the MOCO with every divider at 1. All the
* configurable sources are at least as fast as the MOCO, so the dividers
* are written first: nothing can run faster than configured while the
* source changes. The dividers of ICLK and below are written before the
* CPUCLK one so that CPUCLK never drops below ICLK.
*
* Each register is read back after being written, as the manual asks
* (section 8.12.1), before the next step.
*
****************************************************************************/
static void ra_sysclk_switch(void)
{
putreg32(RA_SCKDIVCR_VALUE, R_SYSTEM_SCKDIVCR);
getreg32(R_SYSTEM_SCKDIVCR);
#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_PLL
/* The PLL is selected with CPUCLK at or below the package limit. If the
* final CPUCLK is above it, start with a slower CPU divider, wait for the
* PLL to settle and only then lower the divider (RA8M1 User's Manual
* figure 8.13).
*/
# if RA_CPUCLK_FREQUENCY > RA_PLL_SWITCH_MAX_CPUCLK
putreg8(RA_SCKDIVCR2_SWITCH_VALUE, R_SYSTEM_SCKDIVCR2);
getreg8(R_SYSTEM_SCKDIVCR2);
putreg8(RA_SCKSCR_VALUE, R_SYSTEM_SCKSCR);
getreg8(R_SYSTEM_SCKSCR);
ra_delay_us(RA_CLOCK_SETTLE_US, RA_CPUCLK_FREQUENCY);
putreg8(RA_SCKDIVCR2_VALUE, R_SYSTEM_SCKDIVCR2);
getreg8(R_SYSTEM_SCKDIVCR2);
ra_delay_us(RA_CLOCK_SETTLE_US, RA_CPUCLK_FREQUENCY);
# else
putreg8(RA_SCKDIVCR2_VALUE, R_SYSTEM_SCKDIVCR2);
getreg8(R_SYSTEM_SCKDIVCR2);
putreg8(RA_SCKSCR_VALUE, R_SYSTEM_SCKSCR);
getreg8(R_SYSTEM_SCKSCR);
ra_delay_us(RA_CLOCK_SETTLE_US, RA_CPUCLK_FREQUENCY);
# endif
#else
putreg8(RA_SCKDIVCR2_VALUE, R_SYSTEM_SCKDIVCR2);
getreg8(R_SYSTEM_SCKDIVCR2);
putreg8(RA_SCKSCR_VALUE, R_SYSTEM_SCKSCR);
getreg8(R_SYSTEM_SCKSCR);
#endif
}
/****************************************************************************
* Name: ra_sciclk_set
*
* Description:
* Select the SCICLK source and divider with the switching handshake of
* the manual (section 8.2.48): request the switch, wait until SCICLK is
* stopped, write the divider and source, release the request, and wait
* until SCICLK runs again.
*
* Changing the divider from a value other than 1 needs the SCI modules
* in the module-stop state. That is the case here: they are all stopped
* after reset and this runs before any of them is started.
*
****************************************************************************/
#if RA_USE_SCICLK
static void ra_sciclk_set(void)
{
modifyreg8(R_SYSTEM_SCICKCR, 0, R_SYSTEM_SCICKCR_CKSREQ);
while ((getreg8(R_SYSTEM_SCICKCR) & R_SYSTEM_SCICKCR_CKSRDY) == 0)
{
}
putreg8(RA_SCICKDIV_VALUE, R_SYSTEM_SCICKDIVCR);
putreg8(RA_SCICKSEL_VALUE | R_SYSTEM_SCICKCR_CKSREQ, R_SYSTEM_SCICKCR);
putreg8(RA_SCICKSEL_VALUE, R_SYSTEM_SCICKCR);
while ((getreg8(R_SYSTEM_SCICKCR) & R_SYSTEM_SCICKCR_CKSRDY) != 0)
{
}
}
#endif
/****************************************************************************
* Name: ra_fcache_enable
*
* Description:
* Enable the flash cache, as the FSP reference start-up code does
* (R_BSP_FlashCacheEnable()): invalidate it and wait for the
* invalidation to finish (RA8M1 User's Manual, Flash Memory chapter,
* "Operation") before enabling it.
*
****************************************************************************/
static void ra_fcache_enable(void)
{
putreg16(R_FCACHE_FCACHEIV_FCACHEIV, R_FCACHE_FCACHEIV);
while ((getreg16(R_FCACHE_FCACHEIV) & R_FCACHE_FCACHEIV_FCACHEIV) != 0)
{
}
putreg16(R_FCACHE_FCACHEE_FCACHEEN, R_FCACHE_FCACHEE);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: ra_clockconfig
*
* Description:
* Called to initialize the RA8M1. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the BOARD_* clock options in board.h.
*
****************************************************************************/
void ra_clockconfig(void)
{
/* Unlock the clock generation (PRC0) and low power/module stop (PRC1)
* registers.
*/
putreg16((R_SYSTEM_PRCR_S_PRKEY_V0XA5 | R_SYSTEM_PRCR_S_PRC0 |
R_SYSTEM_PRCR_S_PRC1), R_SYSTEM_PRCR_S);
/* The MCU is in high-speed operating mode after reset, which is what
* every configuration allowed here needs, so OPCCR is left alone.
*/
/* Start the oscillators the configuration uses before anything that
* depends on them (the PLLs). The MOCO is already running.
*/
#if RA_USE_HOCO
ra_hoco_start();
#endif
#if RA_USE_MOSC
ra_mosc_start();
#endif
#if RA_USE_PLL1
ra_pll1_start();
#endif
#if RA_USE_PLL2
ra_pll2_start();
#endif
/* The flash needs its wait states for the final ICLK. Setting them
* before the clock speeds up is safe: extra wait states at a lower
* frequency only cost time.
*/
putreg8(RA_FLASH_WAIT_STATES, R_FCACHE_FLWT);
ra_fcache_enable();
ra_sysclk_switch();
#if RA_USE_SCICLK
ra_sciclk_set();
#endif
/* Lock the protected registers again */
putreg16(R_SYSTEM_PRCR_S_PRKEY_V0XA5, R_SYSTEM_PRCR_S);
}

656
arch/arm/src/ra8m1/ra_clockconfig.h Normal file
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@ -0,0 +1,656 @@
/****************************************************************************
* arch/arm/src/ra8m1/ra_clockconfig.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_RA_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_RA8M1_RA_CLOCKCONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "hardware/ra8m1_system.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clock frequencies derived from the BOARD_* clock options.
*
* The clock tree is chosen by the board in <arch/board/board.h> (see the
* "Clocking" section of that file for every option and its valid values).
* Everything here is a compile-time constant, and every limit in the RA8M1
* User's Manual chapter 8 (Tables 8.1 and 8.2 and their notes) is checked
* with #error, so a missing option or an invalid combination fails to build
* instead of producing a clock the MCU is not specified for. Some of the
* results are unsigned long long constants (the PLL VCO does not fit in 32
* bits during the calculation); cast them where a plain integer is needed.
*/
/* Options the board has to define. There is no default: a board.h that
* does not describe its clock tree does not build.
*/
#ifndef BOARD_HOCO_FREQUENCY
# error "board.h must define BOARD_HOCO_FREQUENCY"
#endif
#ifndef BOARD_SYSCLK_SOURCE
# error "board.h must define BOARD_SYSCLK_SOURCE"
#endif
#ifndef BOARD_OFS2_DCDC
# error "board.h must define BOARD_OFS2_DCDC"
#endif
#if !defined(BOARD_CPUCLK_DIVIDER) || !defined(BOARD_ICLK_DIVIDER) || \
!defined(BOARD_PCLKA_DIVIDER) || !defined(BOARD_PCLKB_DIVIDER) || \
!defined(BOARD_PCLKC_DIVIDER) || !defined(BOARD_PCLKD_DIVIDER) || \
!defined(BOARD_PCLKE_DIVIDER) || !defined(BOARD_FCLK_DIVIDER) || \
!defined(BOARD_BCLK_DIVIDER)
# error "board.h must define BOARD_CPUCLK/ICLK/PCLKA-E/FCLK/BCLK_DIVIDER"
#endif
/* SCICLK source selectors, for BOARD_SCICLK_SOURCE.
*
* Every other *_SOURCE option reuses the real register-field value from
* hardware/ra8m1_system.h (see board.h). SCICKCR.SCICKSEL has no such
* generated names -- the SVD gives this field no enumeratedValues -- so
* this is the one selector this port has to invent, and it is kept here,
* private to this file, rather than in board.h: board.h only references
* these names (no #include needed for that -- a macro's replacement text
* is resolved where it is used, not where it is written), and the actual
* SCICKCR.SCICKSEL codes these translate to are computed in
* ra_clockconfig.c, independently of the numbering used here.
*/
#define RA_SCICLK_SRC_MOCO 1
#define RA_SCICLK_SRC_HOCO 2
#define RA_SCICLK_SRC_MOSC 3
#define RA_SCICLK_SRC_PLL1P 4
#define RA_SCICLK_SRC_PLL1Q 5
#define RA_SCICLK_SRC_PLL1R 6
#define RA_SCICLK_SRC_PLL2P 7
#define RA_SCICLK_SRC_PLL2Q 8
#define RA_SCICLK_SRC_PLL2R 9
/* Which oscillators, PLLs and dedicated clocks the configuration needs.
* Each RA_USE_* is 0 or 1.
*
* SCICLK is needed as soon as one SCI UART is enabled: the baud rate
* generator of every SCI runs from it.
*/
#if defined(CONFIG_RA_SCI0_UART) || defined(CONFIG_RA_SCI1_UART) || \
defined(CONFIG_RA_SCI2_UART) || defined(CONFIG_RA_SCI3_UART) || \
defined(CONFIG_RA_SCI4_UART) || defined(CONFIG_RA_SCI9_UART)
# define RA_USE_SCICLK 1
#else
# define RA_USE_SCICLK 0
#endif
#if RA_USE_SCICLK
# if !defined(BOARD_SCICLK_SOURCE) || !defined(BOARD_SCICLK_DIVIDER)
# error "board.h must define BOARD_SCICLK_SOURCE and BOARD_SCICLK_DIVIDER"
# endif
#endif
#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_PLL || \
(RA_USE_SCICLK && (BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1P || \
BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1Q || \
BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1R))
# define RA_USE_PLL1 1
#else
# define RA_USE_PLL1 0
#endif
#if RA_USE_SCICLK && (BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2P || \
BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2Q || \
BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2R)
# define RA_USE_PLL2 1
#else
# define RA_USE_PLL2 0
#endif
#if RA_USE_PLL1
# if !defined(BOARD_PLL1_SOURCE) || !defined(BOARD_PLL1_INPUT_DIVIDER) || \
!defined(BOARD_PLL1_MULTIPLIER) || !defined(BOARD_PLL1_MULTIPLIER_FRACTION) || \
!defined(BOARD_PLL1_DIVIDER_P) || !defined(BOARD_PLL1_DIVIDER_Q) || \
!defined(BOARD_PLL1_DIVIDER_R)
# error "PLL1 is used: board.h must define all the BOARD_PLL1_* options"
# endif
#endif
#if RA_USE_PLL2
# if !defined(BOARD_PLL2_SOURCE) || !defined(BOARD_PLL2_INPUT_DIVIDER) || \
!defined(BOARD_PLL2_MULTIPLIER) || !defined(BOARD_PLL2_MULTIPLIER_FRACTION) || \
!defined(BOARD_PLL2_DIVIDER_P) || !defined(BOARD_PLL2_DIVIDER_Q) || \
!defined(BOARD_PLL2_DIVIDER_R)
# error "PLL2 is used: board.h must define all the BOARD_PLL2_* options"
# endif
#endif
#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_HOCO || \
(RA_USE_SCICLK && BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_HOCO) || \
(RA_USE_PLL1 && BOARD_PLL1_SOURCE == R_SYSTEM_PLLCCR_PLSRCSEL) || \
(RA_USE_PLL2 && BOARD_PLL2_SOURCE == R_SYSTEM_PLL2CCR_PL2SRCSEL)
# define RA_USE_HOCO 1
#else
# define RA_USE_HOCO 0
#endif
#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_MAIN_CLOCK_OSCILLATOR || \
(RA_USE_SCICLK && BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_MOSC) || \
(RA_USE_PLL1 && BOARD_PLL1_SOURCE == 0) || \
(RA_USE_PLL2 && BOARD_PLL2_SOURCE == 0)
# define RA_USE_MOSC 1
#else
# define RA_USE_MOSC 0
#endif
#if BOARD_SYSCLK_SOURCE != R_SYSTEM_SCKSCR_CKSEL_MOCO && \
BOARD_SYSCLK_SOURCE != R_SYSTEM_SCKSCR_CKSEL_HOCO && \
BOARD_SYSCLK_SOURCE != R_SYSTEM_SCKSCR_CKSEL_MAIN_CLOCK_OSCILLATOR && \
BOARD_SYSCLK_SOURCE != R_SYSTEM_SCKSCR_CKSEL_PLL
# error "BOARD_SYSCLK_SOURCE must be R_SYSTEM_SCKSCR_CKSEL_MOCO, _HOCO, _MAIN_CLOCK_OSCILLATOR or _PLL"
#endif
/* Oscillators */
#define RA_MOCO_FREQUENCY 8000000
/* The HOCO frequency after reset is the one programmed into OFS1 (see
* ra_option_setting.c), so BOARD_HOCO_FREQUENCY is used for both.
*/
#if BOARD_HOCO_FREQUENCY != 16000000 && BOARD_HOCO_FREQUENCY != 18000000 && \
BOARD_HOCO_FREQUENCY != 20000000 && BOARD_HOCO_FREQUENCY != 32000000 && \
BOARD_HOCO_FREQUENCY != 48000000
# error "BOARD_HOCO_FREQUENCY must be 16, 18, 20, 32 or 48 MHz"
#endif
#define RA_HOCO_FREQUENCY BOARD_HOCO_FREQUENCY
#if RA_USE_MOSC
# if !defined(BOARD_MOSC_FREQUENCY) || !defined(BOARD_MOSC_EXTERNAL_CLOCK) || \
!defined(BOARD_MOSC_STABILIZATION_US)
# error "MOSC is used: board.h must define BOARD_MOSC_FREQUENCY, BOARD_MOSC_EXTERNAL_CLOCK and BOARD_MOSC_STABILIZATION_US"
# endif
# if BOARD_MOSC_FREQUENCY < 8000000 || BOARD_MOSC_FREQUENCY > 48000000
# error "BOARD_MOSC_FREQUENCY must be 8 MHz to 48 MHz"
# endif
# if !BOARD_MOSC_EXTERNAL_CLOCK && \
(BOARD_MOSC_STABILIZATION_US < 12 || BOARD_MOSC_STABILIZATION_US > 31139)
# error "BOARD_MOSC_STABILIZATION_US must be 12 us to 31139 us"
# endif
# define RA_MOSC_FREQUENCY BOARD_MOSC_FREQUENCY
#endif
/* Divider validity. The dividers are the values 1, 2, 3, 4, 6, 8, 12, 16,
* 32 and 64 (SCKDIVCR/SCKDIVCR2 encode them non-linearly).
*/
#define RA_SCKDIV_VALID(d) \
((d) == 1 || (d) == 2 || (d) == 3 || (d) == 4 || (d) == 6 || \
(d) == 8 || (d) == 12 || (d) == 16 || (d) == 32 || (d) == 64)
#define RA_SCKDIV_FAMILY_A(d) \
((d) == 2 || (d) == 4 || (d) == 8 || (d) == 16 || (d) == 32 || (d) == 64)
#define RA_SCKDIV_FAMILY_B(d) ((d) == 3 || (d) == 6 || (d) == 12)
#define RA_PLL_DIV_P_VALID(d) \
((d) == 2 || (d) == 4 || (d) == 6 || (d) == 8 || (d) == 16)
#define RA_PLL_DIV_QR_VALID(d) \
((d) == 2 || (d) == 3 || (d) == 4 || (d) == 5 || (d) == 6 || \
(d) == 8 || (d) == 9)
#define RA_SCICLK_DIV_VALID(d) \
((d) == 1 || (d) == 2 || (d) == 3 || (d) == 4 || (d) == 5 || \
(d) == 6 || (d) == 8)
/* PLL1 and PLL2 */
#if RA_USE_PLL1
# if BOARD_PLL1_SOURCE == 0
# define RA_PLL1_SOURCE_FREQUENCY RA_MOSC_FREQUENCY
# elif BOARD_PLL1_SOURCE == R_SYSTEM_PLLCCR_PLSRCSEL
# define RA_PLL1_SOURCE_FREQUENCY RA_HOCO_FREQUENCY
# else
# error "BOARD_PLL1_SOURCE must be 0 (MOSC) or R_SYSTEM_PLLCCR_PLSRCSEL (HOCO)"
# endif
# if BOARD_PLL1_INPUT_DIVIDER < 1 || BOARD_PLL1_INPUT_DIVIDER > 4
# error "BOARD_PLL1_INPUT_DIVIDER must be 1 to 4"
# endif
# if BOARD_PLL1_MULTIPLIER < 53 || BOARD_PLL1_MULTIPLIER > 180
# error "BOARD_PLL1_MULTIPLIER must be 53 to 180"
# endif
# if BOARD_PLL1_MULTIPLIER_FRACTION == R_SYSTEM_PLLCCR_PLLMULNF_V0_33_1_3
# define RA_PLL1_MULF6 2 /* 1/3 = 2/6 */
# elif BOARD_PLL1_MULTIPLIER_FRACTION == R_SYSTEM_PLLCCR_PLLMULNF_V0_50_1_2
# define RA_PLL1_MULF6 3 /* 1/2 = 3/6 */
# elif BOARD_PLL1_MULTIPLIER_FRACTION == R_SYSTEM_PLLCCR_PLLMULNF_V0_66_2_3
# define RA_PLL1_MULF6 4 /* 2/3 = 4/6 */
# elif BOARD_PLL1_MULTIPLIER_FRACTION == \
R_SYSTEM_PLLCCR_PLLMULNF_V0_00_VALUE_AFTER_RESET
# define RA_PLL1_MULF6 0
# else
# error "BOARD_PLL1_MULTIPLIER_FRACTION must be one of the R_SYSTEM_PLLCCR_PLLMULNF_* codes"
# endif
# define RA_PLL1_INPUT_FREQUENCY (RA_PLL1_SOURCE_FREQUENCY / BOARD_PLL1_INPUT_DIVIDER)
# define RA_PLL1_VCO_FREQUENCY \
((RA_PLL1_INPUT_FREQUENCY * (6ULL * BOARD_PLL1_MULTIPLIER + RA_PLL1_MULF6)) / 6ULL)
# define RA_PLL1P_FREQUENCY (RA_PLL1_VCO_FREQUENCY / BOARD_PLL1_DIVIDER_P)
# define RA_PLL1Q_FREQUENCY (RA_PLL1_VCO_FREQUENCY / BOARD_PLL1_DIVIDER_Q)
# define RA_PLL1R_FREQUENCY (RA_PLL1_VCO_FREQUENCY / BOARD_PLL1_DIVIDER_R)
# if RA_PLL1_SOURCE_FREQUENCY < 8000000 || RA_PLL1_SOURCE_FREQUENCY > 48000000
# error "PLL1 source clock must be 8 MHz to 48 MHz"
# endif
# if RA_PLL1_INPUT_FREQUENCY < 6000000 || RA_PLL1_INPUT_FREQUENCY > 12000000
# error "PLL1 input frequency after the input divider must be 6 MHz to 12 MHz"
# endif
# if RA_PLL1_VCO_FREQUENCY < 640000000ULL || RA_PLL1_VCO_FREQUENCY > 1440000000ULL
# error "PLL1 VCO frequency must be 640 MHz to 1440 MHz"
# endif
# if !RA_PLL_DIV_P_VALID(BOARD_PLL1_DIVIDER_P)
# error "PLL1 output P divider must be 2, 4, 6, 8 or 16"
# endif
# if !RA_PLL_DIV_QR_VALID(BOARD_PLL1_DIVIDER_Q) || !RA_PLL_DIV_QR_VALID(BOARD_PLL1_DIVIDER_R)
# error "PLL1 output Q/R dividers must be 2, 3, 4, 5, 6, 8 or 9"
# endif
# if RA_PLL1P_FREQUENCY < 40000000 || RA_PLL1P_FREQUENCY > 480000000
# error "PLL1P must be 40 MHz to 480 MHz"
# endif
# if RA_PLL1Q_FREQUENCY < 71000000 || RA_PLL1Q_FREQUENCY > 480000000
# error "PLL1Q must be 71 MHz to 480 MHz"
# endif
# if RA_PLL1R_FREQUENCY < 71000000 || RA_PLL1R_FREQUENCY > 480000000
# error "PLL1R must be 71 MHz to 480 MHz"
# endif
#endif /* RA_USE_PLL1 */
#if RA_USE_PLL2
# if BOARD_PLL2_SOURCE == 0
# define RA_PLL2_SOURCE_FREQUENCY RA_MOSC_FREQUENCY
# elif BOARD_PLL2_SOURCE == R_SYSTEM_PLL2CCR_PL2SRCSEL
# define RA_PLL2_SOURCE_FREQUENCY RA_HOCO_FREQUENCY
# else
# error "BOARD_PLL2_SOURCE must be 0 (MOSC) or R_SYSTEM_PLL2CCR_PL2SRCSEL (HOCO)"
# endif
# if BOARD_PLL2_INPUT_DIVIDER < 1 || BOARD_PLL2_INPUT_DIVIDER > 4
# error "BOARD_PLL2_INPUT_DIVIDER must be 1 to 4"
# endif
# if BOARD_PLL2_MULTIPLIER < 53 || BOARD_PLL2_MULTIPLIER > 180
# error "BOARD_PLL2_MULTIPLIER must be 53 to 180"
# endif
# if BOARD_PLL2_MULTIPLIER_FRACTION == R_SYSTEM_PLL2CCR_PLL2MULNF_V0_33_1_3
# define RA_PLL2_MULF6 2 /* 1/3 = 2/6 */
# elif BOARD_PLL2_MULTIPLIER_FRACTION == R_SYSTEM_PLL2CCR_PLL2MULNF_V0_50_1_2
# define RA_PLL2_MULF6 3 /* 1/2 = 3/6 */
# elif BOARD_PLL2_MULTIPLIER_FRACTION == R_SYSTEM_PLL2CCR_PLL2MULNF_V0_66_2_3
# define RA_PLL2_MULF6 4 /* 2/3 = 4/6 */
# elif BOARD_PLL2_MULTIPLIER_FRACTION == \
R_SYSTEM_PLL2CCR_PLL2MULNF_V0_00_VALUE_AFTER_RESET
# define RA_PLL2_MULF6 0
# else
# error "BOARD_PLL2_MULTIPLIER_FRACTION must be one of the R_SYSTEM_PLL2CCR_PLL2MULNF_* codes"
# endif
# define RA_PLL2_INPUT_FREQUENCY (RA_PLL2_SOURCE_FREQUENCY / BOARD_PLL2_INPUT_DIVIDER)
# define RA_PLL2_VCO_FREQUENCY \
((RA_PLL2_INPUT_FREQUENCY * (6ULL * BOARD_PLL2_MULTIPLIER + RA_PLL2_MULF6)) / 6ULL)
# define RA_PLL2P_FREQUENCY (RA_PLL2_VCO_FREQUENCY / BOARD_PLL2_DIVIDER_P)
# define RA_PLL2Q_FREQUENCY (RA_PLL2_VCO_FREQUENCY / BOARD_PLL2_DIVIDER_Q)
# define RA_PLL2R_FREQUENCY (RA_PLL2_VCO_FREQUENCY / BOARD_PLL2_DIVIDER_R)
# if RA_PLL2_SOURCE_FREQUENCY < 8000000 || RA_PLL2_SOURCE_FREQUENCY > 48000000
# error "PLL2 source clock must be 8 MHz to 48 MHz"
# endif
# if RA_PLL2_INPUT_FREQUENCY < 6000000 || RA_PLL2_INPUT_FREQUENCY > 12000000
# error "PLL2 input frequency after the input divider must be 6 MHz to 12 MHz"
# endif
# if RA_PLL2_VCO_FREQUENCY < 640000000ULL || RA_PLL2_VCO_FREQUENCY > 1440000000ULL
# error "PLL2 VCO frequency must be 640 MHz to 1440 MHz"
# endif
# if !RA_PLL_DIV_P_VALID(BOARD_PLL2_DIVIDER_P)
# error "PLL2 output P divider must be 2, 4, 6, 8 or 16"
# endif
# if !RA_PLL_DIV_QR_VALID(BOARD_PLL2_DIVIDER_Q) || !RA_PLL_DIV_QR_VALID(BOARD_PLL2_DIVIDER_R)
# error "PLL2 output Q/R dividers must be 2, 3, 4, 5, 6, 8 or 9"
# endif
# if RA_PLL2P_FREQUENCY < 40000000 || RA_PLL2P_FREQUENCY > 480000000
# error "PLL2P must be 40 MHz to 480 MHz"
# endif
# if RA_PLL2Q_FREQUENCY < 71000000 || RA_PLL2Q_FREQUENCY > 480000000
# error "PLL2Q must be 71 MHz to 480 MHz"
# endif
# if RA_PLL2R_FREQUENCY < 71000000 || RA_PLL2R_FREQUENCY > 480000000
# error "PLL2R must be 71 MHz to 480 MHz"
# endif
#endif /* RA_USE_PLL2 */
/* System clock source */
#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_HOCO
# define RA_SYSCLK_FREQUENCY RA_HOCO_FREQUENCY
#elif BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_MAIN_CLOCK_OSCILLATOR
# define RA_SYSCLK_FREQUENCY RA_MOSC_FREQUENCY
#elif BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_PLL
# define RA_SYSCLK_FREQUENCY RA_PLL1P_FREQUENCY
#else
# define RA_SYSCLK_FREQUENCY RA_MOCO_FREQUENCY
#endif
/* Clocks derived from the system clock */
#define RA_CPUCLK_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_CPUCLK_DIVIDER)
#define RA_ICLK_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_ICLK_DIVIDER)
#define RA_PCLKA_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_PCLKA_DIVIDER)
#define RA_PCLKB_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_PCLKB_DIVIDER)
#define RA_PCLKC_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_PCLKC_DIVIDER)
#define RA_PCLKD_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_PCLKD_DIVIDER)
#define RA_PCLKE_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_PCLKE_DIVIDER)
#define RA_FCLK_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_FCLK_DIVIDER)
#define RA_BCLK_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_BCLK_DIVIDER)
/* SCI clock (SCICLK): the clock of the SCI baud rate generator. When no
* SCI UART is enabled it is left at its reset value, the MOCO.
*/
#if RA_USE_SCICLK
# if BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_HOCO
# define RA_SCICLK_SOURCE_FREQUENCY RA_HOCO_FREQUENCY
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_MOSC
# define RA_SCICLK_SOURCE_FREQUENCY RA_MOSC_FREQUENCY
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1P
# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL1P_FREQUENCY
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1Q
# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL1Q_FREQUENCY
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1R
# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL1R_FREQUENCY
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2P
# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL2P_FREQUENCY
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2Q
# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL2Q_FREQUENCY
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2R
# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL2R_FREQUENCY
# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_MOCO
# define RA_SCICLK_SOURCE_FREQUENCY RA_MOCO_FREQUENCY
# else
# error "BOARD_SCICLK_SOURCE is not a valid clock source"
# endif
# define RA_SCICLK_FREQUENCY \
(RA_SCICLK_SOURCE_FREQUENCY / BOARD_SCICLK_DIVIDER)
#else
# define RA_SCICLK_FREQUENCY RA_MOCO_FREQUENCY
#endif
/* Package dependent limit for switching the system clock to the PLL. The
* switch has to happen with CPUCLK at or below this frequency (RA8M1 User's
* Manual figures 8.13-8.15); CPUCLK is then raised by dropping its divider.
* The package is the one of the selected part number (PLBG0224 = 224-pin
* BGA, PLQP0176/0144/0100 = LQFP). The "AM" package does not appear in the
* manual, so it is treated like the most restrictive one.
*/
#if defined(CONFIG_ARCH_CHIP_R7FA8M1AFECBD) || \
defined(CONFIG_ARCH_CHIP_R7FA8M1AHECBD)
# define RA_PLL_SWITCH_MAX_CPUCLK 240000000
#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFC) || \
defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFC) || \
defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFB) || \
defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFB)
# define RA_PLL_SWITCH_MAX_CPUCLK 200000000
#else
# define RA_PLL_SWITCH_MAX_CPUCLK 180000000
#endif
/* Settling time after the system clock is switched to the PLL: 150 us with
* the DCDC converter enabled, 10 us with an external VDD.
*/
#if BOARD_OFS2_DCDC
# define RA_CLOCK_SETTLE_US 150
#else
# define RA_CLOCK_SETTLE_US 10
#endif
/* Flash wait states (FCACHE.FLWT) required for the ICLK frequency */
#if RA_ICLK_FREQUENCY <= 48000000
# define RA_FLASH_WAIT_STATES 0
#elif RA_ICLK_FREQUENCY <= 96000000
# define RA_FLASH_WAIT_STATES 1
#elif RA_ICLK_FREQUENCY <= 144000000
# define RA_FLASH_WAIT_STATES 2
#elif RA_ICLK_FREQUENCY <= 192000000
# define RA_FLASH_WAIT_STATES 3
#else
# define RA_FLASH_WAIT_STATES 4
#endif
/* Divider families: 3, 6 and 12 can not be mixed with 2, 4, 8, 16, 32, 64 */
#define RA_ANY_DIV_A \
(RA_SCKDIV_FAMILY_A(BOARD_CPUCLK_DIVIDER) || \
RA_SCKDIV_FAMILY_A(BOARD_ICLK_DIVIDER) || \
RA_SCKDIV_FAMILY_A(BOARD_PCLKA_DIVIDER) || \
RA_SCKDIV_FAMILY_A(BOARD_PCLKB_DIVIDER) || \
RA_SCKDIV_FAMILY_A(BOARD_PCLKC_DIVIDER) || \
RA_SCKDIV_FAMILY_A(BOARD_PCLKD_DIVIDER) || \
RA_SCKDIV_FAMILY_A(BOARD_PCLKE_DIVIDER) || \
RA_SCKDIV_FAMILY_A(BOARD_FCLK_DIVIDER) || \
RA_SCKDIV_FAMILY_A(BOARD_BCLK_DIVIDER))
#define RA_ANY_DIV_B \
(RA_SCKDIV_FAMILY_B(BOARD_CPUCLK_DIVIDER) || \
RA_SCKDIV_FAMILY_B(BOARD_ICLK_DIVIDER) || \
RA_SCKDIV_FAMILY_B(BOARD_PCLKA_DIVIDER) || \
RA_SCKDIV_FAMILY_B(BOARD_PCLKB_DIVIDER) || \
RA_SCKDIV_FAMILY_B(BOARD_PCLKC_DIVIDER) || \
RA_SCKDIV_FAMILY_B(BOARD_PCLKD_DIVIDER) || \
RA_SCKDIV_FAMILY_B(BOARD_PCLKE_DIVIDER) || \
RA_SCKDIV_FAMILY_B(BOARD_FCLK_DIVIDER) || \
RA_SCKDIV_FAMILY_B(BOARD_BCLK_DIVIDER))
/* CPUCLK divider used while the PLL is first selected as the system clock
* when CPUCLK is above RA_PLL_SWITCH_MAX_CPUCLK: twice (or, in the 3/6/12
* family, three times) slower than the final one.
*/
#if RA_ANY_DIV_B
# define RA_CPUCLK_SWITCH_DIVIDER (BOARD_CPUCLK_DIVIDER * 3)
#else
# define RA_CPUCLK_SWITCH_DIVIDER (BOARD_CPUCLK_DIVIDER * 2)
#endif
/* Checks against RA8M1 User's Manual chapter 8, Table 8.2 and its notes */
#if !RA_SCKDIV_VALID(BOARD_CPUCLK_DIVIDER) || \
!RA_SCKDIV_VALID(BOARD_ICLK_DIVIDER) || \
!RA_SCKDIV_VALID(BOARD_PCLKA_DIVIDER) || \
!RA_SCKDIV_VALID(BOARD_PCLKB_DIVIDER) || \
!RA_SCKDIV_VALID(BOARD_PCLKC_DIVIDER) || \
!RA_SCKDIV_VALID(BOARD_PCLKD_DIVIDER) || \
!RA_SCKDIV_VALID(BOARD_PCLKE_DIVIDER) || \
!RA_SCKDIV_VALID(BOARD_FCLK_DIVIDER) || \
!RA_SCKDIV_VALID(BOARD_BCLK_DIVIDER)
# error "System clock dividers must be 1, 2, 3, 4, 6, 8, 12, 16, 32 or 64"
#endif
#if RA_ANY_DIV_A && RA_ANY_DIV_B
# error "Clock dividers of 3, 6 and 12 can not be mixed with 2, 4, 8, 16, 32 and 64"
#endif
#if RA_CPUCLK_FREQUENCY > 480000000
# error "CPUCLK must be at most 480 MHz"
#endif
#if RA_ICLK_FREQUENCY > 240000000
# error "ICLK must be at most 240 MHz"
#endif
#if RA_PCLKA_FREQUENCY > 120000000
# error "PCLKA must be at most 120 MHz"
#endif
#if RA_PCLKB_FREQUENCY > 60000000
# error "PCLKB must be at most 60 MHz"
#endif
#if RA_PCLKC_FREQUENCY > 60000000
# error "PCLKC must be at most 60 MHz"
#endif
#if RA_PCLKD_FREQUENCY > 120000000
# error "PCLKD must be at most 120 MHz"
#endif
#if RA_PCLKE_FREQUENCY > 240000000
# error "PCLKE must be at most 240 MHz"
#endif
#if RA_FCLK_FREQUENCY > 60000000
# error "FCLK must be at most 60 MHz"
#endif
#if RA_BCLK_FREQUENCY > 120000000
# error "BCLK must be at most 120 MHz"
#endif
/* Frequency ordering and integer ratios: CPUCLK >= ICLK >= PCLKA >= PCLKB,
* ICLK >= FCLK, ICLK >= BCLK, PCLKD >= PCLKA, CPUCLK:ICLK = N:1,
* ICLK:{PCLKA, PCLKB, FCLK, BCLK} = N:1 and ICLK:{PCLKC, PCLKD, PCLKE} =
* N:1 or 1:N.
*/
#if BOARD_ICLK_DIVIDER < BOARD_CPUCLK_DIVIDER || \
(BOARD_ICLK_DIVIDER % BOARD_CPUCLK_DIVIDER) != 0
# error "CPUCLK:ICLK must be an integer ratio with CPUCLK >= ICLK"
#endif
#if BOARD_PCLKA_DIVIDER < BOARD_ICLK_DIVIDER || \
(BOARD_PCLKA_DIVIDER % BOARD_ICLK_DIVIDER) != 0
# error "ICLK:PCLKA must be an integer ratio with ICLK >= PCLKA"
#endif
#if BOARD_PCLKB_DIVIDER < BOARD_PCLKA_DIVIDER
# error "PCLKA must be at least PCLKB"
#endif
#if BOARD_PCLKB_DIVIDER < BOARD_ICLK_DIVIDER || \
(BOARD_PCLKB_DIVIDER % BOARD_ICLK_DIVIDER) != 0
# error "ICLK:PCLKB must be an integer ratio with ICLK >= PCLKB"
#endif
#if BOARD_FCLK_DIVIDER < BOARD_ICLK_DIVIDER || \
(BOARD_FCLK_DIVIDER % BOARD_ICLK_DIVIDER) != 0
# error "ICLK:FCLK must be an integer ratio with ICLK >= FCLK"
#endif
#if BOARD_BCLK_DIVIDER < BOARD_ICLK_DIVIDER || \
(BOARD_BCLK_DIVIDER % BOARD_ICLK_DIVIDER) != 0
# error "ICLK:BCLK must be an integer ratio with ICLK >= BCLK"
#endif
#if BOARD_PCLKD_DIVIDER > BOARD_PCLKA_DIVIDER
# error "PCLKD must be at least PCLKA"
#endif
#if ((BOARD_PCLKC_DIVIDER % BOARD_ICLK_DIVIDER) != 0 && \
(BOARD_ICLK_DIVIDER % BOARD_PCLKC_DIVIDER) != 0) || \
((BOARD_PCLKD_DIVIDER % BOARD_ICLK_DIVIDER) != 0 && \
(BOARD_ICLK_DIVIDER % BOARD_PCLKD_DIVIDER) != 0) || \
((BOARD_PCLKE_DIVIDER % BOARD_ICLK_DIVIDER) != 0 && \
(BOARD_ICLK_DIVIDER % BOARD_PCLKE_DIVIDER) != 0)
# error "ICLK:PCLKC/PCLKD/PCLKE must be an integer ratio (N:1 or 1:N)"
#endif
/* When the HOCO feeds PLL1 the CPU clock is limited to 360 MHz */
#if RA_USE_PLL1 && BOARD_PLL1_SOURCE == R_SYSTEM_PLLCCR_PLSRCSEL && \
RA_CPUCLK_FREQUENCY > 360000000
# error "CPUCLK above 360 MHz needs the main oscillator as the PLL1 source"
#endif
/* Switching to the PLL: CPUCLK has to be at or below the package limit at
* the moment of the switch, and raised afterwards with the divider.
*/
#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_PLL && \
RA_CPUCLK_FREQUENCY > RA_PLL_SWITCH_MAX_CPUCLK
# if BOARD_CPUCLK_DIVIDER != 1
# error "CPUCLK above the PLL switch limit needs a CPUCLK divider of 1"
# endif
# if (RA_SYSCLK_FREQUENCY / RA_CPUCLK_SWITCH_DIVIDER) > \
RA_PLL_SWITCH_MAX_CPUCLK
# error "CPUCLK is more than 2x (3x) the limit for switching to the PLL"
# endif
#endif
#if RA_USE_SCICLK
# if !RA_SCICLK_DIV_VALID(BOARD_SCICLK_DIVIDER)
# error "SCICLK divider must be 1, 2, 3, 4, 5, 6 or 8"
# endif
# if RA_SCICLK_FREQUENCY > 120000000
# error "SCICLK must be at most 120 MHz"
# endif
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: ra_clockconfig
*
* Description:
* Called to initialize the RA8M1. This does whatever setup is needed to
* put the SoC in a usable state. This includes starting the oscillators
* and PLLs, selecting the system clock source, setting the clock
* dividers and configuring the peripheral dedicated clocks, all from the
* BOARD_* clock options in board.h.
*
****************************************************************************/
void ra_clockconfig(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_RA8M1_RA_CLOCKCONFIG_H */

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/****************************************************************************
* arch/arm/src/ra8m1/ra_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <errno.h>
#include <nuttx/debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "ra_gpio.h"
#include "hardware/ra8m1_pinmap.h"
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: ra_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
* cfgset.cfg is written to the pin's PmnPFS register in a single 32-bit
* access: PMR/PSEL/PCR/NCODR/DSCR select the pin's function and drive
* characteristics, while PDR/PODR set its initial direction/output level
* -- PmnPFS.PDR and PmnPFS.PODR are the same physical bits as
* PORTm.PCNTR1's PDR/PODR (RA8M1 User's Manual 19.2.5), so no separate
* PCNTR1 write is needed here.
*
****************************************************************************/
void ra_configgpio(gpio_pinset_t cfgset)
{
uint8_t regval;
regval = R_PFS_PWPR_PFSWE;
putreg8(0, R_PFS_PWPR);
putreg8(regval, R_PFS_PWPR);
putreg32(cfgset.cfg, R_PFS(cfgset.port, cfgset.pin));
regval = R_PFS_PWPR_B0WI;
putreg8(0, R_PFS_PWPR);
putreg8(regval, R_PFS_PWPR);
}
/****************************************************************************
* Name: ra_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void ra_gpiowrite(gpio_pinset_t pinset, bool value)
{
if (value)
{
putreg16((1 << pinset.pin), R_PORT_POSR(pinset.port));
}
else
{
putreg16((1 << pinset.pin), R_PORT_PORR(pinset.port));
}
}
/****************************************************************************
* Name: ra_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool ra_gpioread(gpio_pinset_t pinset)
{
return (getreg16(R_PORT_PIDR(pinset.port)) &
(uint16_t)(0x01 << pinset.pin));
}

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/****************************************************************************
* arch/arm/src/ra8m1/ra_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_RA_GPIO_H
#define __ARCH_ARM_SRC_RA8M1_RA_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/ra8m1_pinmap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Must be big enough to hold the 32-bit encoding */
typedef struct gpio_pinset
{
uint8_t port;
uint8_t pin;
uint32_t cfg;
}gpio_pinset_t;
/****************************************************************************
* Name: ra_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
****************************************************************************/
void ra_configgpio(gpio_pinset_t cfgset);
/****************************************************************************
* Name: ra_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void ra_gpiowrite(gpio_pinset_t pinset, bool value);
/****************************************************************************
* Name: ra_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool ra_gpioread(gpio_pinset_t pinset);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_RA8M1_RA_GPIO_H */

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/****************************************************************************
* arch/arm/src/ra8m1/ra_icu.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
#include "hardware/ra8m1_icu.h"
#include "hardware/ra8m1_elc.h"
#include "ra_icu.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: ra_attach_icu
*
* Description:
* Every ICU IELSR slot is runtime-configurable -- any peripheral event
* can be routed to any slot. This wires each enabled SCI_B channel's
* RXI/TXI/TEI/ERI events into the slots that irq.h assigned them
* (SCIn_RXI/TXI/TEI/ERI), so their vector numbers actually fire.
*
****************************************************************************/
void ra_attach_icu(void)
{
#ifdef CONFIG_RA_SCI0_UART
putreg32(EVENT_SCI0_RXI, R_ICU_IELSR(SCI0_RXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI0_TXI, R_ICU_IELSR(SCI0_TXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI0_TEI, R_ICU_IELSR(SCI0_TEI - RA_IRQ_FIRST));
putreg32(EVENT_SCI0_ERI, R_ICU_IELSR(SCI0_ERI - RA_IRQ_FIRST));
#endif
#ifdef CONFIG_RA_SCI1_UART
putreg32(EVENT_SCI1_RXI, R_ICU_IELSR(SCI1_RXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI1_TXI, R_ICU_IELSR(SCI1_TXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI1_TEI, R_ICU_IELSR(SCI1_TEI - RA_IRQ_FIRST));
putreg32(EVENT_SCI1_ERI, R_ICU_IELSR(SCI1_ERI - RA_IRQ_FIRST));
#endif
#ifdef CONFIG_RA_SCI2_UART
putreg32(EVENT_SCI2_RXI, R_ICU_IELSR(SCI2_RXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI2_TXI, R_ICU_IELSR(SCI2_TXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI2_TEI, R_ICU_IELSR(SCI2_TEI - RA_IRQ_FIRST));
putreg32(EVENT_SCI2_ERI, R_ICU_IELSR(SCI2_ERI - RA_IRQ_FIRST));
#endif
#ifdef CONFIG_RA_SCI3_UART
putreg32(EVENT_SCI3_RXI, R_ICU_IELSR(SCI3_RXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI3_TXI, R_ICU_IELSR(SCI3_TXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI3_TEI, R_ICU_IELSR(SCI3_TEI - RA_IRQ_FIRST));
putreg32(EVENT_SCI3_ERI, R_ICU_IELSR(SCI3_ERI - RA_IRQ_FIRST));
#endif
#ifdef CONFIG_RA_SCI4_UART
putreg32(EVENT_SCI4_RXI, R_ICU_IELSR(SCI4_RXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI4_TXI, R_ICU_IELSR(SCI4_TXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI4_TEI, R_ICU_IELSR(SCI4_TEI - RA_IRQ_FIRST));
putreg32(EVENT_SCI4_ERI, R_ICU_IELSR(SCI4_ERI - RA_IRQ_FIRST));
#endif
#ifdef CONFIG_RA_SCI9_UART
putreg32(EVENT_SCI9_RXI, R_ICU_IELSR(SCI9_RXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI9_TXI, R_ICU_IELSR(SCI9_TXI - RA_IRQ_FIRST));
putreg32(EVENT_SCI9_TEI, R_ICU_IELSR(SCI9_TEI - RA_IRQ_FIRST));
putreg32(EVENT_SCI9_ERI, R_ICU_IELSR(SCI9_ERI - RA_IRQ_FIRST));
#endif
}
/****************************************************************************
* Name: ra_clear_ir
*
* Description:
* Clear the latched interrupt status flag (IELSR.IR) for the ICU slot
* backing the given IRQ number.
*
****************************************************************************/
void ra_clear_ir(int irq)
{
uint32_t slot = irq - RA_IRQ_FIRST;
modifyreg32(R_ICU_IELSR(slot), R_ICU_IELSR_IR, 0);
getreg32(R_ICU_IELSR(slot));
}

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/****************************************************************************
* arch/arm/src/ra8m1/ra_icu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_RA_ICU_H
#define __ARCH_ARM_SRC_RA8M1_RA_ICU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/ra8m1_icu.h"
/****************************************************************************
* Public Data
****************************************************************************/
void ra_attach_icu(void);
void ra_clear_ir(int irq);
#endif

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/****************************************************************************
* arch/arm/src/ra8m1/ra_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv8-m/nvicpri.h>
#include "nvic.h"
#include "arm_internal.h"
#include "ra_icu.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: ra_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
/****************************************************************************
* Name: ra_prioritize_syscall
*
* Description:
* Set the priority of an exception. This function may be needed
* internally even if support for prioritized interrupts is not enabled.
*
****************************************************************************/
static inline void ra_prioritize_syscall(int priority)
{
uint32_t regval;
/* SVCALL is system handler 11 */
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
}
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void ra_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n", getreg32(
NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo(" IRQ ENABLE: %08x %08x %08x\n", getreg32(
NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n", getreg32(
NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", getreg32(
NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(
NVIC_IRQ20_23_PRIORITY), getreg32(
NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(
NVIC_IRQ36_39_PRIORITY), getreg32(
NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(
NVIC_IRQ52_55_PRIORITY), getreg32(
NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x\n", getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
}
#else
# define ra_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: ra_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int ra_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= RA_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= RA_IRQ_FIRST)
{
n = irq - RA_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
*bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == RA_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == RA_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == RA_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == RA_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
uint32_t regaddr;
int num_priority_registers;
int i;
/* Disable all interrupts */
for (i = 0; i < NR_IRQS - RA_IRQ_FIRST; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
putreg32((uint32_t)_vectors, NVIC_VECTAB);
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
/* The NVIC ICTR register (bits 0-4) holds the number of interrupt
* lines that the NVIC supports:
*
* 0 -> 32 interrupt lines, 8 priority registers
* 1 -> 64 " " " ", 16 priority registers
* 2 -> 96 " " " ", 32 priority registers
* ...
*/
num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
/* Now set all of the interrupt lines to the default priority */
regaddr = NVIC_IRQ0_3_PRIORITY;
while (num_priority_registers--)
{
putreg32(DEFPRIORITY32, regaddr);
regaddr += 4;
}
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(RA_IRQ_SVCALL, arm_svcall, NULL);
irq_attach(RA_IRQ_HARDFAULT, arm_hardfault, NULL);
/* Attach the ICU events to the IRQ vector table */
ra_attach_icu();
ra_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
ra_dumpnvic("initial", RA_IRQ_FIRST + 32);
/* And finally, enable interrupts */
up_irq_enable();
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (ra_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to disable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Clear Enable register. For other exceptions, we need to
* clear the bit in the System Handler Control and State Register.
*/
if (irq >= RA_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
}
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (ra_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to enable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Set Enable register. For other exceptions, we need to
* set the bit in the System Handler Control and State Register.
*/
if (irq >= RA_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
}
}
/****************************************************************************
* Name: arm_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void arm_ack_irq(int irq)
{
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(
irq >= RA_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < RA_IRQ_FIRST)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
*/
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= RA_IRQ_FIRST;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
ra_dumpnvic("prioritize", irq);
return OK;
}
#endif

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/****************************************************************************
* arch/arm/src/ra8m1/ra_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdlib.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include "arm_internal.h"
#include "ra_clockconfig.h"
#include "ra_lowputc.h"
#include "ra_gpio.h"
#include "hardware/ra8m1_sci.h"
#include "hardware/ra8m1_mstp.h"
#include "hardware/ra8m1_system.h"
/* The board.h file may redefine pin configurations defined in ra_pinmap.h */
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* RA8M1 only implements SCI_B0-SCI_B4 and SCI_B9 (SCI_B5-8 do not exist). */
/* Is there a serial console? It could be on SCI0-4 or 9 */
#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI0_UART)
#undef CONFIG_SCI1_SERIAL_CONSOLE
#undef CONFIG_SCI2_SERIAL_CONSOLE
#undef CONFIG_SCI3_SERIAL_CONSOLE
#undef CONFIG_SCI4_SERIAL_CONSOLE
#undef CONFIG_SCI9_SERIAL_CONSOLE
#define HAVE_CONSOLE 1
#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI1_UART)
#undef CONFIG_SCI0_SERIAL_CONSOLE
#undef CONFIG_SCI2_SERIAL_CONSOLE
#undef CONFIG_SCI3_SERIAL_CONSOLE
#undef CONFIG_SCI4_SERIAL_CONSOLE
#undef CONFIG_SCI9_SERIAL_CONSOLE
#define HAVE_CONSOLE 1
#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI2_UART)
#undef CONFIG_SCI0_SERIAL_CONSOLE
#undef CONFIG_SCI1_SERIAL_CONSOLE
#undef CONFIG_SCI3_SERIAL_CONSOLE
#undef CONFIG_SCI4_SERIAL_CONSOLE
#undef CONFIG_SCI9_SERIAL_CONSOLE
#define HAVE_CONSOLE 1
#elif defined(CONFIG_SCI3_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI3_UART)
#undef CONFIG_SCI0_SERIAL_CONSOLE
#undef CONFIG_SCI1_SERIAL_CONSOLE
#undef CONFIG_SCI2_SERIAL_CONSOLE
#undef CONFIG_SCI4_SERIAL_CONSOLE
#undef CONFIG_SCI9_SERIAL_CONSOLE
#define HAVE_CONSOLE 1
#elif defined(CONFIG_SCI4_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI4_UART)
#undef CONFIG_SCI0_SERIAL_CONSOLE
#undef CONFIG_SCI1_SERIAL_CONSOLE
#undef CONFIG_SCI2_SERIAL_CONSOLE
#undef CONFIG_SCI3_SERIAL_CONSOLE
#undef CONFIG_SCI9_SERIAL_CONSOLE
#define HAVE_CONSOLE 1
#elif defined(CONFIG_SCI9_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI9_UART)
#undef CONFIG_SCI0_SERIAL_CONSOLE
#undef CONFIG_SCI1_SERIAL_CONSOLE
#undef CONFIG_SCI2_SERIAL_CONSOLE
#undef CONFIG_SCI3_SERIAL_CONSOLE
#undef CONFIG_SCI4_SERIAL_CONSOLE
#define HAVE_CONSOLE 1
#else
#ifndef CONFIG_NO_SERIAL_CONSOLE
#warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting"
#endif
#undef CONFIG_SCI0_SERIAL_CONSOLE
#undef CONFIG_SCI1_SERIAL_CONSOLE
#undef CONFIG_SCI2_SERIAL_CONSOLE
#undef CONFIG_SCI3_SERIAL_CONSOLE
#undef CONFIG_SCI4_SERIAL_CONSOLE
#undef CONFIG_SCI9_SERIAL_CONSOLE
#undef HAVE_CONSOLE
#endif
#if defined(HAVE_CONSOLE)
/* Select SCI_B parameters for the selected console */
# if defined(CONFIG_SCI0_SERIAL_CONSOLE)
# define RA_CONSOLE_BASE R_SCI_B0_BASE
# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB31
# define RA_CONSOLE_BAUD CONFIG_SCI0_BAUD
# define RA_CONSOLE_BITS CONFIG_SCI0_BITS
# define RA_CONSOLE_PARITY CONFIG_SCI0_PARITY
# define RA_CONSOLE_2STOP CONFIG_SCI0_2STOP
# elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
# define RA_CONSOLE_BASE R_SCI_B1_BASE
# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB30
# define RA_CONSOLE_BAUD CONFIG_SCI1_BAUD
# define RA_CONSOLE_BITS CONFIG_SCI1_BITS
# define RA_CONSOLE_PARITY CONFIG_SCI1_PARITY
# define RA_CONSOLE_2STOP CONFIG_SCI1_2STOP
# elif defined(CONFIG_SCI2_SERIAL_CONSOLE)
# define RA_CONSOLE_BASE R_SCI_B2_BASE
# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB29
# define RA_CONSOLE_BAUD CONFIG_SCI2_BAUD
# define RA_CONSOLE_BITS CONFIG_SCI2_BITS
# define RA_CONSOLE_PARITY CONFIG_SCI2_PARITY
# define RA_CONSOLE_2STOP CONFIG_SCI2_2STOP
# elif defined(CONFIG_SCI3_SERIAL_CONSOLE)
# define RA_CONSOLE_BASE R_SCI_B3_BASE
# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB28
# define RA_CONSOLE_BAUD CONFIG_SCI3_BAUD
# define RA_CONSOLE_BITS CONFIG_SCI3_BITS
# define RA_CONSOLE_PARITY CONFIG_SCI3_PARITY
# define RA_CONSOLE_2STOP CONFIG_SCI3_2STOP
# elif defined(CONFIG_SCI4_SERIAL_CONSOLE)
# define RA_CONSOLE_BASE R_SCI_B4_BASE
# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB27
# define RA_CONSOLE_BAUD CONFIG_SCI4_BAUD
# define RA_CONSOLE_BITS CONFIG_SCI4_BITS
# define RA_CONSOLE_PARITY CONFIG_SCI4_PARITY
# define RA_CONSOLE_2STOP CONFIG_SCI4_2STOP
# elif defined(CONFIG_SCI9_SERIAL_CONSOLE)
# define RA_CONSOLE_BASE R_SCI_B9_BASE
# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB22
# define RA_CONSOLE_BAUD CONFIG_SCI9_BAUD
# define RA_CONSOLE_BITS CONFIG_SCI9_BITS
# define RA_CONSOLE_PARITY CONFIG_SCI9_PARITY
# define RA_CONSOLE_2STOP CONFIG_SCI9_2STOP
# else
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
# endif
# endif
/* Configuration ************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef HAVE_CONSOLE
static spinlock_t g_ra_lowputc_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void arm_lowputc(char ch)
{
#ifdef HAVE_CONSOLE
irqstate_t flags;
for (; ; )
{
while ((getreg32(RA_CONSOLE_BASE + R_SCI_B_CSR_OFFSET)
& R_SCI_B_CSR_TEND) == 0)
{
}
/* Disable interrupts so that the test and the transmission are
* atomic.
*/
flags = spin_lock_irqsave(&g_ra_lowputc_lock);
if ((getreg32(RA_CONSOLE_BASE + R_SCI_B_CSR_OFFSET)
& R_SCI_B_CSR_TEND) == R_SCI_B_CSR_TEND)
{
/* Send the character */
putreg32((uint32_t)ch & R_SCI_B_TDR_TDAT_MASK,
RA_CONSOLE_BASE + R_SCI_B_TDR_OFFSET);
spin_unlock_irqrestore(&g_ra_lowputc_lock, flags);
return;
}
spin_unlock_irqrestore(&g_ra_lowputc_lock, flags);
}
#endif
}
/****************************************************************************
* Name: up_putc
*
* Description:
* Provide priority, low-level access to support OS debug writes
*
****************************************************************************/
void up_putc(int ch)
{
#ifdef HAVE_CONSOLE
arm_lowputc(ch);
#endif
}
/****************************************************************************
* Name: ra_sci_baud_ccr2
*
* Description:
* See ra_lowputc.h. Table 31.7 gives, for asynchronous mode,
*
* N = TCLK / (D x 2^(2n-1) x B) - 1
*
* where N is BRR, n is CCR2.CKS (TCLK divided by 1, 4, 16 or 64) and D
* is 64, 32, 16 or 12 depending on BGDM/ABCS/ABCSE. Try every D and n
* and keep the pair with the smallest baud rate error.
*
****************************************************************************/
uint32_t ra_sci_baud_ccr2(uint32_t sciclk_hz, uint32_t baud)
{
static const uint8_t div_baud[4] =
{
12, 16, 32, 64
};
int64_t brr = 0;
uint32_t reg_brr = 0;
uint32_t best_brr = 0;
uint32_t actual_baudrate = 0;
int64_t error = 0;
int64_t min_error = INT64_MAX;
uint8_t best_n = 0;
uint8_t best_i = 0;
uint32_t regval = 0;
for (uint8_t i = 0; i < 4; i++)
{
for (uint8_t n = 0; n < 4; n++)
{
uint32_t div_n = (n == 0) ? 1 : (1U << (2 * n - 1));
uint32_t multiplier = (n == 0) ? 2UL : 1UL;
/* The products below reach several billion (for example 64 x 32
* x 3000000 baud), so they must be 64-bit.
*/
brr = (int64_t)(((uint64_t)sciclk_hz * 100UL * multiplier) /
((uint64_t)div_baud[i] * div_n * baud)) - 100;
/* A negative value means this setting can not reach the requested
* baud rate; use its fastest one (N = 0), which is the closest.
*/
if (brr < 0)
{
brr = 0;
}
reg_brr = (uint32_t)((brr + 50) / 100);
if (reg_brr > 255)
{
continue;
}
actual_baudrate = (sciclk_hz * multiplier) /
(div_baud[i] * div_n * (reg_brr + 1));
/* Error in thousandths of a percent. The baud rate difference
* times 100000 does not fit in 32 bits, so it is 64-bit and
* signed.
*/
error = (((int64_t)actual_baudrate - (int64_t)baud) * 100000) /
(int64_t)baud;
/* Store the best values if we find a new minimum error */
if (llabs(error) < llabs(min_error))
{
min_error = error;
best_n = n;
best_i = i;
best_brr = reg_brr;
}
}
}
switch (best_i)
{
case 0:
regval = R_SCI_B_CCR2_ABCSE;
break;
case 1:
regval = R_SCI_B_CCR2_BGDM | R_SCI_B_CCR2_ABCS;
break;
case 2:
regval = R_SCI_B_CCR2_BGDM;
break;
default:
break;
}
regval |= (best_brr << R_SCI_B_CCR2_BRR_SHIFT);
regval |= ((uint32_t)best_n << R_SCI_B_CCR2_CKS_SHIFT);
return regval;
}
/****************************************************************************
* Name: ra_lowsetup
*
* Description:
* This performs basic initialization of the USART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void ra_lowsetup(void)
{
#ifdef HAVE_CONSOLE
uint32_t regval;
/* Configure only the console's own pins. This must key off which
* channel is the console (CONFIG_SCIn_SERIAL_CONSOLE), not off which
* SCI_B drivers are built in (CONFIG_RA_SCIn_UART): several channels
* may be enabled at once, but ra_lowsetup only ever brings up the one
* that is the console.
*/
#if defined(CONFIG_SCI0_SERIAL_CONSOLE)
ra_configgpio(GPIO_SCI0_RX);
ra_configgpio(GPIO_SCI0_TX);
#elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
ra_configgpio(GPIO_SCI1_RX);
ra_configgpio(GPIO_SCI1_TX);
#elif defined(CONFIG_SCI2_SERIAL_CONSOLE)
ra_configgpio(GPIO_SCI2_RX);
ra_configgpio(GPIO_SCI2_TX);
#elif defined(CONFIG_SCI3_SERIAL_CONSOLE)
ra_configgpio(GPIO_SCI3_RX);
ra_configgpio(GPIO_SCI3_TX);
#elif defined(CONFIG_SCI4_SERIAL_CONSOLE)
ra_configgpio(GPIO_SCI4_RX);
ra_configgpio(GPIO_SCI4_TX);
#elif defined(CONFIG_SCI9_SERIAL_CONSOLE)
ra_configgpio(GPIO_SCI9_RX);
ra_configgpio(GPIO_SCI9_TX);
#endif
putreg16((R_SYSTEM_PRCR_S_PRKEY_V0XA5 | R_SYSTEM_PRCR_S_PRC1),
R_SYSTEM_PRCR_S);
modifyreg32(R_MSTP_MSTPCRB, RA_CONSOLE_MTSP, 0);
putreg16(R_SYSTEM_PRCR_S_PRKEY_V0XA5, R_SYSTEM_PRCR_S);
/* Disable the channel while it is configured */
regval = 0;
putreg32(regval, RA_CONSOLE_BASE + R_SCI_B_CCR0_OFFSET);
/* Baud rate generator: ra_clockconfig() has already set SCICLK, which
* is the baud rate generator's input clock (CCR3.BPEN is 0 after
* reset). Load the console baud rate, with the remaining CCR2 fields
* chosen for the smallest error.
*/
regval = ra_sci_baud_ccr2(RA_SCICLK_FREQUENCY, RA_CONSOLE_BAUD);
putreg32(regval, RA_CONSOLE_BASE + R_SCI_B_CCR2_OFFSET);
regval = (R_SCI_B_CCR0_TE | R_SCI_B_CCR0_RE);
putreg32(regval, RA_CONSOLE_BASE + R_SCI_B_CCR0_OFFSET);
#endif /* HAVE_CONSOLE */
}

109
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/****************************************************************************
* arch/arm/src/ra8m1/ra_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA8M1_RA_LOWPUTC_H
#define __ARCH_ARM_SRC_RA8M1_RA_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: ra_lowsetup
*
* Description:
* Called at the very beginning of _start.
* Performs low level initialization including setup of the console UART.
* This UART done early so that the serial console is available for
* debugging very early in the boot sequence.
*
****************************************************************************/
void ra_lowsetup(void);
/****************************************************************************
* Name: ra_sci_baud_ccr2
*
* Description:
* Find the SCI_B baud rate generator settings closest to the requested
* baud rate for the given SCICLK (the baud rate generator input clock,
* TCLK, when CCR3.BPEN is 0), following RA8M1 User's Manual Table 31.7
* for asynchronous mode.
*
* Input Parameters:
* sciclk_hz - SCICLK frequency, in Hz.
* baud - Requested baud rate.
*
* Returned Value:
* The CCR2 bits to set: BGDM/ABCS/ABCSE, BRR and CKS. All other CCR2
* bits are 0.
*
****************************************************************************/
uint32_t ra_sci_baud_ccr2(uint32_t sciclk_hz, uint32_t baud);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_RA8M1_RA_LOWPUTC_H */

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/****************************************************************************
* arch/arm/src/ra8m1/ra_option_setting.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Option-setting memory images: OFS0, OFS1, OFS2 and OFS1_SEL.
*
* The MCU samples these flash words at reset to decide the watchdog start-up
* state, the voltage detection level, the HOCO, the debug behaviour, ECC and
* the DCDC converter. Each one is a const object in a section of its own;
* the linker script (ek_ra8m1.ld) places the section at the fixed hardware
* address and the flash tool programs it together with the image. The
* values come from the BOARD_OFS* options in the board's board.h.
*
* This is a flat (no TrustZone) image, so only the secure-region registers
* are used. OFS1 is the register at 0x0300_A200 (OFS1_SEC in the manual);
* OFS1_SEL is programmed as 0 so that every OFS1 field is taken from it.
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/board/board.h>
#include "hardware/ra8m1_option_setting.h"
#include "ra_start.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Option values from board.h -> OFS0/OFS1/OFS2 fields. Every value the
* board gives is checked, so an invalid one fails to build.
*
* With auto start off, every field of that watchdog reads as the erased
* (all ones) value: register start mode, and the remaining fields are not
* used, so their BOARD_* options need not be defined.
*/
#ifndef BOARD_OFS0_IWDT_AUTOSTART
# error "board.h must define BOARD_OFS0_IWDT_AUTOSTART"
#endif
#ifndef BOARD_OFS0_WDT_AUTOSTART
# error "board.h must define BOARD_OFS0_WDT_AUTOSTART"
#endif
#if !defined(BOARD_OFS1_VDSEL_MV) || !defined(BOARD_OFS1_LVD0_RESET) || \
!defined(BOARD_OFS1_PVD0_LOWPOWER) || !defined(BOARD_OFS1_HOCO_START) || \
!defined(BOARD_OFS1_SWDBG) || !defined(BOARD_OFS1_INITECC)
# error "board.h must define all the BOARD_OFS1_* options"
#endif
#ifndef BOARD_OFS2_DCDC
# error "board.h must define BOARD_OFS2_DCDC"
#endif
#ifndef BOARD_HOCO_FREQUENCY
# error "board.h must define BOARD_HOCO_FREQUENCY"
#endif
/* OFS0: IWDT */
#define RA_OFS0_IWDT_ALL_ONES \
(R_OFS0_IWDTSTRT | \
(R_OFS0_IWDTTOPS_MASK << R_OFS0_IWDTTOPS_SHIFT) | \
(R_OFS0_IWDTCKS_MASK << R_OFS0_IWDTCKS_SHIFT) | \
(R_OFS0_IWDTRPES_MASK << R_OFS0_IWDTRPES_SHIFT) | \
(R_OFS0_IWDTRPSS_MASK << R_OFS0_IWDTRPSS_SHIFT) | \
R_OFS0_IWDTRSTIRQS | R_OFS0_IWDTSTPCTL)
#if BOARD_OFS0_IWDT_AUTOSTART
# if !defined(BOARD_OFS0_IWDT_TIMEOUT) || !defined(BOARD_OFS0_IWDT_CLKDIV) || \
!defined(BOARD_OFS0_IWDT_WINDOW_END) || \
!defined(BOARD_OFS0_IWDT_WINDOW_START) || \
!defined(BOARD_OFS0_IWDT_RESET) || \
!defined(BOARD_OFS0_IWDT_STOP_IN_SLEEP)
# error "IWDT auto start: board.h must define all the BOARD_OFS0_IWDT_* options"
# endif
# if BOARD_OFS0_IWDT_TIMEOUT == 128
# define RA_OFS0_IWDT_TOPS_VAL R_OFS0_IWDTTOPS_128
# elif BOARD_OFS0_IWDT_TIMEOUT == 512
# define RA_OFS0_IWDT_TOPS_VAL R_OFS0_IWDTTOPS_512
# elif BOARD_OFS0_IWDT_TIMEOUT == 1024
# define RA_OFS0_IWDT_TOPS_VAL R_OFS0_IWDTTOPS_1024
# elif BOARD_OFS0_IWDT_TIMEOUT == 2048
# define RA_OFS0_IWDT_TOPS_VAL R_OFS0_IWDTTOPS_2048
# else
# error "BOARD_OFS0_IWDT_TIMEOUT must be 128, 512, 1024 or 2048"
# endif
# if BOARD_OFS0_IWDT_CLKDIV == 1
# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV1
# elif BOARD_OFS0_IWDT_CLKDIV == 16
# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV16
# elif BOARD_OFS0_IWDT_CLKDIV == 32
# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV32
# elif BOARD_OFS0_IWDT_CLKDIV == 64
# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV64
# elif BOARD_OFS0_IWDT_CLKDIV == 128
# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV128
# elif BOARD_OFS0_IWDT_CLKDIV == 256
# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV256
# else
# error "BOARD_OFS0_IWDT_CLKDIV must be 1, 16, 32, 64, 128 or 256"
# endif
# if BOARD_OFS0_IWDT_WINDOW_END == 75
# define RA_OFS0_IWDT_RPES_VAL R_OFS0_IWDTRPES_75
# elif BOARD_OFS0_IWDT_WINDOW_END == 50
# define RA_OFS0_IWDT_RPES_VAL R_OFS0_IWDTRPES_50
# elif BOARD_OFS0_IWDT_WINDOW_END == 25
# define RA_OFS0_IWDT_RPES_VAL R_OFS0_IWDTRPES_25
# elif BOARD_OFS0_IWDT_WINDOW_END == 0
# define RA_OFS0_IWDT_RPES_VAL R_OFS0_IWDTRPES_0
# else
# error "BOARD_OFS0_IWDT_WINDOW_END must be 75, 50, 25 or 0"
# endif
# if BOARD_OFS0_IWDT_WINDOW_START == 25
# define RA_OFS0_IWDT_RPSS_VAL R_OFS0_IWDTRPSS_25
# elif BOARD_OFS0_IWDT_WINDOW_START == 50
# define RA_OFS0_IWDT_RPSS_VAL R_OFS0_IWDTRPSS_50
# elif BOARD_OFS0_IWDT_WINDOW_START == 75
# define RA_OFS0_IWDT_RPSS_VAL R_OFS0_IWDTRPSS_75
# elif BOARD_OFS0_IWDT_WINDOW_START == 100
# define RA_OFS0_IWDT_RPSS_VAL R_OFS0_IWDTRPSS_100
# else
# error "BOARD_OFS0_IWDT_WINDOW_START must be 25, 50, 75 or 100"
# endif
# if BOARD_OFS0_IWDT_RESET
# define RA_OFS0_IWDT_RESET_BIT R_OFS0_IWDTRSTIRQS
# else
# define RA_OFS0_IWDT_RESET_BIT 0
# endif
# if BOARD_OFS0_IWDT_STOP_IN_SLEEP
# define RA_OFS0_IWDT_STOP_BIT R_OFS0_IWDTSTPCTL
# else
# define RA_OFS0_IWDT_STOP_BIT 0
# endif
# define RA_OFS0_IWDT \
(RA_OFS0_IWDT_TOPS_VAL | RA_OFS0_IWDT_CKS_VAL | \
RA_OFS0_IWDT_RPES_VAL | RA_OFS0_IWDT_RPSS_VAL | \
RA_OFS0_IWDT_RESET_BIT | RA_OFS0_IWDT_STOP_BIT)
#else
# define RA_OFS0_IWDT RA_OFS0_IWDT_ALL_ONES
#endif
/* OFS0: WDT */
#define RA_OFS0_WDT_ALL_ONES \
(R_OFS0_WDT0STRT | \
(R_OFS0_WDT0TOPS_MASK << R_OFS0_WDT0TOPS_SHIFT) | \
(R_OFS0_WDT0CKS_MASK << R_OFS0_WDT0CKS_SHIFT) | \
(R_OFS0_WDT0RPES_MASK << R_OFS0_WDT0RPES_SHIFT) | \
(R_OFS0_WDT0RPSS_MASK << R_OFS0_WDT0RPSS_SHIFT) | \
R_OFS0_WDT0RSTIRQS | R_OFS0_WDT0STPCTL)
#if BOARD_OFS0_WDT_AUTOSTART
# if !defined(BOARD_OFS0_WDT_TIMEOUT) || !defined(BOARD_OFS0_WDT_CLKDIV) || \
!defined(BOARD_OFS0_WDT_WINDOW_END) || \
!defined(BOARD_OFS0_WDT_WINDOW_START) || \
!defined(BOARD_OFS0_WDT_RESET) || \
!defined(BOARD_OFS0_WDT_STOP_IN_SLEEP)
# error "WDT auto start: board.h must define all the BOARD_OFS0_WDT_* options"
# endif
# if BOARD_OFS0_WDT_TIMEOUT == 1024
# define RA_OFS0_WDT_TOPS_VAL R_OFS0_WDT0TOPS_1024
# elif BOARD_OFS0_WDT_TIMEOUT == 4096
# define RA_OFS0_WDT_TOPS_VAL R_OFS0_WDT0TOPS_4096
# elif BOARD_OFS0_WDT_TIMEOUT == 8192
# define RA_OFS0_WDT_TOPS_VAL R_OFS0_WDT0TOPS_8192
# elif BOARD_OFS0_WDT_TIMEOUT == 16384
# define RA_OFS0_WDT_TOPS_VAL R_OFS0_WDT0TOPS_16384
# else
# error "BOARD_OFS0_WDT_TIMEOUT must be 1024, 4096, 8192 or 16384"
# endif
# if BOARD_OFS0_WDT_CLKDIV == 4
# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV4
# elif BOARD_OFS0_WDT_CLKDIV == 64
# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV64
# elif BOARD_OFS0_WDT_CLKDIV == 128
# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV128
# elif BOARD_OFS0_WDT_CLKDIV == 512
# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV512
# elif BOARD_OFS0_WDT_CLKDIV == 2048
# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV2048
# elif BOARD_OFS0_WDT_CLKDIV == 8192
# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV8192
# else
# error "BOARD_OFS0_WDT_CLKDIV must be 4, 64, 128, 512, 2048 or 8192"
# endif
# if BOARD_OFS0_WDT_WINDOW_END == 75
# define RA_OFS0_WDT_RPES_VAL R_OFS0_WDT0RPES_75
# elif BOARD_OFS0_WDT_WINDOW_END == 50
# define RA_OFS0_WDT_RPES_VAL R_OFS0_WDT0RPES_50
# elif BOARD_OFS0_WDT_WINDOW_END == 25
# define RA_OFS0_WDT_RPES_VAL R_OFS0_WDT0RPES_25
# elif BOARD_OFS0_WDT_WINDOW_END == 0
# define RA_OFS0_WDT_RPES_VAL R_OFS0_WDT0RPES_0
# else
# error "BOARD_OFS0_WDT_WINDOW_END must be 75, 50, 25 or 0"
# endif
# if BOARD_OFS0_WDT_WINDOW_START == 25
# define RA_OFS0_WDT_RPSS_VAL R_OFS0_WDT0RPSS_25
# elif BOARD_OFS0_WDT_WINDOW_START == 50
# define RA_OFS0_WDT_RPSS_VAL R_OFS0_WDT0RPSS_50
# elif BOARD_OFS0_WDT_WINDOW_START == 75
# define RA_OFS0_WDT_RPSS_VAL R_OFS0_WDT0RPSS_75
# elif BOARD_OFS0_WDT_WINDOW_START == 100
# define RA_OFS0_WDT_RPSS_VAL R_OFS0_WDT0RPSS_100
# else
# error "BOARD_OFS0_WDT_WINDOW_START must be 25, 50, 75 or 100"
# endif
# if BOARD_OFS0_WDT_RESET
# define RA_OFS0_WDT_RESET_BIT R_OFS0_WDT0RSTIRQS
# else
# define RA_OFS0_WDT_RESET_BIT 0
# endif
# if BOARD_OFS0_WDT_STOP_IN_SLEEP
# define RA_OFS0_WDT_STOP_BIT R_OFS0_WDT0STPCTL
# else
# define RA_OFS0_WDT_STOP_BIT 0
# endif
# define RA_OFS0_WDT \
(RA_OFS0_WDT_TOPS_VAL | RA_OFS0_WDT_CKS_VAL | \
RA_OFS0_WDT_RPES_VAL | RA_OFS0_WDT_RPSS_VAL | \
RA_OFS0_WDT_RESET_BIT | RA_OFS0_WDT_STOP_BIT)
#else
# define RA_OFS0_WDT RA_OFS0_WDT_ALL_ONES
#endif
#define RA_OFS0 (R_OFS0_RESERVED | RA_OFS0_IWDT | RA_OFS0_WDT)
/* OFS1. PVDAS, PVDLPSEL, HOCOEN and SWDBG are active low: the bit is set
* when the feature is off.
*/
#if BOARD_OFS1_VDSEL_MV == 2850
# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_2_85V
#elif BOARD_OFS1_VDSEL_MV == 2580
# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_2_58V
#elif BOARD_OFS1_VDSEL_MV == 2150
# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_2_15V
#elif BOARD_OFS1_VDSEL_MV == 2000
# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_2_00V
#elif BOARD_OFS1_VDSEL_MV == 1900
# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_1_90V
#elif BOARD_OFS1_VDSEL_MV == 1800
# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_1_80V
#elif BOARD_OFS1_VDSEL_MV == 1700
# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_1_70V
#elif BOARD_OFS1_VDSEL_MV == 1600
# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_1_60V
#else
# error "BOARD_OFS1_VDSEL_MV must be 2850, 2580, 2150, 2000, 1900, 1800, 1700 or 1600"
#endif
/* The HOCO frequency after reset is the same BOARD_HOCO_FREQUENCY that
* ra_clockconfig.h uses as the HOCO frequency.
*/
#if BOARD_HOCO_FREQUENCY == 16000000
# define RA_OFS1_HOCOFRQ_VAL R_OFS1_HOCOFRQ0_16MHZ
#elif BOARD_HOCO_FREQUENCY == 18000000
# define RA_OFS1_HOCOFRQ_VAL R_OFS1_HOCOFRQ0_18MHZ
#elif BOARD_HOCO_FREQUENCY == 20000000
# define RA_OFS1_HOCOFRQ_VAL R_OFS1_HOCOFRQ0_20MHZ
#elif BOARD_HOCO_FREQUENCY == 32000000
# define RA_OFS1_HOCOFRQ_VAL R_OFS1_HOCOFRQ0_32MHZ
#elif BOARD_HOCO_FREQUENCY == 48000000
# define RA_OFS1_HOCOFRQ_VAL R_OFS1_HOCOFRQ0_48MHZ
#else
# error "BOARD_HOCO_FREQUENCY must be 16, 18, 20, 32 or 48 MHz"
#endif
#if BOARD_OFS1_LVD0_RESET
# define RA_OFS1_PVDAS_BIT 0
#else
# define RA_OFS1_PVDAS_BIT R_OFS1_PVDAS
#endif
#if BOARD_OFS1_PVD0_LOWPOWER
# define RA_OFS1_PVDLPSEL_BIT 0
#else
# define RA_OFS1_PVDLPSEL_BIT R_OFS1_PVDLPSEL
#endif
#if BOARD_OFS1_HOCO_START
# define RA_OFS1_HOCOEN_BIT 0
#else
# define RA_OFS1_HOCOEN_BIT R_OFS1_HOCOEN
#endif
#if BOARD_OFS1_SWDBG
# define RA_OFS1_SWDBG_BIT 0
#else
# define RA_OFS1_SWDBG_BIT R_OFS1_SWDBG
#endif
#if BOARD_OFS1_INITECC
# define RA_OFS1_INITECCEN_BIT R_OFS1_INITECCEN
#else
# define RA_OFS1_INITECCEN_BIT 0
#endif
#define RA_OFS1 \
(R_OFS1_RESERVED | RA_OFS1_VDSEL_VAL | RA_OFS1_PVDAS_BIT | \
RA_OFS1_PVDLPSEL_BIT | RA_OFS1_HOCOEN_BIT | RA_OFS1_HOCOFRQ_VAL | \
RA_OFS1_SWDBG_BIT | RA_OFS1_INITECCEN_BIT)
/* OFS2 */
#if BOARD_OFS2_DCDC
# define RA_OFS2 (R_OFS2_RESERVED | R_OFS2_DCDCEN)
#else
# define RA_OFS2 R_OFS2_RESERVED
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* "used" and the KEEP() in the linker script keep the sections themselves.
* The objects have external linkage and ra_start.c references them, because
* nothing else refers to this file and the linker would otherwise not pull
* it out of the library at all.
*/
const uint32_t g_ra_option_setting_ofs0
__attribute__((section(".option_setting_ofs0"), used)) = RA_OFS0;
const uint32_t g_ra_option_setting_ofs2
__attribute__((section(".option_setting_ofs2"), used)) = RA_OFS2;
const uint32_t g_ra_option_setting_ofs1
__attribute__((section(".option_setting_ofs1"), used)) = RA_OFS1;
const uint32_t g_ra_option_setting_ofs1_sel
__attribute__((section(".option_setting_ofs1_sel"), used)) =
R_OFS1_SEL_ALL_SECURE;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/ra8m1/ra_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/debug.h>
#include <nuttx/init.h>
#include "arch/board/board.h"
#include "arm_internal.h"
#include "nvic.h"
#include "ra_clockconfig.h"
#include "ra_lowputc.h"
#include "ra_start.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define HEAP_BASE ((uint32_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE)
/****************************************************************************
* Private Data
****************************************************************************/
/* Nothing calls into ra_option_setting.c, so without a reference the linker
* would leave it out of the library and the option-setting words (OFS0,
* OFS1, OFS2, OFS1_SEL) would not be in the image. This table only exists
* to reference them; it is not used at run time.
*/
static const uint32_t * const g_ra_option_setting_refs[]
__attribute__((used)) =
{
&g_ra_option_setting_ofs0,
&g_ra_option_setting_ofs2,
&g_ra_option_setting_ofs1,
&g_ra_option_setting_ofs1_sel
};
/****************************************************************************
* Public Data
****************************************************************************/
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the CONSOLE USART to show boot status.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) arm_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: __start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
void __start(void)
{
const uint32_t *src;
uint32_t *dest;
/* Configure the uart so that we can get debug output as soon as possible */
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; )
{
*dest++ = 0;
}
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = (const uint32_t *)_eronly, dest = (uint32_t *)_sdata;
dest < (uint32_t *)_edata;
)
{
*dest++ = *src++;
}
ra_clockconfig();
arm_fpuconfig();
ra_lowsetup();
showprogress('A');
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
arm_earlyserialinit();
#endif
showprogress('B');
/* Initialize onboard resources */
ra_boardinitialize();
showprogress('C');
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
nx_start();
/* Shouldn't get here */
for (; ; )
{
}
}

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/****************************************************************************
* arch/arm/src/ra8m1/ra_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RA_START_H
#define __ARCH_ARM_SRC_RA_START_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Public Data
****************************************************************************/
/* Option-setting memory words (ra_option_setting.c) */
extern const uint32_t g_ra_option_setting_ofs0;
extern const uint32_t g_ra_option_setting_ofs2;
extern const uint32_t g_ra_option_setting_ofs1;
extern const uint32_t g_ra_option_setting_ofs1_sel;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void ra_boardinitialize(void);
#endif /* __ARCH_ARM_SRC_RA_START_H */

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/****************************************************************************
* arch/arm/src/ra8m1/ra_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <nuttx/debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "arm_internal.h"
#include "chip.h"
#include "ra_clockconfig.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SysTick is clocked from the processor clock (CLKSOURCE is set below),
* which is CPUCLK: on RA8M1 that is not ICLK.
*/
#define SYSTICK_CLOCK (RA_CPUCLK_FREQUENCY)
#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1)
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
#define SYSTICK_MAX 0x00ffffff
#if SYSTICK_RELOAD > SYSTICK_MAX
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: ra_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
#if !defined(CONFIG_ARMV8M_SYSTICK) && !defined(CONFIG_TIMER_ARCH)
static int ra_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t regval;
/* Set the SysTick interrupt to the default priority */
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Make sure that the SYSTICK clock source is set correctly */
#if defined(CONFIG_ARMV8M_SYSTICK) && defined(CONFIG_TIMER_ARCH)
up_timer_set_lowerhalf(systick_initialize(true, SYSTICK_CLOCK, -1));
#else
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
/* Attach the timer interrupt vector */
irq_attach(RA_IRQ_SYSTICK, (xcpt_t)ra_timerisr, NULL);
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */
up_enable_irq(RA_IRQ_SYSTICK);
#endif
}