From 1515b3fafd97dc63ba2b568b4788cef9ef044248 Mon Sep 17 00:00:00 2001 From: leocafonso Date: Fri, 25 Sep 2026 11:08:56 -0700 Subject: [PATCH] arch/arm/ra8m1: Add Renesas RA8M1 chip support Add initial architecture support for the Renesas RA8M1 (Cortex-M85) family: clock configuration, GPIO, ICU/IRQ handling, SCI serial, system timer, option setting and start-up code, plus the Kconfig and build system integration. Co-Authored-By: Claude Sonnet 5 Signed-off-by: leocafonso --- arch/arm/Kconfig | 11 + arch/arm/include/ra8m1/chip.h | 235 ++ arch/arm/include/ra8m1/irq.h | 103 + arch/arm/include/ra8m1/ra8m1_irq.h | 222 ++ arch/arm/src/cmake/armv8-m.cmake | 10 + arch/arm/src/cmake/platform.cmake | 2 + arch/arm/src/ra8m1/CMakeLists.txt | 33 + arch/arm/src/ra8m1/Kconfig | 186 ++ arch/arm/src/ra8m1/Make.defs | 38 + arch/arm/src/ra8m1/chip.h | 59 + arch/arm/src/ra8m1/hardware/ra8m1_elc.h | 367 +++ arch/arm/src/ra8m1/hardware/ra8m1_fcache.h | 94 + arch/arm/src/ra8m1/hardware/ra8m1_gpio.h | 324 +++ arch/arm/src/ra8m1/hardware/ra8m1_icu.h | 218 ++ arch/arm/src/ra8m1/hardware/ra8m1_memorymap.h | 208 ++ arch/arm/src/ra8m1/hardware/ra8m1_mstp.h | 146 ++ .../src/ra8m1/hardware/ra8m1_option_setting.h | 175 ++ arch/arm/src/ra8m1/hardware/ra8m1_pinmap.h | 274 +++ arch/arm/src/ra8m1/hardware/ra8m1_sci.h | 1989 +++++++++++++++++ arch/arm/src/ra8m1/hardware/ra8m1_system.h | 1635 ++++++++++++++ arch/arm/src/ra8m1/ra_allocateheap.c | 98 + arch/arm/src/ra8m1/ra_clockconfig.c | 495 ++++ arch/arm/src/ra8m1/ra_clockconfig.h | 656 ++++++ arch/arm/src/ra8m1/ra_gpio.c | 115 + arch/arm/src/ra8m1/ra_gpio.h | 100 + arch/arm/src/ra8m1/ra_icu.c | 106 + arch/arm/src/ra8m1/ra_icu.h | 37 + arch/arm/src/ra8m1/ra_irq.c | 387 ++++ arch/arm/src/ra8m1/ra_lowputc.c | 419 ++++ arch/arm/src/ra8m1/ra_lowputc.h | 109 + arch/arm/src/ra8m1/ra_option_setting.c | 372 +++ arch/arm/src/ra8m1/ra_serial.c | 1200 ++++++++++ arch/arm/src/ra8m1/ra_start.c | 158 ++ arch/arm/src/ra8m1/ra_start.h | 49 + arch/arm/src/ra8m1/ra_timerisr.c | 130 ++ 35 files changed, 10760 insertions(+) create mode 100644 arch/arm/include/ra8m1/chip.h create mode 100644 arch/arm/include/ra8m1/irq.h create mode 100644 arch/arm/include/ra8m1/ra8m1_irq.h create mode 100644 arch/arm/src/ra8m1/CMakeLists.txt create mode 100644 arch/arm/src/ra8m1/Kconfig create mode 100644 arch/arm/src/ra8m1/Make.defs create mode 100644 arch/arm/src/ra8m1/chip.h create mode 100644 arch/arm/src/ra8m1/hardware/ra8m1_elc.h create mode 100644 arch/arm/src/ra8m1/hardware/ra8m1_fcache.h create mode 100644 arch/arm/src/ra8m1/hardware/ra8m1_gpio.h create mode 100644 arch/arm/src/ra8m1/hardware/ra8m1_icu.h create mode 100644 arch/arm/src/ra8m1/hardware/ra8m1_memorymap.h create mode 100644 arch/arm/src/ra8m1/hardware/ra8m1_mstp.h create mode 100644 arch/arm/src/ra8m1/hardware/ra8m1_option_setting.h create mode 100644 arch/arm/src/ra8m1/hardware/ra8m1_pinmap.h create mode 100644 arch/arm/src/ra8m1/hardware/ra8m1_sci.h create mode 100644 arch/arm/src/ra8m1/hardware/ra8m1_system.h create mode 100644 arch/arm/src/ra8m1/ra_allocateheap.c create mode 100644 arch/arm/src/ra8m1/ra_clockconfig.c create mode 100644 arch/arm/src/ra8m1/ra_clockconfig.h create mode 100644 arch/arm/src/ra8m1/ra_gpio.c create mode 100644 arch/arm/src/ra8m1/ra_gpio.h create mode 100644 arch/arm/src/ra8m1/ra_icu.c create mode 100644 arch/arm/src/ra8m1/ra_icu.h create mode 100644 arch/arm/src/ra8m1/ra_irq.c create mode 100644 arch/arm/src/ra8m1/ra_lowputc.c create mode 100644 arch/arm/src/ra8m1/ra_lowputc.h create mode 100644 arch/arm/src/ra8m1/ra_option_setting.c create mode 100644 arch/arm/src/ra8m1/ra_serial.c create mode 100644 arch/arm/src/ra8m1/ra_start.c create mode 100644 arch/arm/src/ra8m1/ra_start.h create mode 100644 arch/arm/src/ra8m1/ra_timerisr.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e6dabd07e9f..080486cf963 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -382,6 +382,13 @@ config ARCH_CHIP_RA4 ---help--- Renesas RA4 Architecture (ARM Cortex-M4F/M33). +config ARCH_CHIP_RA8M1 + bool "Renesas RA8M1" + select ARCH_CORTEXM85 + select ARCH_HAVE_FPU + ---help--- + Renesas RA8M1 Family (ARM Cortex-M85). + config ARCH_CHIP_RP2040 bool "Raspberry Pi RP2040" select ARCH_CORTEXM0 @@ -1358,6 +1365,7 @@ config ARCH_CHIP default "nrf91" if ARCH_CHIP_NRF91 default "nuc1xx" if ARCH_CHIP_NUC1XX default "ra4" if ARCH_CHIP_RA4 + default "ra8m1" if ARCH_CHIP_RA8M1 default "rp2040" if ARCH_CHIP_RP2040 default "rp23xx" if ARCH_CHIP_RP23XX default "s32k1xx" if ARCH_CHIP_S32K1XX @@ -1869,6 +1877,9 @@ endif if ARCH_CHIP_RA4 source "arch/arm/src/ra4/Kconfig" endif +if ARCH_CHIP_RA8M1 +source "arch/arm/src/ra8m1/Kconfig" +endif if ARCH_CHIP_RP2040 source "arch/arm/src/rp2040/Kconfig" endif diff --git a/arch/arm/include/ra8m1/chip.h b/arch/arm/include/ra8m1/chip.h new file mode 100644 index 00000000000..d22b7384094 --- /dev/null +++ b/arch/arm/include/ra8m1/chip.h @@ -0,0 +1,235 @@ +/**************************************************************************** + * arch/arm/include/ra8m1/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_RA8M1_CHIP_H +#define __ARCH_ARM_INCLUDE_RA8M1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_R7FA8M1AFECAM) +# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */ + +# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */ +# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */ +# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */ +# if defined(CONFIG_ARMV8M_HAVE_ITCM) +# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */ +# else +# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */ +# endif +# if defined(CONFIG_ARMV8M_HAVE_DTCM) +# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */ +# else +# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */ +# endif + +#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECBD) +# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */ + +# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */ +# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */ +# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */ +# if defined(CONFIG_ARMV8M_HAVE_ITCM) +# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */ +# else +# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */ +# endif +# if defined(CONFIG_ARMV8M_HAVE_DTCM) +# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */ +# else +# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */ +# endif + +#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFB) +# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */ + +# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */ +# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */ +# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */ +# if defined(CONFIG_ARMV8M_HAVE_ITCM) +# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */ +# else +# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */ +# endif +# if defined(CONFIG_ARMV8M_HAVE_DTCM) +# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */ +# else +# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */ +# endif + +#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFC) +# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */ + +# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */ +# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */ +# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */ +# if defined(CONFIG_ARMV8M_HAVE_ITCM) +# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */ +# else +# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */ +# endif +# if defined(CONFIG_ARMV8M_HAVE_DTCM) +# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */ +# else +# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */ +# endif + +#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFP) +# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */ + +# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */ +# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */ +# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */ +# if defined(CONFIG_ARMV8M_HAVE_ITCM) +# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */ +# else +# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */ +# endif +# if defined(CONFIG_ARMV8M_HAVE_DTCM) +# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */ +# else +# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */ +# endif + +#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECAM) +# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */ + +# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */ +# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */ +# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */ +# if defined(CONFIG_ARMV8M_HAVE_ITCM) +# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */ +# else +# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */ +# endif +# if defined(CONFIG_ARMV8M_HAVE_DTCM) +# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */ +# else +# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */ +# endif + +#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECBD) +# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */ + +# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */ +# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */ +# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */ +# if defined(CONFIG_ARMV8M_HAVE_ITCM) +# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */ +# else +# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */ +# endif +# if defined(CONFIG_ARMV8M_HAVE_DTCM) +# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */ +# else +# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */ +# endif + +#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFB) +# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */ + +# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */ +# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */ +# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */ +# if defined(CONFIG_ARMV8M_HAVE_ITCM) +# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */ +# else +# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */ +# endif +# if defined(CONFIG_ARMV8M_HAVE_DTCM) +# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */ +# else +# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */ +# endif + +#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFC) +# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */ + +# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */ +# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */ +# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */ +# if defined(CONFIG_ARMV8M_HAVE_ITCM) +# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */ +# else +# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */ +# endif +# if defined(CONFIG_ARMV8M_HAVE_DTCM) +# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */ +# else +# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */ +# endif + +#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFP) +# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */ + +# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */ +# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */ +# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */ +# if defined(CONFIG_ARMV8M_HAVE_ITCM) +# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */ +# else +# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */ +# endif +# if defined(CONFIG_ARMV8M_HAVE_DTCM) +# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */ +# else +# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */ +# endif + +#else +# error "Unsupported RA8M1 chip" +#endif + +/* NVIC Priority Levels *****************************************************/ + +/* Each priority field holds a priority value, 0-15. The lower + * the value, the greater the priority of the corresponding + * interrupt. The processor implements only bits[7:4] of each + * field, bits[3:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_RA8M1_CHIP_H */ diff --git a/arch/arm/include/ra8m1/irq.h b/arch/arm/include/ra8m1/irq.h new file mode 100644 index 00000000000..e400e65339d --- /dev/null +++ b/arch/arm/include/ra8m1/irq.h @@ -0,0 +1,103 @@ +/**************************************************************************** + * arch/arm/include/ra8m1/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_RA8M1_IRQ_H +#define __ARCH_ARM_INCLUDE_RA8M1_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#if defined(CONFIG_RA8M1_FAMILY) +# include +#else +# error Unrecognized RA architecture +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Common Processor Exceptions (vectors 0-15) */ + +#define RA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define RA_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define RA_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define RA_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define RA_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define RA_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define RA_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define RA_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define RA_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define RA_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* Chip-Specific External interrupts */ + +#define RA_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +#define NR_IRQS (RA_IRQ_FIRST + RA_IRQ_NEXTINT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_INCLUDE_RA8M1_IRQ_H */ diff --git a/arch/arm/include/ra8m1/ra8m1_irq.h b/arch/arm/include/ra8m1/ra8m1_irq.h new file mode 100644 index 00000000000..c50fb06ff50 --- /dev/null +++ b/arch/arm/include/ra8m1/ra8m1_irq.h @@ -0,0 +1,222 @@ +/**************************************************************************** + * arch/arm/include/ra8m1/ra8m1_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_RA8M1_RA8M1_IRQ_H +#define __ARCH_ARM_INCLUDE_RA8M1_RA8M1_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Total number of IRQ numbers. + * + * Every ICU IELSR slot is runtime-configurable -- any peripheral event + * can be routed to any slot -- so RA_IRQ_IELSRn below are just the raw + * vector numbers; RA_IRQ_NEXTINT is the total slot count. Both come + * directly from this chip's .rzone . + */ + +#define RA_IRQ_IELSR0 (RA_IRQ_FIRST + 0) /* 0: Event selected in the ICU.IELSR0 register */ +#define RA_IRQ_IELSR1 (RA_IRQ_FIRST + 1) /* 1: Event selected in the ICU.IELSR1 register */ +#define RA_IRQ_IELSR2 (RA_IRQ_FIRST + 2) /* 2: Event selected in the ICU.IELSR2 register */ +#define RA_IRQ_IELSR3 (RA_IRQ_FIRST + 3) /* 3: Event selected in the ICU.IELSR3 register */ +#define RA_IRQ_IELSR4 (RA_IRQ_FIRST + 4) /* 4: Event selected in the ICU.IELSR4 register */ +#define RA_IRQ_IELSR5 (RA_IRQ_FIRST + 5) /* 5: Event selected in the ICU.IELSR5 register */ +#define RA_IRQ_IELSR6 (RA_IRQ_FIRST + 6) /* 6: Event selected in the ICU.IELSR6 register */ +#define RA_IRQ_IELSR7 (RA_IRQ_FIRST + 7) /* 7: Event selected in the ICU.IELSR7 register */ +#define RA_IRQ_IELSR8 (RA_IRQ_FIRST + 8) /* 8: Event selected in the ICU.IELSR8 register */ +#define RA_IRQ_IELSR9 (RA_IRQ_FIRST + 9) /* 9: Event selected in the ICU.IELSR9 register */ +#define RA_IRQ_IELSR10 (RA_IRQ_FIRST + 10) /* 10: Event selected in the ICU.IELSR10 register */ +#define RA_IRQ_IELSR11 (RA_IRQ_FIRST + 11) /* 11: Event selected in the ICU.IELSR11 register */ +#define RA_IRQ_IELSR12 (RA_IRQ_FIRST + 12) /* 12: Event selected in the ICU.IELSR12 register */ +#define RA_IRQ_IELSR13 (RA_IRQ_FIRST + 13) /* 13: Event selected in the ICU.IELSR13 register */ +#define RA_IRQ_IELSR14 (RA_IRQ_FIRST + 14) /* 14: Event selected in the ICU.IELSR14 register */ +#define RA_IRQ_IELSR15 (RA_IRQ_FIRST + 15) /* 15: Event selected in the ICU.IELSR15 register */ +#define RA_IRQ_IELSR16 (RA_IRQ_FIRST + 16) /* 16: Event selected in the ICU.IELSR16 register */ +#define RA_IRQ_IELSR17 (RA_IRQ_FIRST + 17) /* 17: Event selected in the ICU.IELSR17 register */ +#define RA_IRQ_IELSR18 (RA_IRQ_FIRST + 18) /* 18: Event selected in the ICU.IELSR18 register */ +#define RA_IRQ_IELSR19 (RA_IRQ_FIRST + 19) /* 19: Event selected in the ICU.IELSR19 register */ +#define RA_IRQ_IELSR20 (RA_IRQ_FIRST + 20) /* 20: Event selected in the ICU.IELSR20 register */ +#define RA_IRQ_IELSR21 (RA_IRQ_FIRST + 21) /* 21: Event selected in the ICU.IELSR21 register */ +#define RA_IRQ_IELSR22 (RA_IRQ_FIRST + 22) /* 22: Event selected in the ICU.IELSR22 register */ +#define RA_IRQ_IELSR23 (RA_IRQ_FIRST + 23) /* 23: Event selected in the ICU.IELSR23 register */ +#define RA_IRQ_IELSR24 (RA_IRQ_FIRST + 24) /* 24: Event selected in the ICU.IELSR24 register */ +#define RA_IRQ_IELSR25 (RA_IRQ_FIRST + 25) /* 25: Event selected in the ICU.IELSR25 register */ +#define RA_IRQ_IELSR26 (RA_IRQ_FIRST + 26) /* 26: Event selected in the ICU.IELSR26 register */ +#define RA_IRQ_IELSR27 (RA_IRQ_FIRST + 27) /* 27: Event selected in the ICU.IELSR27 register */ +#define RA_IRQ_IELSR28 (RA_IRQ_FIRST + 28) /* 28: Event selected in the ICU.IELSR28 register */ +#define RA_IRQ_IELSR29 (RA_IRQ_FIRST + 29) /* 29: Event selected in the ICU.IELSR29 register */ +#define RA_IRQ_IELSR30 (RA_IRQ_FIRST + 30) /* 30: Event selected in the ICU.IELSR30 register */ +#define RA_IRQ_IELSR31 (RA_IRQ_FIRST + 31) /* 31: Event selected in the ICU.IELSR31 register */ +#define RA_IRQ_IELSR32 (RA_IRQ_FIRST + 32) /* 32: Event selected in the ICU.IELSR32 register */ +#define RA_IRQ_IELSR33 (RA_IRQ_FIRST + 33) /* 33: Event selected in the ICU.IELSR33 register */ +#define RA_IRQ_IELSR34 (RA_IRQ_FIRST + 34) /* 34: Event selected in the ICU.IELSR34 register */ +#define RA_IRQ_IELSR35 (RA_IRQ_FIRST + 35) /* 35: Event selected in the ICU.IELSR35 register */ +#define RA_IRQ_IELSR36 (RA_IRQ_FIRST + 36) /* 36: Event selected in the ICU.IELSR36 register */ +#define RA_IRQ_IELSR37 (RA_IRQ_FIRST + 37) /* 37: Event selected in the ICU.IELSR37 register */ +#define RA_IRQ_IELSR38 (RA_IRQ_FIRST + 38) /* 38: Event selected in the ICU.IELSR38 register */ +#define RA_IRQ_IELSR39 (RA_IRQ_FIRST + 39) /* 39: Event selected in the ICU.IELSR39 register */ +#define RA_IRQ_IELSR40 (RA_IRQ_FIRST + 40) /* 40: Event selected in the ICU.IELSR40 register */ +#define RA_IRQ_IELSR41 (RA_IRQ_FIRST + 41) /* 41: Event selected in the ICU.IELSR41 register */ +#define RA_IRQ_IELSR42 (RA_IRQ_FIRST + 42) /* 42: Event selected in the ICU.IELSR42 register */ +#define RA_IRQ_IELSR43 (RA_IRQ_FIRST + 43) /* 43: Event selected in the ICU.IELSR43 register */ +#define RA_IRQ_IELSR44 (RA_IRQ_FIRST + 44) /* 44: Event selected in the ICU.IELSR44 register */ +#define RA_IRQ_IELSR45 (RA_IRQ_FIRST + 45) /* 45: Event selected in the ICU.IELSR45 register */ +#define RA_IRQ_IELSR46 (RA_IRQ_FIRST + 46) /* 46: Event selected in the ICU.IELSR46 register */ +#define RA_IRQ_IELSR47 (RA_IRQ_FIRST + 47) /* 47: Event selected in the ICU.IELSR47 register */ +#define RA_IRQ_IELSR48 (RA_IRQ_FIRST + 48) /* 48: Event selected in the ICU.IELSR48 register */ +#define RA_IRQ_IELSR49 (RA_IRQ_FIRST + 49) /* 49: Event selected in the ICU.IELSR49 register */ +#define RA_IRQ_IELSR50 (RA_IRQ_FIRST + 50) /* 50: Event selected in the ICU.IELSR50 register */ +#define RA_IRQ_IELSR51 (RA_IRQ_FIRST + 51) /* 51: Event selected in the ICU.IELSR51 register */ +#define RA_IRQ_IELSR52 (RA_IRQ_FIRST + 52) /* 52: Event selected in the ICU.IELSR52 register */ +#define RA_IRQ_IELSR53 (RA_IRQ_FIRST + 53) /* 53: Event selected in the ICU.IELSR53 register */ +#define RA_IRQ_IELSR54 (RA_IRQ_FIRST + 54) /* 54: Event selected in the ICU.IELSR54 register */ +#define RA_IRQ_IELSR55 (RA_IRQ_FIRST + 55) /* 55: Event selected in the ICU.IELSR55 register */ +#define RA_IRQ_IELSR56 (RA_IRQ_FIRST + 56) /* 56: Event selected in the ICU.IELSR56 register */ +#define RA_IRQ_IELSR57 (RA_IRQ_FIRST + 57) /* 57: Event selected in the ICU.IELSR57 register */ +#define RA_IRQ_IELSR58 (RA_IRQ_FIRST + 58) /* 58: Event selected in the ICU.IELSR58 register */ +#define RA_IRQ_IELSR59 (RA_IRQ_FIRST + 59) /* 59: Event selected in the ICU.IELSR59 register */ +#define RA_IRQ_IELSR60 (RA_IRQ_FIRST + 60) /* 60: Event selected in the ICU.IELSR60 register */ +#define RA_IRQ_IELSR61 (RA_IRQ_FIRST + 61) /* 61: Event selected in the ICU.IELSR61 register */ +#define RA_IRQ_IELSR62 (RA_IRQ_FIRST + 62) /* 62: Event selected in the ICU.IELSR62 register */ +#define RA_IRQ_IELSR63 (RA_IRQ_FIRST + 63) /* 63: Event selected in the ICU.IELSR63 register */ +#define RA_IRQ_IELSR64 (RA_IRQ_FIRST + 64) /* 64: Event selected in the ICU.IELSR64 register */ +#define RA_IRQ_IELSR65 (RA_IRQ_FIRST + 65) /* 65: Event selected in the ICU.IELSR65 register */ +#define RA_IRQ_IELSR66 (RA_IRQ_FIRST + 66) /* 66: Event selected in the ICU.IELSR66 register */ +#define RA_IRQ_IELSR67 (RA_IRQ_FIRST + 67) /* 67: Event selected in the ICU.IELSR67 register */ +#define RA_IRQ_IELSR68 (RA_IRQ_FIRST + 68) /* 68: Event selected in the ICU.IELSR68 register */ +#define RA_IRQ_IELSR69 (RA_IRQ_FIRST + 69) /* 69: Event selected in the ICU.IELSR69 register */ +#define RA_IRQ_IELSR70 (RA_IRQ_FIRST + 70) /* 70: Event selected in the ICU.IELSR70 register */ +#define RA_IRQ_IELSR71 (RA_IRQ_FIRST + 71) /* 71: Event selected in the ICU.IELSR71 register */ +#define RA_IRQ_IELSR72 (RA_IRQ_FIRST + 72) /* 72: Event selected in the ICU.IELSR72 register */ +#define RA_IRQ_IELSR73 (RA_IRQ_FIRST + 73) /* 73: Event selected in the ICU.IELSR73 register */ +#define RA_IRQ_IELSR74 (RA_IRQ_FIRST + 74) /* 74: Event selected in the ICU.IELSR74 register */ +#define RA_IRQ_IELSR75 (RA_IRQ_FIRST + 75) /* 75: Event selected in the ICU.IELSR75 register */ +#define RA_IRQ_IELSR76 (RA_IRQ_FIRST + 76) /* 76: Event selected in the ICU.IELSR76 register */ +#define RA_IRQ_IELSR77 (RA_IRQ_FIRST + 77) /* 77: Event selected in the ICU.IELSR77 register */ +#define RA_IRQ_IELSR78 (RA_IRQ_FIRST + 78) /* 78: Event selected in the ICU.IELSR78 register */ +#define RA_IRQ_IELSR79 (RA_IRQ_FIRST + 79) /* 79: Event selected in the ICU.IELSR79 register */ +#define RA_IRQ_IELSR80 (RA_IRQ_FIRST + 80) /* 80: Event selected in the ICU.IELSR80 register */ +#define RA_IRQ_IELSR81 (RA_IRQ_FIRST + 81) /* 81: Event selected in the ICU.IELSR81 register */ +#define RA_IRQ_IELSR82 (RA_IRQ_FIRST + 82) /* 82: Event selected in the ICU.IELSR82 register */ +#define RA_IRQ_IELSR83 (RA_IRQ_FIRST + 83) /* 83: Event selected in the ICU.IELSR83 register */ +#define RA_IRQ_IELSR84 (RA_IRQ_FIRST + 84) /* 84: Event selected in the ICU.IELSR84 register */ +#define RA_IRQ_IELSR85 (RA_IRQ_FIRST + 85) /* 85: Event selected in the ICU.IELSR85 register */ +#define RA_IRQ_IELSR86 (RA_IRQ_FIRST + 86) /* 86: Event selected in the ICU.IELSR86 register */ +#define RA_IRQ_IELSR87 (RA_IRQ_FIRST + 87) /* 87: Event selected in the ICU.IELSR87 register */ +#define RA_IRQ_IELSR88 (RA_IRQ_FIRST + 88) /* 88: Event selected in the ICU.IELSR88 register */ +#define RA_IRQ_IELSR89 (RA_IRQ_FIRST + 89) /* 89: Event selected in the ICU.IELSR89 register */ +#define RA_IRQ_IELSR90 (RA_IRQ_FIRST + 90) /* 90: Event selected in the ICU.IELSR90 register */ +#define RA_IRQ_IELSR91 (RA_IRQ_FIRST + 91) /* 91: Event selected in the ICU.IELSR91 register */ +#define RA_IRQ_IELSR92 (RA_IRQ_FIRST + 92) /* 92: Event selected in the ICU.IELSR92 register */ +#define RA_IRQ_IELSR93 (RA_IRQ_FIRST + 93) /* 93: Event selected in the ICU.IELSR93 register */ +#define RA_IRQ_IELSR94 (RA_IRQ_FIRST + 94) /* 94: Event selected in the ICU.IELSR94 register */ +#define RA_IRQ_IELSR95 (RA_IRQ_FIRST + 95) /* 95: Event selected in the ICU.IELSR95 register */ + +#define RA_IRQ_NEXTINT (96) + +/* SCI_B interrupt events. + * + * The ICU routes any peripheral event to any of the IELSR slots, so the + * SCI_B events are simply given fixed slots: four per channel (receive data + * full, transmit data empty, transmit end, receive error). The numbers do + * not depend on which channels a build enables, so every file that uses + * them (ra_serial.c, ra_icu.c) sees the same value. Only RA_IRQ_IELSR0 to + * RA_IRQ_IELSR23 are used; ra_attach_icu() routes the events of the enabled + * channels to their slots. + * + * RA8M1 has SCI_B0-4 and SCI_B9 (no SCI_B5-8), named SCI0-4 and SCI9 here. + */ + +#define SCI0_RXI (RA_IRQ_FIRST + 0) /* Receive data full */ +#define SCI0_TXI (RA_IRQ_FIRST + 1) /* Transmit data empty */ +#define SCI0_TEI (RA_IRQ_FIRST + 2) /* Transmit end */ +#define SCI0_ERI (RA_IRQ_FIRST + 3) /* Receive error */ + +#define SCI1_RXI (RA_IRQ_FIRST + 4) /* Receive data full */ +#define SCI1_TXI (RA_IRQ_FIRST + 5) /* Transmit data empty */ +#define SCI1_TEI (RA_IRQ_FIRST + 6) /* Transmit end */ +#define SCI1_ERI (RA_IRQ_FIRST + 7) /* Receive error */ + +#define SCI2_RXI (RA_IRQ_FIRST + 8) /* Receive data full */ +#define SCI2_TXI (RA_IRQ_FIRST + 9) /* Transmit data empty */ +#define SCI2_TEI (RA_IRQ_FIRST + 10) /* Transmit end */ +#define SCI2_ERI (RA_IRQ_FIRST + 11) /* Receive error */ + +#define SCI3_RXI (RA_IRQ_FIRST + 12) /* Receive data full */ +#define SCI3_TXI (RA_IRQ_FIRST + 13) /* Transmit data empty */ +#define SCI3_TEI (RA_IRQ_FIRST + 14) /* Transmit end */ +#define SCI3_ERI (RA_IRQ_FIRST + 15) /* Receive error */ + +#define SCI4_RXI (RA_IRQ_FIRST + 16) /* Receive data full */ +#define SCI4_TXI (RA_IRQ_FIRST + 17) /* Transmit data empty */ +#define SCI4_TEI (RA_IRQ_FIRST + 18) /* Transmit end */ +#define SCI4_ERI (RA_IRQ_FIRST + 19) /* Receive error */ + +#define SCI9_RXI (RA_IRQ_FIRST + 20) /* Receive data full */ +#define SCI9_TXI (RA_IRQ_FIRST + 21) /* Transmit data empty */ +#define SCI9_TEI (RA_IRQ_FIRST + 22) /* Transmit end */ +#define SCI9_ERI (RA_IRQ_FIRST + 23) /* Receive error */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_RA8M1_RA8M1_IRQ_H */ diff --git a/arch/arm/src/cmake/armv8-m.cmake b/arch/arm/src/cmake/armv8-m.cmake index ab083c46796..24fb13efd3f 100644 --- a/arch/arm/src/cmake/armv8-m.cmake +++ b/arch/arm/src/cmake/armv8-m.cmake @@ -76,6 +76,16 @@ elseif(CONFIG_ARCH_CORTEXM55) if(CONFIG_ARCH_FPU) list(APPEND PLATFORM_FLAGS -mfpu=fpv5-d16) endif() +elseif(CONFIG_ARCH_CORTEXM85) + list(APPEND PLATFORM_FLAGS -mtune=cortex-m85) + if(CONFIG_ARM_HAVE_MVE) + list(APPEND PLATFORM_FLAGS -march=armv8.1-m.main${EXTCPUFLAGS}+mve.fp+fp.dp) + else() + list(APPEND PLATFORM_FLAGS -march=armv8.1-m.main${EXTCPUFLAGS}) + endif() + if(CONFIG_ARCH_FPU) + list(APPEND PLATFORM_FLAGS -mfpu=fpv5-d16) + endif() endif() if(CONFIG_ARCH_FPU) diff --git a/arch/arm/src/cmake/platform.cmake b/arch/arm/src/cmake/platform.cmake index 10f051eaf24..1f31e0eb6e3 100644 --- a/arch/arm/src/cmake/platform.cmake +++ b/arch/arm/src/cmake/platform.cmake @@ -38,6 +38,8 @@ elseif(CONFIG_ARCH_CORTEXM35P) set(CMAKE_SYSTEM_PROCESSOR cortex-m35p) elseif(CONFIG_ARCH_CORTEXM55) set(CMAKE_SYSTEM_PROCESSOR cortex-m55) +elseif(CONFIG_ARCH_CORTEXM85) + set(CMAKE_SYSTEM_PROCESSOR cortex-m85) elseif(CONFIG_ARCH_CORTEXA5) set(CMAKE_SYSTEM_PROCESSOR cortex-a5) elseif(CONFIG_ARCH_CORTEXA7) diff --git a/arch/arm/src/ra8m1/CMakeLists.txt b/arch/arm/src/ra8m1/CMakeLists.txt new file mode 100644 index 00000000000..575db6d404c --- /dev/null +++ b/arch/arm/src/ra8m1/CMakeLists.txt @@ -0,0 +1,33 @@ +# ############################################################################## +# arch/arm/src/ra8m1/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS + ra_start.c + ra_serial.c + ra_timerisr.c + ra_clockconfig.c + ra_option_setting.c + ra_irq.c + ra_lowputc.c + ra_icu.c + ra_gpio.c + ra_allocateheap.c) + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/ra8m1/Kconfig b/arch/arm/src/ra8m1/Kconfig new file mode 100644 index 00000000000..732c03df930 --- /dev/null +++ b/arch/arm/src/ra8m1/Kconfig @@ -0,0 +1,186 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "RA Configuration Options" + +choice + prompt "RA Chip Selection" + default ARCH_CHIP_R7FA8M1AHECFC + depends on ARCH_CHIP_RA8M1 + +config ARCH_CHIP_R7FA8M1AFECAM + bool "R7FA8M1AFECAM" + select RA_HAVE_SCI_B0 + select RA_HAVE_SCI_B1 + select RA_HAVE_SCI_B2 + select RA_HAVE_SCI_B3 + select RA_HAVE_SCI_B4 + select RA_HAVE_SCI_B9 + select RA8M1_FAMILY + +config ARCH_CHIP_R7FA8M1AFECBD + bool "R7FA8M1AFECBD" + select RA_HAVE_SCI_B0 + select RA_HAVE_SCI_B1 + select RA_HAVE_SCI_B2 + select RA_HAVE_SCI_B3 + select RA_HAVE_SCI_B4 + select RA_HAVE_SCI_B9 + select RA8M1_FAMILY + +config ARCH_CHIP_R7FA8M1AFECFB + bool "R7FA8M1AFECFB" + select RA_HAVE_SCI_B0 + select RA_HAVE_SCI_B1 + select RA_HAVE_SCI_B2 + select RA_HAVE_SCI_B3 + select RA_HAVE_SCI_B4 + select RA_HAVE_SCI_B9 + select RA8M1_FAMILY + +config ARCH_CHIP_R7FA8M1AFECFC + bool "R7FA8M1AFECFC" + select RA_HAVE_SCI_B0 + select RA_HAVE_SCI_B1 + select RA_HAVE_SCI_B2 + select RA_HAVE_SCI_B3 + select RA_HAVE_SCI_B4 + select RA_HAVE_SCI_B9 + select RA8M1_FAMILY + +config ARCH_CHIP_R7FA8M1AFECFP + bool "R7FA8M1AFECFP" + select RA_HAVE_SCI_B0 + select RA_HAVE_SCI_B1 + select RA_HAVE_SCI_B2 + select RA_HAVE_SCI_B3 + select RA_HAVE_SCI_B4 + select RA_HAVE_SCI_B9 + select RA8M1_FAMILY + +config ARCH_CHIP_R7FA8M1AHECAM + bool "R7FA8M1AHECAM" + select RA_HAVE_SCI_B0 + select RA_HAVE_SCI_B1 + select RA_HAVE_SCI_B2 + select RA_HAVE_SCI_B3 + select RA_HAVE_SCI_B4 + select RA_HAVE_SCI_B9 + select RA8M1_FAMILY + +config ARCH_CHIP_R7FA8M1AHECBD + bool "R7FA8M1AHECBD" + select RA_HAVE_SCI_B0 + select RA_HAVE_SCI_B1 + select RA_HAVE_SCI_B2 + select RA_HAVE_SCI_B3 + select RA_HAVE_SCI_B4 + select RA_HAVE_SCI_B9 + select RA8M1_FAMILY + +config ARCH_CHIP_R7FA8M1AHECFB + bool "R7FA8M1AHECFB" + select RA_HAVE_SCI_B0 + select RA_HAVE_SCI_B1 + select RA_HAVE_SCI_B2 + select RA_HAVE_SCI_B3 + select RA_HAVE_SCI_B4 + select RA_HAVE_SCI_B9 + select RA8M1_FAMILY + +config ARCH_CHIP_R7FA8M1AHECFC + bool "R7FA8M1AHECFC" + select RA_HAVE_SCI_B0 + select RA_HAVE_SCI_B1 + select RA_HAVE_SCI_B2 + select RA_HAVE_SCI_B3 + select RA_HAVE_SCI_B4 + select RA_HAVE_SCI_B9 + select RA8M1_FAMILY + +config ARCH_CHIP_R7FA8M1AHECFP + bool "R7FA8M1AHECFP" + select RA_HAVE_SCI_B0 + select RA_HAVE_SCI_B1 + select RA_HAVE_SCI_B2 + select RA_HAVE_SCI_B3 + select RA_HAVE_SCI_B4 + select RA_HAVE_SCI_B9 + select RA8M1_FAMILY + +endchoice # RA Chip Selection + +config RA8M1_FAMILY + bool + default n + select ARCH_CORTEXM85 + +menu "RA8M1 Peripheral Support" + +config RA_HAVE_SCI_B0 + bool + default n + +config RA_HAVE_SCI_B1 + bool + default n + +config RA_HAVE_SCI_B2 + bool + default n + +config RA_HAVE_SCI_B3 + bool + default n + +config RA_HAVE_SCI_B4 + bool + default n + +config RA_HAVE_SCI_B9 + bool + default n + +# TODO: user-facing enable options go here, one per +# RA_HAVE_* above (prompt, depends on RA_HAVE_*, select +# the driver it wires up -- see README "Kconfig draft"). + +config RA_SCI0_UART + bool "UART 0" + default n + depends on RA_HAVE_SCI_B0 + select SCI0_SERIALDRIVER + +config RA_SCI1_UART + bool "UART 1" + default n + depends on RA_HAVE_SCI_B1 + select SCI1_SERIALDRIVER + +config RA_SCI2_UART + bool "UART 2" + default n + depends on RA_HAVE_SCI_B2 + select SCI2_SERIALDRIVER + +config RA_SCI3_UART + bool "UART 3" + default n + depends on RA_HAVE_SCI_B3 + select SCI3_SERIALDRIVER + +config RA_SCI4_UART + bool "UART 4" + default n + depends on RA_HAVE_SCI_B4 + select SCI4_SERIALDRIVER + +config RA_SCI9_UART + bool "UART 9" + default n + depends on RA_HAVE_SCI_B9 + select SCI9_SERIALDRIVER + +endmenu # RA8M1 Peripheral Support diff --git a/arch/arm/src/ra8m1/Make.defs b/arch/arm/src/ra8m1/Make.defs new file mode 100644 index 00000000000..f2739593327 --- /dev/null +++ b/arch/arm/src/ra8m1/Make.defs @@ -0,0 +1,38 @@ +############################################################################ +# arch/arm/src/ra8m1/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# The start-up, "head", file + +# Common ARM and Cortex-M85 (ARMv8-M) files + +include armv8-m/Make.defs + +# Required RA files + +CHIP_CSRCS += ra_start.c +CHIP_CSRCS += ra_clockconfig.c +CHIP_CSRCS += ra_option_setting.c +CHIP_CSRCS += ra_irq.c +CHIP_CSRCS += ra_icu.c +CHIP_CSRCS += ra_gpio.c +CHIP_CSRCS += ra_serial.c +CHIP_CSRCS += ra_lowputc.c +CHIP_CSRCS += ra_allocateheap.c +CHIP_CSRCS += ra_timerisr.c diff --git a/arch/arm/src/ra8m1/chip.h b/arch/arm/src/ra8m1/chip.h new file mode 100644 index 00000000000..a4e50f5bb2d --- /dev/null +++ b/arch/arm/src/ra8m1/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_CHIP_H +#define __ARCH_ARM_SRC_RA8M1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the memory map and the chip definitions file. Other chip + * hardware files should then include this file for the proper setup. + */ + +#include +#include "hardware/ra8m1_memorymap.h" + +/* Include the chip interrupt definition file */ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The common ARMv8-M vector handling logic expects the number of external + * interrupts here. RA_IRQ_NEXTINT comes from the chip IRQ header (one NVIC + * vector per ICU IELSR slot). + */ + +#define ARMV8M_PERIPHERAL_INTERRUPTS RA_IRQ_NEXTINT + +/* The Cortex-M85 caches have 32 byte lines */ + +#define ARMV8M_ICACHE_LINESIZE 32 +#define ARMV8M_DCACHE_LINESIZE 32 + +#endif /* __ARCH_ARM_SRC_RA8M1_CHIP_H */ diff --git a/arch/arm/src/ra8m1/hardware/ra8m1_elc.h b/arch/arm/src/ra8m1/hardware/ra8m1_elc.h new file mode 100644 index 00000000000..5450e85329a --- /dev/null +++ b/arch/arm/src/ra8m1/hardware/ra8m1_elc.h @@ -0,0 +1,367 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/hardware/ra8m1_elc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ELC_H +#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ELC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EVENT_NONE (0x000) /* Link disabled */ +#define EVENT_ICU_IRQ0 (0x001) /* External pin interrupt 0 */ +#define EVENT_ICU_IRQ1 (0x002) /* External pin interrupt 1 */ +#define EVENT_ICU_IRQ2 (0x003) /* External pin interrupt 2 */ +#define EVENT_ICU_IRQ3 (0x004) /* External pin interrupt 3 */ +#define EVENT_ICU_IRQ4 (0x005) /* External pin interrupt 4 */ +#define EVENT_ICU_IRQ5 (0x006) /* External pin interrupt 5 */ +#define EVENT_ICU_IRQ6 (0x007) /* External pin interrupt 6 */ +#define EVENT_ICU_IRQ7 (0x008) /* External pin interrupt 7 */ +#define EVENT_ICU_IRQ8 (0x009) /* External pin interrupt 8 */ +#define EVENT_ICU_IRQ9 (0x00A) /* External pin interrupt 9 */ +#define EVENT_ICU_IRQ10 (0x00B) /* External pin interrupt 10 */ +#define EVENT_ICU_IRQ11 (0x00C) /* External pin interrupt 11 */ +#define EVENT_ICU_IRQ12 (0x00D) /* External pin interrupt 12 */ +#define EVENT_ICU_IRQ13 (0x00E) /* External pin interrupt 13 */ +#define EVENT_ICU_IRQ14 (0x00F) /* External pin interrupt 14 */ +#define EVENT_ICU_IRQ15 (0x010) /* External pin interrupt 15 */ +#define EVENT_DMAC0_INT (0x011) /* DMAC0 transfer end */ +#define EVENT_DMAC1_INT (0x012) /* DMAC1 transfer end */ +#define EVENT_DMAC2_INT (0x013) /* DMAC2 transfer end */ +#define EVENT_DMAC3_INT (0x014) /* DMAC3 transfer end */ +#define EVENT_DMAC4_INT (0x015) /* DMAC4 transfer end */ +#define EVENT_DMAC5_INT (0x016) /* DMAC5 transfer end */ +#define EVENT_DMAC6_INT (0x017) /* DMAC6 transfer end */ +#define EVENT_DMAC7_INT (0x018) /* DMAC7 transfer end */ +#define EVENT_DTC_END (0x021) /* DTC transfer end */ +#define EVENT_DTC_COMPLETE (0x022) /* DTC transfer complete */ +#define EVENT_DMA_TRANSERR (0x027) /* DMA/DTC transfer error */ +#define EVENT_DBG_CTIIRQ0 (0x029) /* Coresight Crosstrigger Event */ +#define EVENT_DBG_CTIIRQ1 (0x02A) /* Coresight Crosstrigger Event */ +#define EVENT_DBG_JBRXI (0x02B) /* JB RXI */ +#define EVENT_FCU_FIFERR (0x030) /* Flash access error interrupt */ +#define EVENT_FCU_FRDYI (0x031) /* Flash ready interrupt */ +#define EVENT_LVD_LVD1 (0x038) /* Voltage monitor 1 interrupt */ +#define EVENT_LVD_LVD2 (0x039) /* Voltage monitor 2 interrupt */ +#define EVENT_VBATT_TADI (0x03D) /* VBATT Tamper Detection */ +#define EVENT_CGC_MOSC_STOP (0x03E) /* Main Clock oscillation stop */ +#define EVENT_ULPT0_INT (0x040) /* ULPT0 Underflow */ +#define EVENT_ULPT0_COMPARE_A (0x041) /* ULPT0 Compare match A */ +#define EVENT_ULPT0_COMPARE_B (0x042) /* ULPT0 Compare match B */ +#define EVENT_ULPT1_INT (0x043) /* ULPT1 Underflow */ +#define EVENT_ULPT1_COMPARE_A (0x044) /* ULPT1 Compare match A */ +#define EVENT_ULPT1_COMPARE_B (0x045) /* ULPT1 Compare match B */ +#define EVENT_AGT0_INT (0x046) /* AGT interrupt */ +#define EVENT_AGT0_COMPARE_A (0x047) /* Compare match A */ +#define EVENT_AGT0_COMPARE_B (0x048) /* Compare match B */ +#define EVENT_AGT1_INT (0x049) /* AGT interrupt */ +#define EVENT_AGT1_COMPARE_A (0x04A) /* Compare match A */ +#define EVENT_AGT1_COMPARE_B (0x04B) /* Compare match B */ +#define EVENT_IWDT_UNDERFLOW (0x052) /* IWDT underflow */ +#define EVENT_WDT0_UNDERFLOW (0x053) /* WDT0 underflow */ +#define EVENT_RTC_ALARM (0x055) /* Alarm interrupt */ +#define EVENT_RTC_PERIOD (0x056) /* Periodic interrupt */ +#define EVENT_RTC_CARRY (0x057) /* Carry interrupt */ +#define EVENT_USBFS_FIFO_0 (0x058) /* DMA/DTC transfer request 0 */ +#define EVENT_USBFS_FIFO_1 (0x059) /* DMA/DTC transfer request 1 */ +#define EVENT_USBFS_INT (0x05A) /* USBFS interrupt */ +#define EVENT_USBFS_RESUME (0x05B) /* USBFS resume interrupt */ +#define EVENT_IIC0_RXI (0x05C) /* Receive data full */ +#define EVENT_IIC0_TXI (0x05D) /* Transmit data empty */ +#define EVENT_IIC0_TEI (0x05E) /* Transmit end */ +#define EVENT_IIC0_ERI (0x05F) /* Transfer error */ +#define EVENT_IIC0_WUI (0x060) /* Wakeup interrupt */ +#define EVENT_IIC1_RXI (0x061) /* Receive data full */ +#define EVENT_IIC1_TXI (0x062) /* Transmit data empty */ +#define EVENT_IIC1_TEI (0x063) /* Transmit end */ +#define EVENT_IIC1_ERI (0x064) /* Transfer error */ +#define EVENT_SDHIMMC0_ACCS (0x06B) /* Card access */ +#define EVENT_SDHIMMC0_SDIO (0x06C) /* SDIO access */ +#define EVENT_SDHIMMC0_CARD (0x06D) /* Card detect */ +#define EVENT_SDHIMMC0_DMA_REQ (0x06E) /* DMA transfer request */ +#define EVENT_SDHIMMC1_ACCS (0x06F) /* Card access */ +#define EVENT_SDHIMMC1_SDIO (0x070) /* SDIO access */ +#define EVENT_SDHIMMC1_CARD (0x071) /* Card detect */ +#define EVENT_SDHIMMC1_DMA_REQ (0x072) /* DMA transfer request */ +#define EVENT_SSI0_TXI (0x073) /* Transmit data empty */ +#define EVENT_SSI0_RXI (0x074) /* Receive data full */ +#define EVENT_SSI0_INT (0x076) /* Error interrupt */ +#define EVENT_SSI1_TXI (0x079) /* Receive data full/Transmit data empty */ +#define EVENT_SSI1_RXI (0x079) /* Receive data full/Transmit data empty */ +#define EVENT_SSI1_INT (0x07A) /* Error interrupt */ +#define EVENT_ACMPHS0_INT (0x07B) /* High Speed Comparator channel 0 interrupt */ +#define EVENT_ACMPHS1_INT (0x07C) /* High Speed Comparator channel 1 interrupt */ +#define EVENT_ELC_SOFTWARE_EVENT_0 (0x083) /* Software event 0 */ +#define EVENT_ELC_SOFTWARE_EVENT_1 (0x084) /* Software event 1 */ +#define EVENT_IOPORT_EVENT_1 (0x088) /* Port 1 event */ +#define EVENT_IOPORT_EVENT_2 (0x089) /* Port 2 event */ +#define EVENT_IOPORT_EVENT_3 (0x08A) /* Port 3 event */ +#define EVENT_IOPORT_EVENT_4 (0x08B) /* Port 4 event */ +#define EVENT_CAC_FREQUENCY_ERROR (0x08C) /* Frequency error interrupt */ +#define EVENT_CAC_MEASUREMENT_END (0x08D) /* Measurement end interrupt */ +#define EVENT_CAC_OVERFLOW (0x08E) /* Overflow interrupt */ +#define EVENT_POEG0_EVENT (0x08F) /* Port Output disable 0 interrupt */ +#define EVENT_POEG1_EVENT (0x090) /* Port Output disable 1 interrupt */ +#define EVENT_POEG2_EVENT (0x091) /* Port Output disable 2 interrupt */ +#define EVENT_POEG3_EVENT (0x092) /* Port Output disable 3 interrupt */ +#define EVENT_OPS_UVW_EDGE (0x0A0) /* UVW edge event */ +#define EVENT_GPT0_CAPTURE_COMPARE_A (0x0A1) /* Capture/Compare match A */ +#define EVENT_GPT0_CAPTURE_COMPARE_B (0x0A2) /* Capture/Compare match B */ +#define EVENT_GPT0_COMPARE_C (0x0A3) /* Compare match C */ +#define EVENT_GPT0_COMPARE_D (0x0A4) /* Compare match D */ +#define EVENT_GPT0_COMPARE_E (0x0A5) /* Compare match E */ +#define EVENT_GPT0_COMPARE_F (0x0A6) /* Compare match F */ +#define EVENT_GPT0_COUNTER_OVERFLOW (0x0A7) /* Overflow */ +#define EVENT_GPT0_COUNTER_UNDERFLOW (0x0A8) /* Underflow */ +#define EVENT_GPT0_PC (0x0A9) /* Period count function finish */ +#define EVENT_GPT1_CAPTURE_COMPARE_A (0x0AA) /* Capture/Compare match A */ +#define EVENT_GPT1_CAPTURE_COMPARE_B (0x0AB) /* Capture/Compare match B */ +#define EVENT_GPT1_COMPARE_C (0x0AC) /* Compare match C */ +#define EVENT_GPT1_COMPARE_D (0x0AD) /* Compare match D */ +#define EVENT_GPT1_COMPARE_E (0x0AE) /* Compare match E */ +#define EVENT_GPT1_COMPARE_F (0x0AF) /* Compare match F */ +#define EVENT_GPT1_COUNTER_OVERFLOW (0x0B0) /* Overflow */ +#define EVENT_GPT1_COUNTER_UNDERFLOW (0x0B1) /* Underflow */ +#define EVENT_GPT1_PC (0x0B2) /* Period count function finish */ +#define EVENT_GPT2_CAPTURE_COMPARE_A (0x0B3) /* Capture/Compare match A */ +#define EVENT_GPT2_CAPTURE_COMPARE_B (0x0B4) /* Capture/Compare match B */ +#define EVENT_GPT2_COMPARE_C (0x0B5) /* Compare match C */ +#define EVENT_GPT2_COMPARE_D (0x0B6) /* Compare match D */ +#define EVENT_GPT2_COMPARE_E (0x0B7) /* Compare match E */ +#define EVENT_GPT2_COMPARE_F (0x0B8) /* Compare match F */ +#define EVENT_GPT2_COUNTER_OVERFLOW (0x0B9) /* Overflow */ +#define EVENT_GPT2_COUNTER_UNDERFLOW (0x0BA) /* Underflow */ +#define EVENT_GPT2_PC (0x0BB) /* Period count function finish */ +#define EVENT_GPT3_CAPTURE_COMPARE_A (0x0BC) /* Capture/Compare match A */ +#define EVENT_GPT3_CAPTURE_COMPARE_B (0x0BD) /* Capture/Compare match B */ +#define EVENT_GPT3_COMPARE_C (0x0BE) /* Compare match C */ +#define EVENT_GPT3_COMPARE_D (0x0BF) /* Compare match D */ +#define EVENT_GPT3_COMPARE_E (0x0C0) /* Compare match E */ +#define EVENT_GPT3_COMPARE_F (0x0C1) /* Compare match F */ +#define EVENT_GPT3_COUNTER_OVERFLOW (0x0C2) /* Overflow */ +#define EVENT_GPT3_COUNTER_UNDERFLOW (0x0C3) /* Underflow */ +#define EVENT_GPT3_PC (0x0C4) /* Period count function finish */ +#define EVENT_GPT4_CAPTURE_COMPARE_A (0x0C5) /* Capture/Compare match A */ +#define EVENT_GPT4_CAPTURE_COMPARE_B (0x0C6) /* Capture/Compare match B */ +#define EVENT_GPT4_COMPARE_C (0x0C7) /* Compare match C */ +#define EVENT_GPT4_COMPARE_D (0x0C8) /* Compare match D */ +#define EVENT_GPT4_COMPARE_E (0x0C9) /* Compare match E */ +#define EVENT_GPT4_COMPARE_F (0x0CA) /* Compare match F */ +#define EVENT_GPT4_COUNTER_OVERFLOW (0x0CB) /* Overflow */ +#define EVENT_GPT4_COUNTER_UNDERFLOW (0x0CC) /* Underflow */ +#define EVENT_GPT5_CAPTURE_COMPARE_A (0x0CE) /* Capture/Compare match A */ +#define EVENT_GPT5_CAPTURE_COMPARE_B (0x0CF) /* Capture/Compare match B */ +#define EVENT_GPT5_COMPARE_C (0x0D0) /* Compare match C */ +#define EVENT_GPT5_COMPARE_D (0x0D1) /* Compare match D */ +#define EVENT_GPT5_COMPARE_E (0x0D2) /* Compare match E */ +#define EVENT_GPT5_COMPARE_F (0x0D3) /* Compare match F */ +#define EVENT_GPT5_COUNTER_OVERFLOW (0x0D4) /* Overflow */ +#define EVENT_GPT5_COUNTER_UNDERFLOW (0x0D5) /* Underflow */ +#define EVENT_GPT6_CAPTURE_COMPARE_A (0x0D7) /* Capture/Compare match A */ +#define EVENT_GPT6_CAPTURE_COMPARE_B (0x0D8) /* Capture/Compare match B */ +#define EVENT_GPT6_COMPARE_C (0x0D9) /* Compare match C */ +#define EVENT_GPT6_COMPARE_D (0x0DA) /* Compare match D */ +#define EVENT_GPT6_COMPARE_E (0x0DB) /* Compare match E */ +#define EVENT_GPT6_COMPARE_F (0x0DC) /* Compare match F */ +#define EVENT_GPT6_COUNTER_OVERFLOW (0x0DD) /* Overflow */ +#define EVENT_GPT6_COUNTER_UNDERFLOW (0x0DE) /* Underflow */ +#define EVENT_GPT7_CAPTURE_COMPARE_A (0x0E0) /* Capture/Compare match A */ +#define EVENT_GPT7_CAPTURE_COMPARE_B (0x0E1) /* Capture/Compare match B */ +#define EVENT_GPT7_COMPARE_C (0x0E2) /* Compare match C */ +#define EVENT_GPT7_COMPARE_D (0x0E3) /* Compare match D */ +#define EVENT_GPT7_COMPARE_E (0x0E4) /* Compare match E */ +#define EVENT_GPT7_COMPARE_F (0x0E5) /* Compare match F */ +#define EVENT_GPT7_COUNTER_OVERFLOW (0x0E6) /* Overflow */ +#define EVENT_GPT7_COUNTER_UNDERFLOW (0x0E7) /* Underflow */ +#define EVENT_GPT8_CAPTURE_COMPARE_A (0x0E9) /* Capture/Compare match A */ +#define EVENT_GPT8_CAPTURE_COMPARE_B (0x0EA) /* Capture/Compare match B */ +#define EVENT_GPT8_COMPARE_C (0x0EB) /* Compare match C */ +#define EVENT_GPT8_COMPARE_D (0x0EC) /* Compare match D */ +#define EVENT_GPT8_COMPARE_E (0x0ED) /* Compare match E */ +#define EVENT_GPT8_COMPARE_F (0x0EE) /* Compare match F */ +#define EVENT_GPT8_COUNTER_OVERFLOW (0x0EF) /* Overflow */ +#define EVENT_GPT8_COUNTER_UNDERFLOW (0x0F0) /* Underflow */ +#define EVENT_GPT8_PC (0x0F1) /* Period count function finish */ +#define EVENT_GPT9_CAPTURE_COMPARE_A (0x0F2) /* Capture/Compare match A */ +#define EVENT_GPT9_CAPTURE_COMPARE_B (0x0F3) /* Capture/Compare match B */ +#define EVENT_GPT9_COMPARE_C (0x0F4) /* Compare match C */ +#define EVENT_GPT9_COMPARE_D (0x0F5) /* Compare match D */ +#define EVENT_GPT9_COMPARE_E (0x0F6) /* Compare match E */ +#define EVENT_GPT9_COMPARE_F (0x0F7) /* Compare match F */ +#define EVENT_GPT9_COUNTER_OVERFLOW (0x0F8) /* Overflow */ +#define EVENT_GPT9_COUNTER_UNDERFLOW (0x0F9) /* Underflow */ +#define EVENT_GPT9_PC (0x0FA) /* Period count function finish */ +#define EVENT_GPT10_CAPTURE_COMPARE_A (0x0FB) /* Capture/Compare match A */ +#define EVENT_GPT10_CAPTURE_COMPARE_B (0x0FC) /* Capture/Compare match B */ +#define EVENT_GPT10_COMPARE_C (0x0FD) /* Compare match C */ +#define EVENT_GPT10_COMPARE_D (0x0FE) /* Compare match D */ +#define EVENT_GPT10_COMPARE_E (0x0FF) /* Compare match E */ +#define EVENT_GPT10_COMPARE_F (0x100) /* Compare match F */ +#define EVENT_GPT10_COUNTER_OVERFLOW (0x101) /* Overflow */ +#define EVENT_GPT10_COUNTER_UNDERFLOW (0x102) /* Underflow */ +#define EVENT_GPT10_PC (0x103) /* Period count function finish */ +#define EVENT_GPT11_CAPTURE_COMPARE_A (0x104) /* Capture/Compare match A */ +#define EVENT_GPT11_CAPTURE_COMPARE_B (0x105) /* Capture/Compare match B */ +#define EVENT_GPT11_COMPARE_C (0x106) /* Compare match C */ +#define EVENT_GPT11_COMPARE_D (0x107) /* Compare match D */ +#define EVENT_GPT11_COMPARE_E (0x108) /* Compare match E */ +#define EVENT_GPT11_COMPARE_F (0x109) /* Compare match F */ +#define EVENT_GPT11_COUNTER_OVERFLOW (0x10A) /* Overflow */ +#define EVENT_GPT11_COUNTER_UNDERFLOW (0x10B) /* Underflow */ +#define EVENT_GPT12_CAPTURE_COMPARE_A (0x10D) /* Capture/Compare match A */ +#define EVENT_GPT12_CAPTURE_COMPARE_B (0x10E) /* Capture/Compare match B */ +#define EVENT_GPT12_COMPARE_C (0x10F) /* Compare match C */ +#define EVENT_GPT12_COMPARE_D (0x110) /* Compare match D */ +#define EVENT_GPT12_COMPARE_E (0x111) /* Compare match E */ +#define EVENT_GPT12_COMPARE_F (0x112) /* Compare match F */ +#define EVENT_GPT12_COUNTER_OVERFLOW (0x113) /* Overflow */ +#define EVENT_GPT12_COUNTER_UNDERFLOW (0x114) /* Underflow */ +#define EVENT_GPT13_CAPTURE_COMPARE_A (0x116) /* Capture/Compare match A */ +#define EVENT_GPT13_CAPTURE_COMPARE_B (0x117) /* Capture/Compare match B */ +#define EVENT_GPT13_COMPARE_C (0x118) /* Compare match C */ +#define EVENT_GPT13_COMPARE_D (0x119) /* Compare match D */ +#define EVENT_GPT13_COMPARE_E (0x11A) /* Compare match E */ +#define EVENT_GPT13_COMPARE_F (0x11B) /* Compare match F */ +#define EVENT_GPT13_COUNTER_OVERFLOW (0x11C) /* Overflow */ +#define EVENT_GPT13_COUNTER_UNDERFLOW (0x11D) /* Underflow */ +#define EVENT_EDMAC0_EINT (0x120) /* EDMAC 0 interrupt */ +#define EVENT_USBHS_FIFO_0 (0x121) /* DMA transfer request 0 */ +#define EVENT_USBHS_FIFO_1 (0x122) /* DMA transfer request 1 */ +#define EVENT_USBHS_USB_INT_RESUME (0x123) /* USBHS interrupt */ +#define EVENT_SCI0_RXI (0x124) /* Receive data full */ +#define EVENT_SCI0_TXI (0x125) /* Transmit data empty */ +#define EVENT_SCI0_TEI (0x126) /* Transmit end */ +#define EVENT_SCI0_ERI (0x127) /* Receive error */ +#define EVENT_SCI0_AED (0x128) /* Active edge detection */ +#define EVENT_SCI0_BFD (0x129) /* Break field detection */ +#define EVENT_SCI0_AM (0x12A) /* Address match event */ +#define EVENT_SCI1_RXI (0x12B) /* Receive data full */ +#define EVENT_SCI1_TXI (0x12C) /* Transmit data empty */ +#define EVENT_SCI1_TEI (0x12D) /* Transmit end */ +#define EVENT_SCI1_ERI (0x12E) /* Receive error */ +#define EVENT_SCI1_AED (0x12F) /* Active edge detection */ +#define EVENT_SCI1_BFD (0x130) /* Break field detection */ +#define EVENT_SCI1_AM (0x131) /* Address match event */ +#define EVENT_SCI2_RXI (0x132) /* Receive data full */ +#define EVENT_SCI2_TXI (0x133) /* Transmit data empty */ +#define EVENT_SCI2_TEI (0x134) /* Transmit end */ +#define EVENT_SCI2_ERI (0x135) /* Receive error */ +#define EVENT_SCI2_AM (0x138) /* Address match event */ +#define EVENT_SCI3_RXI (0x139) /* Receive data full */ +#define EVENT_SCI3_TXI (0x13A) /* Transmit data empty */ +#define EVENT_SCI3_TEI (0x13B) /* Transmit end */ +#define EVENT_SCI3_ERI (0x13C) /* Receive error */ +#define EVENT_SCI3_AM (0x13F) /* Address match event */ +#define EVENT_SCI4_RXI (0x140) /* Receive data full */ +#define EVENT_SCI4_TXI (0x141) /* Transmit data empty */ +#define EVENT_SCI4_TEI (0x142) /* Transmit end */ +#define EVENT_SCI4_ERI (0x143) /* Receive error */ +#define EVENT_SCI4_AM (0x146) /* Address match event */ +#define EVENT_SCI9_RXI (0x163) /* Receive data full */ +#define EVENT_SCI9_TXI (0x164) /* Transmit data empty */ +#define EVENT_SCI9_TEI (0x165) /* Transmit end */ +#define EVENT_SCI9_ERI (0x166) /* Receive error */ +#define EVENT_SCI9_AM (0x169) /* Address match event */ +#define EVENT_SPI0_RXI (0x178) /* Receive buffer full */ +#define EVENT_SPI0_TXI (0x179) /* Transmit buffer empty */ +#define EVENT_SPI0_IDLE (0x17A) /* Idle */ +#define EVENT_SPI0_ERI (0x17B) /* Error */ +#define EVENT_SPI0_TEI (0x17C) /* Transmission complete event */ +#define EVENT_SPI1_RXI (0x17D) /* Receive buffer full */ +#define EVENT_SPI1_TXI (0x17E) /* Transmit buffer empty */ +#define EVENT_SPI1_IDLE (0x17F) /* Idle */ +#define EVENT_SPI1_ERI (0x180) /* Error */ +#define EVENT_SPI1_TEI (0x181) /* Transmission complete event */ +#define EVENT_XSPI_ERR (0x182) /* xSPI Error */ +#define EVENT_XSPI_CMP (0x183) /* xSPI Complete */ +#define EVENT_CAN_RXF (0x185) /* Global receive FIFO interrupt */ +#define EVENT_CAN_GLERR (0x186) /* Global error */ +#define EVENT_CAN0_DMAREQ0 (0x187) /* RX fifo DMA request 0 */ +#define EVENT_CAN0_DMAREQ1 (0x188) /* RX fifo DMA request 1 */ +#define EVENT_CAN1_DMAREQ0 (0x18B) /* RX fifo DMA request 0 */ +#define EVENT_CAN1_DMAREQ1 (0x18C) /* RX fifo DMA request 1 */ +#define EVENT_CAN0_TX (0x18F) /* Transmit interrupt */ +#define EVENT_CAN0_CHERR (0x190) /* Channel error */ +#define EVENT_CAN0_COMFRX (0x191) /* Common FIFO receive interrupt */ +#define EVENT_CAN0_CF_DMAREQ (0x192) /* Channel DMA request */ +#define EVENT_CAN0_RXMB (0x193) /* Receive message buffer interrupt */ +#define EVENT_CAN1_TX (0x194) /* Transmit interrupt */ +#define EVENT_CAN1_CHERR (0x195) /* Channel error */ +#define EVENT_CAN1_COMFRX (0x196) /* Common FIFO receive interrupt */ +#define EVENT_CAN1_CF_DMAREQ (0x197) /* Channel DMA request */ +#define EVENT_CAN1_RXMB (0x198) /* Receive message buffer interrupt */ +#define EVENT_CAN0_MRAM_ERI (0x19B) /* CANFD0 ECC error */ +#define EVENT_CAN1_MRAM_ERI (0x19C) /* CANFD1 ECC error */ +#define EVENT_I3C0_RESPONSE (0x19D) /* Response status buffer full */ +#define EVENT_I3C0_COMMAND (0x19E) /* Command buffer empty */ +#define EVENT_I3C0_IBI (0x19F) /* IBI status buffer full */ +#define EVENT_I3C0_RX (0x1A0) /* Receive */ +#define EVENT_IICB0_RXI (0x1A0) /* Receive */ +#define EVENT_I3C0_TX (0x1A1) /* Transmit */ +#define EVENT_IICB0_TXI (0x1A1) /* Transmit */ +#define EVENT_I3C0_RCV_STATUS (0x1A2) /* Receive status buffer full */ +#define EVENT_I3C0_HRESP (0x1A3) /* High priority response queue full */ +#define EVENT_I3C0_HCMD (0x1A4) /* High priority command queue empty */ +#define EVENT_I3C0_HRX (0x1A5) /* High priority rx data buffer full */ +#define EVENT_I3C0_HTX (0x1A6) /* High priority tx data buffer empty */ +#define EVENT_I3C0_TEND (0x1A7) /* Transmit end */ +#define EVENT_IICB0_TEI (0x1A7) /* Transmit end */ +#define EVENT_I3C0_EEI (0x1A8) /* Error */ +#define EVENT_IICB0_ERI (0x1A8) /* Error */ +#define EVENT_I3C0_STEV (0x1A9) /* Synchronous timing */ +#define EVENT_I3C0_MREFOVF (0x1AA) /* MREF counter overflow */ +#define EVENT_I3C0_MREFCPT (0x1AB) /* MREF capture */ +#define EVENT_I3C0_AMEV (0x1AC) /* Additional master-initiated bus event */ +#define EVENT_I3C0_WU (0x1AD) /* Wake-up Condition Detection interrupt */ +#define EVENT_ADC0_SCAN_END (0x1AE) /* End of A/D scanning operation */ +#define EVENT_ADC0_SCAN_END_B (0x1AF) /* A/D scan end interrupt for group B */ +#define EVENT_ADC0_WINDOW_A (0x1B0) /* Window A Compare match interrupt */ +#define EVENT_ADC0_WINDOW_B (0x1B1) /* Window B Compare match interrupt */ +#define EVENT_ADC0_COMPARE_MATCH (0x1B2) /* Compare match */ +#define EVENT_ADC0_COMPARE_MISMATCH (0x1B3) /* Compare mismatch */ +#define EVENT_ADC1_SCAN_END (0x1B4) /* End of A/D scanning operation */ +#define EVENT_ADC1_SCAN_END_B (0x1B5) /* A/D scan end interrupt for group B */ +#define EVENT_ADC1_WINDOW_A (0x1B6) /* Window A Compare match interrupt */ +#define EVENT_ADC1_WINDOW_B (0x1B7) /* Window B Compare match interrupt */ +#define EVENT_ADC1_COMPARE_MATCH (0x1B8) /* Compare match */ +#define EVENT_ADC1_COMPARE_MISMATCH (0x1B9) /* Compare mismatch */ +#define EVENT_DOC_INT (0x1BA) /* Data operation circuit interrupt */ +#define EVENT_RSIP_TADI (0x1BC) /* RSIP Tamper Detection */ +#define EVENT_CEU_CEUI (0x1DA) /* CEU interrupt */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ELC_H */ diff --git a/arch/arm/src/ra8m1/hardware/ra8m1_fcache.h b/arch/arm/src/ra8m1/hardware/ra8m1_fcache.h new file mode 100644 index 00000000000..726b00c812b --- /dev/null +++ b/arch/arm/src/ra8m1/hardware/ra8m1_fcache.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/hardware/ra8m1_fcache.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_FCACHE_H +#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_FCACHE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/ra8m1_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define R_FCACHE_FCACHEE_OFFSET 0x0000 /* Flash Cache Enable Register (16-bits) */ +#define R_FCACHE_FCACHEIV_OFFSET 0x0004 /* Flash Cache Invalidate Register (16-bits) */ +#define R_FCACHE_FLWT_OFFSET 0x001c /* Flash Wait Cycle Register (8-bits) */ +#define R_FCACHE_FSAR_OFFSET 0x0040 /* Flash Security Attribution Register (16-bits) */ + +/* Register Addresses *******************************************************/ + +/* FCACHE Registers */ + +#define R_FCACHE_FCACHEE (R_FCACHE_BASE + R_FCACHE_FCACHEE_OFFSET) +#define R_FCACHE_FCACHEIV (R_FCACHE_BASE + R_FCACHE_FCACHEIV_OFFSET) +#define R_FCACHE_FLWT (R_FCACHE_BASE + R_FCACHE_FLWT_OFFSET) +#define R_FCACHE_FSAR (R_FCACHE_BASE + R_FCACHE_FSAR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Flash Cache Enable Register (16-bits) ************************************/ + +#define R_FCACHE_FCACHEE_FCACHEEN (1 << 0) /* 01: Flash Cache Enable */ + +/* Flash Cache Invalidate Register (16-bits) ********************************/ + +#define R_FCACHE_FCACHEIV_FCACHEIV (1 << 0) /* 01: Flash Cache Invalidate */ + +/* Flash Wait Cycle Register (8-bits) ***************************************/ + +#define R_FCACHE_FLWT_FLWT_SHIFT (0) +#define R_FCACHE_FLWT_FLWT_MASK (0x7) +# define R_FCACHE_FLWT_FLWT_V0_WAIT_ICLK_48MHZ (0 << R_FCACHE_FLWT_FLWT_SHIFT) /* 0 wait (ICLK <= 48MHz) */ +# define R_FCACHE_FLWT_FLWT_V001 (1 << R_FCACHE_FLWT_FLWT_SHIFT) /* 1 wait (48MHz < ICLK <= 96MHz) */ +# define R_FCACHE_FLWT_FLWT_V010 (2 << R_FCACHE_FLWT_FLWT_SHIFT) /* 2 waits (96MHz < ICLK <= 144MHz) */ +# define R_FCACHE_FLWT_FLWT_V011 (3 << R_FCACHE_FLWT_FLWT_SHIFT) /* 3 waits (144Hz < ICLK <= 192MHz) */ +# define R_FCACHE_FLWT_FLWT_V100 (4 << R_FCACHE_FLWT_FLWT_SHIFT) /* 4 waits (192Hz < ICLK <= 240MHz) */ + +/* Flash Security Attribution Register (16-bits) ****************************/ + +#define R_FCACHE_FSAR_FLWTSA (1 << 0) /* 01: FLWT Security Attribution */ +#define R_FCACHE_FSAR_FCACHEENSA (1 << 1) /* 02: FCHACHEEN Security Attribution */ +#define R_FCACHE_FSAR_FCKMHZSA (1 << 8) /* 100: FCKMHZ Security Attribution */ +#define R_FCACHE_FSAR_FACICOMISA (1 << 9) /* 200: FACI command Issuing Security Attribution */ +#define R_FCACHE_FSAR_FACICOMRSA (1 << 10) /* 400: FACI command Registers Security Attribution */ +#define R_FCACHE_FSAR_FACITRSA (1 << 11) /* 800: FACI transfer Security Attribution */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_FCACHE_H */ diff --git a/arch/arm/src/ra8m1/hardware/ra8m1_gpio.h b/arch/arm/src/ra8m1/hardware/ra8m1_gpio.h new file mode 100644 index 00000000000..3730cad4500 --- /dev/null +++ b/arch/arm/src/ra8m1/hardware/ra8m1_gpio.h @@ -0,0 +1,324 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/hardware/ra8m1_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_GPIO_H +#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/ra8m1_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define R_GPIO_PCNTR1_OFFSET 0x0000 /* Port Control Register 1 (32-bits) */ +#define R_GPIO_PDR_OFFSET 0x0000 /* Data direction register (16-bits) */ +#define R_GPIO_PODR_OFFSET 0x0002 /* Output data register (16-bits) */ +#define R_GPIO_PCNTR2_OFFSET 0x0004 /* Port Control Register 2 (32-bits) */ +#define R_GPIO_PIDR_OFFSET 0x0004 /* Input data register (16-bits) */ +#define R_GPIO_EIDR_OFFSET 0x0006 /* Port Event Input Data register (16-bits) */ +#define R_GPIO_PCNTR3_OFFSET 0x0008 /* Port Control Register 3 (32-bits) */ +#define R_GPIO_POSR_OFFSET 0x0008 /* Output set register (16-bits) */ +#define R_GPIO_PORR_OFFSET 0x000a /* Output reset register (16-bits) */ +#define R_GPIO_PCNTR4_OFFSET 0x000c /* Port Control Register 4 (32-bits) */ +#define R_GPIO_EOSR_OFFSET 0x000c /* Event output reset register (16-bits) */ +#define R_GPIO_EORR_OFFSET 0x000e /* Event output set register (16-bits) */ + +/* Register Addresses *******************************************************/ + +/* PORT0 Registers (subset: 9 of 12 registers) */ + +#define R_PORT0_PCNTR1 (R_PORT0_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORT0_PDR (R_PORT0_BASE + R_GPIO_PDR_OFFSET) +#define R_PORT0_PODR (R_PORT0_BASE + R_GPIO_PODR_OFFSET) +#define R_PORT0_PCNTR2 (R_PORT0_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORT0_PIDR (R_PORT0_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORT0_EIDR (R_PORT0_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORT0_PCNTR3 (R_PORT0_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORT0_POSR (R_PORT0_BASE + R_GPIO_POSR_OFFSET) +#define R_PORT0_PORR (R_PORT0_BASE + R_GPIO_PORR_OFFSET) + +/* PORT1 Registers */ + +#define R_PORT1_PCNTR1 (R_PORT1_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORT1_PDR (R_PORT1_BASE + R_GPIO_PDR_OFFSET) +#define R_PORT1_PODR (R_PORT1_BASE + R_GPIO_PODR_OFFSET) +#define R_PORT1_PCNTR2 (R_PORT1_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORT1_PIDR (R_PORT1_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORT1_EIDR (R_PORT1_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORT1_PCNTR3 (R_PORT1_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORT1_POSR (R_PORT1_BASE + R_GPIO_POSR_OFFSET) +#define R_PORT1_PORR (R_PORT1_BASE + R_GPIO_PORR_OFFSET) +#define R_PORT1_PCNTR4 (R_PORT1_BASE + R_GPIO_PCNTR4_OFFSET) +#define R_PORT1_EOSR (R_PORT1_BASE + R_GPIO_EOSR_OFFSET) +#define R_PORT1_EORR (R_PORT1_BASE + R_GPIO_EORR_OFFSET) + +/* PORT2 Registers */ + +#define R_PORT2_PCNTR1 (R_PORT2_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORT2_PDR (R_PORT2_BASE + R_GPIO_PDR_OFFSET) +#define R_PORT2_PODR (R_PORT2_BASE + R_GPIO_PODR_OFFSET) +#define R_PORT2_PCNTR2 (R_PORT2_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORT2_PIDR (R_PORT2_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORT2_EIDR (R_PORT2_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORT2_PCNTR3 (R_PORT2_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORT2_POSR (R_PORT2_BASE + R_GPIO_POSR_OFFSET) +#define R_PORT2_PORR (R_PORT2_BASE + R_GPIO_PORR_OFFSET) +#define R_PORT2_PCNTR4 (R_PORT2_BASE + R_GPIO_PCNTR4_OFFSET) +#define R_PORT2_EOSR (R_PORT2_BASE + R_GPIO_EOSR_OFFSET) +#define R_PORT2_EORR (R_PORT2_BASE + R_GPIO_EORR_OFFSET) + +/* PORT3 Registers */ + +#define R_PORT3_PCNTR1 (R_PORT3_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORT3_PDR (R_PORT3_BASE + R_GPIO_PDR_OFFSET) +#define R_PORT3_PODR (R_PORT3_BASE + R_GPIO_PODR_OFFSET) +#define R_PORT3_PCNTR2 (R_PORT3_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORT3_PIDR (R_PORT3_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORT3_EIDR (R_PORT3_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORT3_PCNTR3 (R_PORT3_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORT3_POSR (R_PORT3_BASE + R_GPIO_POSR_OFFSET) +#define R_PORT3_PORR (R_PORT3_BASE + R_GPIO_PORR_OFFSET) +#define R_PORT3_PCNTR4 (R_PORT3_BASE + R_GPIO_PCNTR4_OFFSET) +#define R_PORT3_EOSR (R_PORT3_BASE + R_GPIO_EOSR_OFFSET) +#define R_PORT3_EORR (R_PORT3_BASE + R_GPIO_EORR_OFFSET) + +/* PORT4 Registers */ + +#define R_PORT4_PCNTR1 (R_PORT4_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORT4_PDR (R_PORT4_BASE + R_GPIO_PDR_OFFSET) +#define R_PORT4_PODR (R_PORT4_BASE + R_GPIO_PODR_OFFSET) +#define R_PORT4_PCNTR2 (R_PORT4_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORT4_PIDR (R_PORT4_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORT4_EIDR (R_PORT4_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORT4_PCNTR3 (R_PORT4_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORT4_POSR (R_PORT4_BASE + R_GPIO_POSR_OFFSET) +#define R_PORT4_PORR (R_PORT4_BASE + R_GPIO_PORR_OFFSET) +#define R_PORT4_PCNTR4 (R_PORT4_BASE + R_GPIO_PCNTR4_OFFSET) +#define R_PORT4_EOSR (R_PORT4_BASE + R_GPIO_EOSR_OFFSET) +#define R_PORT4_EORR (R_PORT4_BASE + R_GPIO_EORR_OFFSET) + +/* PORT5 Registers (subset: 9 of 12 registers) */ + +#define R_PORT5_PCNTR1 (R_PORT5_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORT5_PDR (R_PORT5_BASE + R_GPIO_PDR_OFFSET) +#define R_PORT5_PODR (R_PORT5_BASE + R_GPIO_PODR_OFFSET) +#define R_PORT5_PCNTR2 (R_PORT5_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORT5_PIDR (R_PORT5_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORT5_EIDR (R_PORT5_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORT5_PCNTR3 (R_PORT5_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORT5_POSR (R_PORT5_BASE + R_GPIO_POSR_OFFSET) +#define R_PORT5_PORR (R_PORT5_BASE + R_GPIO_PORR_OFFSET) + +/* PORT6 Registers (subset: 9 of 12 registers) */ + +#define R_PORT6_PCNTR1 (R_PORT6_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORT6_PDR (R_PORT6_BASE + R_GPIO_PDR_OFFSET) +#define R_PORT6_PODR (R_PORT6_BASE + R_GPIO_PODR_OFFSET) +#define R_PORT6_PCNTR2 (R_PORT6_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORT6_PIDR (R_PORT6_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORT6_EIDR (R_PORT6_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORT6_PCNTR3 (R_PORT6_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORT6_POSR (R_PORT6_BASE + R_GPIO_POSR_OFFSET) +#define R_PORT6_PORR (R_PORT6_BASE + R_GPIO_PORR_OFFSET) + +/* PORT7 Registers (subset: 9 of 12 registers) */ + +#define R_PORT7_PCNTR1 (R_PORT7_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORT7_PDR (R_PORT7_BASE + R_GPIO_PDR_OFFSET) +#define R_PORT7_PODR (R_PORT7_BASE + R_GPIO_PODR_OFFSET) +#define R_PORT7_PCNTR2 (R_PORT7_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORT7_PIDR (R_PORT7_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORT7_EIDR (R_PORT7_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORT7_PCNTR3 (R_PORT7_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORT7_POSR (R_PORT7_BASE + R_GPIO_POSR_OFFSET) +#define R_PORT7_PORR (R_PORT7_BASE + R_GPIO_PORR_OFFSET) + +/* PORT8 Registers (subset: 9 of 12 registers) */ + +#define R_PORT8_PCNTR1 (R_PORT8_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORT8_PDR (R_PORT8_BASE + R_GPIO_PDR_OFFSET) +#define R_PORT8_PODR (R_PORT8_BASE + R_GPIO_PODR_OFFSET) +#define R_PORT8_PCNTR2 (R_PORT8_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORT8_PIDR (R_PORT8_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORT8_EIDR (R_PORT8_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORT8_PCNTR3 (R_PORT8_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORT8_POSR (R_PORT8_BASE + R_GPIO_POSR_OFFSET) +#define R_PORT8_PORR (R_PORT8_BASE + R_GPIO_PORR_OFFSET) + +/* PORT9 Registers (subset: 9 of 12 registers) */ + +#define R_PORT9_PCNTR1 (R_PORT9_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORT9_PDR (R_PORT9_BASE + R_GPIO_PDR_OFFSET) +#define R_PORT9_PODR (R_PORT9_BASE + R_GPIO_PODR_OFFSET) +#define R_PORT9_PCNTR2 (R_PORT9_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORT9_PIDR (R_PORT9_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORT9_EIDR (R_PORT9_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORT9_PCNTR3 (R_PORT9_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORT9_POSR (R_PORT9_BASE + R_GPIO_POSR_OFFSET) +#define R_PORT9_PORR (R_PORT9_BASE + R_GPIO_PORR_OFFSET) + +/* PORTA Registers (subset: 9 of 12 registers) */ + +#define R_PORTA_PCNTR1 (R_PORTA_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORTA_PDR (R_PORTA_BASE + R_GPIO_PDR_OFFSET) +#define R_PORTA_PODR (R_PORTA_BASE + R_GPIO_PODR_OFFSET) +#define R_PORTA_PCNTR2 (R_PORTA_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORTA_PIDR (R_PORTA_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORTA_EIDR (R_PORTA_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORTA_PCNTR3 (R_PORTA_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORTA_POSR (R_PORTA_BASE + R_GPIO_POSR_OFFSET) +#define R_PORTA_PORR (R_PORTA_BASE + R_GPIO_PORR_OFFSET) + +/* PORTB Registers (subset: 9 of 12 registers) */ + +#define R_PORTB_PCNTR1 (R_PORTB_BASE + R_GPIO_PCNTR1_OFFSET) +#define R_PORTB_PDR (R_PORTB_BASE + R_GPIO_PDR_OFFSET) +#define R_PORTB_PODR (R_PORTB_BASE + R_GPIO_PODR_OFFSET) +#define R_PORTB_PCNTR2 (R_PORTB_BASE + R_GPIO_PCNTR2_OFFSET) +#define R_PORTB_PIDR (R_PORTB_BASE + R_GPIO_PIDR_OFFSET) +#define R_PORTB_EIDR (R_PORTB_BASE + R_GPIO_EIDR_OFFSET) +#define R_PORTB_PCNTR3 (R_PORTB_BASE + R_GPIO_PCNTR3_OFFSET) +#define R_PORTB_POSR (R_PORTB_BASE + R_GPIO_POSR_OFFSET) +#define R_PORTB_PORR (R_PORTB_BASE + R_GPIO_PORR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Port Control Register 1 (32-bits) ****************************************/ + +#define R_GPIO_PCNTR1_PDR_SHIFT (0) +#define R_GPIO_PCNTR1_PDR_MASK (0xffff) +# define R_GPIO_PCNTR1_PDR_V0 (0 << R_GPIO_PCNTR1_PDR_SHIFT) /* Input (functions as an input pin) */ +# define R_GPIO_PCNTR1_PDR_V1 (1 << R_GPIO_PCNTR1_PDR_SHIFT) /* Output (functions as an output pin). */ +#define R_GPIO_PCNTR1_PODR_SHIFT (16) +#define R_GPIO_PCNTR1_PODR_MASK (0xffff) +# define R_GPIO_PCNTR1_PODR_LOW_OUTPUT (0 << R_GPIO_PCNTR1_PODR_SHIFT) /* Low output */ +# define R_GPIO_PCNTR1_PODR_HIGH_OUTPUT (1 << R_GPIO_PCNTR1_PODR_SHIFT) /* High output. */ + +/* Data direction register (16-bits) ****************************************/ + +#define R_GPIO_PDR_PDR_SHIFT (0) +#define R_GPIO_PDR_PDR_MASK (0xffff) +# define R_GPIO_PDR_PDR_V0 (0 << R_GPIO_PDR_PDR_SHIFT) /* Input (functions as an input pin) */ +# define R_GPIO_PDR_PDR_V1 (1 << R_GPIO_PDR_PDR_SHIFT) /* Output (functions as an output pin). */ + +/* Output data register (16-bits) *******************************************/ + +#define R_GPIO_PODR_PODR_SHIFT (0) +#define R_GPIO_PODR_PODR_MASK (0xffff) +# define R_GPIO_PODR_PODR_LOW_OUTPUT (0 << R_GPIO_PODR_PODR_SHIFT) /* Low output */ +# define R_GPIO_PODR_PODR_HIGH_OUTPUT (1 << R_GPIO_PODR_PODR_SHIFT) /* High output. */ + +/* Port Control Register 2 (32-bits) ****************************************/ + +#define R_GPIO_PCNTR2_PIDR_SHIFT (0) +#define R_GPIO_PCNTR2_PIDR_MASK (0xffff) +# define R_GPIO_PCNTR2_PIDR_LOW_INPUT (0 << R_GPIO_PCNTR2_PIDR_SHIFT) /* Low input */ +# define R_GPIO_PCNTR2_PIDR_HIGH_INPUT (1 << R_GPIO_PCNTR2_PIDR_SHIFT) /* High input. */ +#define R_GPIO_PCNTR2_EIDR_SHIFT (16) +#define R_GPIO_PCNTR2_EIDR_MASK (0xffff) +# define R_GPIO_PCNTR2_EIDR_LOW_INPUT (0 << R_GPIO_PCNTR2_EIDR_SHIFT) /* Low input */ +# define R_GPIO_PCNTR2_EIDR_HIGH_INPUT (1 << R_GPIO_PCNTR2_EIDR_SHIFT) /* High input. */ + +/* Input data register (16-bits) ********************************************/ + +#define R_GPIO_PIDR_PIDR_SHIFT (0) +#define R_GPIO_PIDR_PIDR_MASK (0xffff) +# define R_GPIO_PIDR_PIDR_LOW_LEVEL (0 << R_GPIO_PIDR_PIDR_SHIFT) /* Low level */ +# define R_GPIO_PIDR_PIDR_HIGH_LEVEL (1 << R_GPIO_PIDR_PIDR_SHIFT) /* high level. */ + +/* Port Event Input Data register (16-bits) *********************************/ + +#define R_GPIO_EIDR_EIDR_SHIFT (0) +#define R_GPIO_EIDR_EIDR_MASK (0xffff) +# define R_GPIO_EIDR_EIDR_LOW_INPUT (0 << R_GPIO_EIDR_EIDR_SHIFT) /* Low input */ +# define R_GPIO_EIDR_EIDR_HIGH_INPUT (1 << R_GPIO_EIDR_EIDR_SHIFT) /* High input. */ + +/* Port Control Register 3 (32-bits) ****************************************/ + +#define R_GPIO_PCNTR3_POSR_SHIFT (0) +#define R_GPIO_PCNTR3_POSR_MASK (0xffff) +# define R_GPIO_PCNTR3_POSR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_PCNTR3_POSR_SHIFT) /* No affect to output */ +# define R_GPIO_PCNTR3_POSR_HIGH_OUTPUT (1 << R_GPIO_PCNTR3_POSR_SHIFT) /* High output. */ +#define R_GPIO_PCNTR3_PORR_SHIFT (16) +#define R_GPIO_PCNTR3_PORR_MASK (0xffff) +# define R_GPIO_PCNTR3_PORR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_PCNTR3_PORR_SHIFT) /* No affect to output */ +# define R_GPIO_PCNTR3_PORR_LOW_OUTPUT (1 << R_GPIO_PCNTR3_PORR_SHIFT) /* Low output. */ + +/* Output set register (16-bits) ********************************************/ + +#define R_GPIO_POSR_POSR_SHIFT (0) +#define R_GPIO_POSR_POSR_MASK (0xffff) +# define R_GPIO_POSR_POSR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_POSR_POSR_SHIFT) /* No affect to output */ +# define R_GPIO_POSR_POSR_HIGH_OUTPUT (1 << R_GPIO_POSR_POSR_SHIFT) /* High output. */ + +/* Output reset register (16-bits) ******************************************/ + +#define R_GPIO_PORR_PORR_SHIFT (0) +#define R_GPIO_PORR_PORR_MASK (0xffff) +# define R_GPIO_PORR_PORR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_PORR_PORR_SHIFT) /* No affect to output */ +# define R_GPIO_PORR_PORR_LOW_OUTPUT (1 << R_GPIO_PORR_PORR_SHIFT) /* Low output. */ + +/* Port Control Register 4 (32-bits) ****************************************/ + +#define R_GPIO_PCNTR4_EOSR_SHIFT (0) +#define R_GPIO_PCNTR4_EOSR_MASK (0xffff) +# define R_GPIO_PCNTR4_EOSR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_PCNTR4_EOSR_SHIFT) /* No affect to output */ +# define R_GPIO_PCNTR4_EOSR_HIGH_OUTPUT (1 << R_GPIO_PCNTR4_EOSR_SHIFT) /* High output. */ +#define R_GPIO_PCNTR4_EORR_SHIFT (16) +#define R_GPIO_PCNTR4_EORR_MASK (0xffff) +# define R_GPIO_PCNTR4_EORR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_PCNTR4_EORR_SHIFT) /* No affect to output */ +# define R_GPIO_PCNTR4_EORR_LOW_OUTPUT (1 << R_GPIO_PCNTR4_EORR_SHIFT) /* Low output */ + +/* Event output reset register (16-bits) ************************************/ + +#define R_GPIO_EOSR_EOSR_SHIFT (0) +#define R_GPIO_EOSR_EOSR_MASK (0xffff) +# define R_GPIO_EOSR_EOSR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_EOSR_EOSR_SHIFT) /* No affect to output */ +# define R_GPIO_EOSR_EOSR_HIGH_OUTPUT (1 << R_GPIO_EOSR_EOSR_SHIFT) /* High output. */ + +/* Event output set register (16-bits) **************************************/ + +#define R_GPIO_EORR_EORR_SHIFT (0) +#define R_GPIO_EORR_EORR_MASK (0xffff) +# define R_GPIO_EORR_EORR_NO_AFFECT_TO_OUTPUT (0 << R_GPIO_EORR_EORR_SHIFT) /* No affect to output */ +# define R_GPIO_EORR_EORR_LOW_OUTPUT (1 << R_GPIO_EORR_EORR_SHIFT) /* Low output */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_GPIO_H */ diff --git a/arch/arm/src/ra8m1/hardware/ra8m1_icu.h b/arch/arm/src/ra8m1/hardware/ra8m1_icu.h new file mode 100644 index 00000000000..a3c7b80610d --- /dev/null +++ b/arch/arm/src/ra8m1/hardware/ra8m1_icu.h @@ -0,0 +1,218 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/hardware/ra8m1_icu.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ICU_H +#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ICU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/ra8m1_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define R_ICU_IRQCR_OFFSET 0x0000 /* IRQ Control Register %s (8-bits) */ +#define R_ICU_NMICR_OFFSET 0x0010 /* NMI Pin Interrupt Control Register (8-bits) */ +#define R_ICU_SWIRQ_S_OFFSET 0x6010 /* Software Interrupt Request Register for Secure Interrupt (8-bits) */ +#define R_ICU_SWIRQ_NS_OFFSET 0x6020 /* Software Interrupt Request Register for Non-secure Interrupt (8-bits) */ +#define R_ICU_IENMIER_OFFSET 0x6060 /* Integrated Error NMI Interrupt Enable Register for CPU (16-bits) */ +#define R_ICU_NMIER_OFFSET 0x6100 /* Non-Maskable Interrupt Enable Register (16-bits) */ +#define R_ICU_NMICLR_OFFSET 0x6110 /* Non-Maskable Interrupt Status Clear Register (16-bits) */ +#define R_ICU_NMISR_OFFSET 0x6120 /* Non-Maskable Interrupt Status Register (16-bits) */ +#define R_ICU_WUPEN0_OFFSET 0x61a0 /* Wake Up Interrupt Enable Register 0 (32-bits) */ +#define R_ICU_WUPEN1_OFFSET 0x61a4 /* Wake Up Interrupt Enable Register 1 (32-bits) */ +#define R_ICU_SELSR0_OFFSET 0x6200 /* SYS Event Link Setting Register (16-bits) */ +#define R_ICU_IELSR_OFFSET 0x6300 /* ICU Event Link Setting Register %s (32-bits) */ + +/* Register Addresses *******************************************************/ + +/* ICU Registers */ + +#define R_ICU_IRQCR(p) (R_ICU_BASE + R_ICU_IRQCR_OFFSET + (p)*0x0001) +#define R_ICU_NMICR (R_ICU_BASE + R_ICU_NMICR_OFFSET) +#define R_ICU_SWIRQ_S (R_ICU_BASE + R_ICU_SWIRQ_S_OFFSET) +#define R_ICU_SWIRQ_NS (R_ICU_BASE + R_ICU_SWIRQ_NS_OFFSET) +#define R_ICU_IENMIER (R_ICU_BASE + R_ICU_IENMIER_OFFSET) +#define R_ICU_NMIER (R_ICU_BASE + R_ICU_NMIER_OFFSET) +#define R_ICU_NMICLR (R_ICU_BASE + R_ICU_NMICLR_OFFSET) +#define R_ICU_NMISR (R_ICU_BASE + R_ICU_NMISR_OFFSET) +#define R_ICU_WUPEN0 (R_ICU_BASE + R_ICU_WUPEN0_OFFSET) +#define R_ICU_WUPEN1 (R_ICU_BASE + R_ICU_WUPEN1_OFFSET) +#define R_ICU_SELSR0 (R_ICU_BASE + R_ICU_SELSR0_OFFSET) +#define R_ICU_IELSR(p) (R_ICU_BASE + R_ICU_IELSR_OFFSET + (p)*0x0004) + +/* Register Bitfield Definitions ********************************************/ + +/* IRQ Control Register %s (8-bits) *****************************************/ + +#define R_ICU_IRQCR_SIZE 16 +#define R_ICU_IRQCR_IRQMD_SHIFT (0) +#define R_ICU_IRQCR_IRQMD_MASK (0x3) +# define R_ICU_IRQCR_IRQMD_FALLING_EDGE (0 << R_ICU_IRQCR_IRQMD_SHIFT) /* Falling edge */ +# define R_ICU_IRQCR_IRQMD_RISING_EDGE (1 << R_ICU_IRQCR_IRQMD_SHIFT) /* Rising edge */ +# define R_ICU_IRQCR_IRQMD_RISING_AND_FALLING_EDGES (2 << R_ICU_IRQCR_IRQMD_SHIFT) /* Rising and falling edges */ +# define R_ICU_IRQCR_IRQMD_LOW_LEVEL (3 << R_ICU_IRQCR_IRQMD_SHIFT) /* Low level */ +#define R_ICU_IRQCR_FCLKSEL_SHIFT (4) +#define R_ICU_IRQCR_FCLKSEL_MASK (0x3) +# define R_ICU_IRQCR_FCLKSEL_PCLKB (0 << R_ICU_IRQCR_FCLKSEL_SHIFT) /* PCLKB */ +# define R_ICU_IRQCR_FCLKSEL_PCLKB_8 (1 << R_ICU_IRQCR_FCLKSEL_SHIFT) /* PCLKB/8 */ +# define R_ICU_IRQCR_FCLKSEL_PCLKB_32 (2 << R_ICU_IRQCR_FCLKSEL_SHIFT) /* PCLKB/32 */ +# define R_ICU_IRQCR_FCLKSEL_PCLKB_64 (3 << R_ICU_IRQCR_FCLKSEL_SHIFT) /* PCLKB/64 */ +#define R_ICU_IRQCR_FLTEN (1 << 7) /* 80: IRQ Digital Filter Enable */ + +/* NMI Pin Interrupt Control Register (8-bits) ******************************/ + +#define R_ICU_NMICR_NMIMD (1 << 0) /* 01: NMI Detection Set */ +#define R_ICU_NMICR_NFCLKSEL_SHIFT (4) +#define R_ICU_NMICR_NFCLKSEL_MASK (0x3) +# define R_ICU_NMICR_NFCLKSEL_PCLKB (0 << R_ICU_NMICR_NFCLKSEL_SHIFT) /* PCLKB */ +# define R_ICU_NMICR_NFCLKSEL_PCLKB_8 (1 << R_ICU_NMICR_NFCLKSEL_SHIFT) /* PCLKB/8 */ +# define R_ICU_NMICR_NFCLKSEL_PCLKB_32 (2 << R_ICU_NMICR_NFCLKSEL_SHIFT) /* PCLKB/32 */ +# define R_ICU_NMICR_NFCLKSEL_PCLKB_64 (3 << R_ICU_NMICR_NFCLKSEL_SHIFT) /* PCLKB/64 */ +#define R_ICU_NMICR_NFLTEN (1 << 7) /* 80: NMI Digital Filter Enable */ + +/* Software Interrupt Request Register for Secure Interrupt (8-bits) ********/ + +#define R_ICU_SWIRQ_S_SWIRQS (1 << 0) /* 01: Generates an interrupt for the other CPU subsystem. */ + +/* Software Interrupt Request Register for Non-secure Interrupt (8-bits) ****/ + +#define R_ICU_SWIRQ_NS_SWIRQNS (1 << 0) /* 01: Generates an interrupt for the other CPU subsystem. */ + +/* Integrated Error NMI Interrupt Enable Register for CPU (16-bits) *********/ + +#define R_ICU_IENMIER_CMEN (1 << 0) /* 01: Integrated Common Memory error nmi Enable */ +#define R_ICU_IENMIER_LMEN (1 << 1) /* 02: Integrated Local Memory error nmi Enable */ +#define R_ICU_IENMIER_BUSEN (1 << 2) /* 04: Integrated BUS error nmi Enable */ + +/* Non-Maskable Interrupt Enable Register (16-bits) *************************/ + +#define R_ICU_NMIER_IWDTEN (1 << 0) /* 01: IWDT Underflow/Refresh Error Interrupt Enable */ +#define R_ICU_NMIER_WDTEN (1 << 1) /* 02: WDT Underflow/Refresh Error Interrupt Enable */ +#define R_ICU_NMIER_PVD1EN (1 << 2) /* 04: Voltage-Monitoring 1 Interrupt Enable */ +#define R_ICU_NMIER_PVD2EN (1 << 3) /* 08: Voltage-Monitoring 2 Interrupt Enable */ +#define R_ICU_NMIER_OSTEN (1 << 6) /* 40: Oscillation Stop Detection Interrupt Enable */ +#define R_ICU_NMIER_NMIEN (1 << 7) /* 80: NMI Pin Interrupt Enable */ +#define R_ICU_NMIER_BUSEN (1 << 12) /* 1000: BUS error Interrupt Enable */ +#define R_ICU_NMIER_CMEN (1 << 13) /* 2000: Common Memory error Interrupt Enable */ +#define R_ICU_NMIER_LUEN (1 << 15) /* 8000: LockUp Interrupt Enable */ + +/* Non-Maskable Interrupt Status Clear Register (16-bits) *******************/ + +#define R_ICU_NMICLR_IWDTCLR (1 << 0) /* 01: IWDT Clear */ +#define R_ICU_NMICLR_WDTCLR (1 << 1) /* 02: WDT Clear */ +#define R_ICU_NMICLR_PVD1CLR (1 << 2) /* 04: PVD1 Clear */ +#define R_ICU_NMICLR_PVD2CLR (1 << 3) /* 08: PVD2 Clear */ +#define R_ICU_NMICLR_OSTCLR (1 << 6) /* 40: OST Clear */ +#define R_ICU_NMICLR_NMICLR (1 << 7) /* 80: NMI Clear */ +#define R_ICU_NMICLR_BUSCLR (1 << 12) /* 1000: Bus Clear */ +#define R_ICU_NMICLR_CMCLR (1 << 13) /* 2000: CM Clear */ +#define R_ICU_NMICLR_LUCLR (1 << 15) /* 8000: LU Clear */ + +/* Non-Maskable Interrupt Status Register (16-bits) *************************/ + +#define R_ICU_NMISR_IWDTST (1 << 0) /* 01: IWDT Underflow/Refresh Error Status Flag */ +#define R_ICU_NMISR_WDTST (1 << 1) /* 02: WDT Underflow/Refresh Error Status Flag */ +#define R_ICU_NMISR_PVD1ST (1 << 2) /* 04: Voltage-Monitoring 1 Interrupt Status Flag */ +#define R_ICU_NMISR_PVD2ST (1 << 3) /* 08: Voltage-Monitoring 2 Interrupt Status Flag */ +#define R_ICU_NMISR_OSTST (1 << 6) /* 40: Oscillation Stop Detection Interrupt Status Flag */ +#define R_ICU_NMISR_NMIST (1 << 7) /* 80: NMI Status Flag */ +#define R_ICU_NMISR_BUSST (1 << 12) /* 1000: BUS error Interrupt Status Flag */ +#define R_ICU_NMISR_CMST (1 << 13) /* 2000: Common Memory error Interrupt Status Flag */ +#define R_ICU_NMISR_LUST (1 << 15) /* 8000: LockUp Interrupt Status Flag */ + +/* Wake Up Interrupt Enable Register 0 (32-bits) ****************************/ + +#define R_ICU_WUPEN0_IRQWUPEN0 (1 << 0) /* 01: IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN1 (1 << 1) /* 02: IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN2 (1 << 2) /* 04: IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN3 (1 << 3) /* 08: IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN4 (1 << 4) /* 10: IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN5 (1 << 5) /* 20: IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN6 (1 << 6) /* 40: IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN7 (1 << 7) /* 80: IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN8 (1 << 8) /* 100: IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN9 (1 << 9) /* 200: IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN10 (1 << 10) /* 400: IRQ10 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN11 (1 << 11) /* 800: IRQ11 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN12 (1 << 12) /* 1000: IRQ12 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN13 (1 << 13) /* 2000: IRQ13 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN14 (1 << 14) /* 4000: IRQ14 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IRQWUPEN15 (1 << 15) /* 8000: IRQ15 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_IWDTWUPEN (1 << 16) /* 10000: IWDT Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_PVD1WUPEN (1 << 18) /* 40000: PVD1 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_PVD2WUPEN (1 << 19) /* 80000: PVD2 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_VBATTWUPEN (1 << 20) /* 100000: VBATT Monitor Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_RTCALMWUPEN (1 << 24) /* 1000000: RTC Alarm Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_RTCPRDWUPEN (1 << 25) /* 2000000: RCT Period Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_USBHSWUPEN (1 << 26) /* 4000000: USBHS Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_USBFSWUPEN (1 << 27) /* 8000000: USBFS0 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_AGT1UDWUPEN (1 << 28) /* 10000000: AGT1 Underflow Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_AGT1CAWUPEN (1 << 29) /* 20000000: AGT1 Compare Match A Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_AGT1CBWUPEN (1 << 30) /* 40000000: AGT1 Compare Match B Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN0_RIIC0WUPEN (1 << 31) /* 80000000: RIIC0 Address Match Interrupt Deep Sleep/Software Standby Returns Enable bit */ + +/* Wake Up Interrupt Enable Register 1 (32-bits) ****************************/ + +#define R_ICU_WUPEN1_COMPHS0WUPEN (1 << 3) /* 08: Comparator-HS0 Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN1_ULP0UWUPEN (1 << 8) /* 100: ULPT0 Underflow Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN1_ULP0AWUPEN (1 << 9) /* 200: ULPT0 Compare Match A Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN1_ULP0BWUPEN (1 << 10) /* 400: ULPT0 Compare Match B Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN1_I3CWUPEN (1 << 11) /* 800: I3C Wakeup Condition Detection Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN1_ULP1UWUPEN (1 << 12) /* 1000: ULPT1 Underflow Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN1_ULP1AWUPEN (1 << 13) /* 2000: ULPT1 Compare Match A Interrupt Deep Sleep/Software Standby Returns Enable bit */ +#define R_ICU_WUPEN1_ULP1BWUPEN (1 << 14) /* 4000: ULPT1 Compare Match B Interrupt Deep Sleep/Software Standby Returns Enable bit */ + +/* SYS Event Link Setting Register (16-bits) ********************************/ + +#define R_ICU_SELSR0_SELS_SHIFT (0) +#define R_ICU_SELSR0_SELS_MASK (0x1ff) +# define R_ICU_SELSR0_SELS_V000000000 (0 << R_ICU_SELSR0_SELS_SHIFT) /* Disable event output to the associated low-power mode module */ + +/* ICU Event Link Setting Register %s (32-bits) *****************************/ + +#define R_ICU_IELSR_SIZE 96 +#define R_ICU_IELSR_IELS_SHIFT (0) +#define R_ICU_IELSR_IELS_MASK (0x1ff) +# define R_ICU_IELSR_IELS_NOTHING_IS_SELECTED (0 << R_ICU_IELSR_IELS_SHIFT) /* Nothing is selected */ +#define R_ICU_IELSR_IR (1 << 16) /* 10000: Interrupt Status Flag */ +#define R_ICU_IELSR_DTCE (1 << 24) /* 1000000: DTC Activation Enable */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_ICU_H */ diff --git a/arch/arm/src/ra8m1/hardware/ra8m1_memorymap.h b/arch/arm/src/ra8m1/hardware/ra8m1_memorymap.h new file mode 100644 index 00000000000..604c075c1f2 --- /dev/null +++ b/arch/arm/src/ra8m1/hardware/ra8m1_memorymap.h @@ -0,0 +1,208 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/hardware/ra8m1_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MEMORYMAP_H +#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Registers Base Addresses */ + +#define R_ACMPHS0_BASE 0x40236000UL +#define R_ACMPHS1_BASE 0x40236100UL +#define R_ACMPHS2_BASE 0x40236200UL +#define R_ACMPHS3_BASE 0x40236300UL +#define R_ACMPHS4_BASE 0x40236400UL +#define R_ACMPHS5_BASE 0x40236500UL +#define R_ADC0_BASE 0x40332000UL +#define R_ADC1_BASE 0x40332200UL +#define R_AGTX0_BASE 0x40221000UL +#define R_AGTX1_BASE 0x40221100UL +#define R_AGTX2_BASE 0x40221200UL +#define R_AGTX3_BASE 0x40221300UL +#define R_AGTX4_BASE 0x40221400UL +#define R_AGTX5_BASE 0x40221500UL +#define R_AGTX6_BASE 0x40221600UL +#define R_AGTX7_BASE 0x40221700UL +#define R_AGTX8_BASE 0x40221800UL +#define R_AGTX9_BASE 0x40221900UL +#define R_BUS_BASE 0x40003000UL +#define R_CAC_BASE 0x40202400UL +#define R_CANFD1_BASE 0x40382000UL +#define R_CANFD_BASE 0x40380000UL +#define R_CEU_BASE 0x40348000UL +#define R_CPSCU_BASE 0x40008000UL +#define R_CRC_BASE 0x40310000UL +#define R_DAC_BASE 0x40333000UL +#define R_DEBUG_BASE 0x4001B000UL +#define R_DEBUG_OCD_BASE 0x40011000UL +#define R_DMAC0_BASE 0x4000A000UL +#define R_DMAC1_BASE 0x4000A040UL +#define R_DMAC2_BASE 0x4000A080UL +#define R_DMAC3_BASE 0x4000A0C0UL +#define R_DMAC4_BASE 0x4000A100UL +#define R_DMAC5_BASE 0x4000A140UL +#define R_DMAC6_BASE 0x4000A180UL +#define R_DMAC7_BASE 0x4000A1C0UL +#define R_DMA_BASE 0x4000A800UL +#define R_DOC_BASE 0x40311000UL +#define R_DOC_B_BASE 0x40311000UL +#define R_DOTF1_BASE 0x40268900UL +#define R_DOTF_BASE 0x40268800UL +#define R_DTC_BASE 0x4000AC00UL +#define R_ECCMB0_BASE 0x4036F200UL +#define R_ECCMB1_BASE 0x4036F300UL +#define R_ELC_BASE 0x40201000UL +#define R_ETHERC0_BASE 0x40354100UL +#define R_ETHERC_EDMAC_BASE 0x40354000UL +#define R_FACI_HP_BASE 0x4011E000UL +#define R_FACI_HP_CMD_BASE 0x40100000UL +#define R_FCACHE_BASE 0x4001C100UL +#define R_FLAD_BASE 0x4011C000UL +#define R_GPT0_BASE 0x40322000UL +#define R_GPT10_BASE 0x40322A00UL +#define R_GPT11_BASE 0x40322B00UL +#define R_GPT12_BASE 0x40322C00UL +#define R_GPT13_BASE 0x40322D00UL +#define R_GPT1_BASE 0x40322100UL +#define R_GPT2_BASE 0x40322200UL +#define R_GPT3_BASE 0x40322300UL +#define R_GPT4_BASE 0x40322400UL +#define R_GPT5_BASE 0x40322500UL +#define R_GPT6_BASE 0x40322600UL +#define R_GPT7_BASE 0x40322700UL +#define R_GPT8_BASE 0x40322800UL +#define R_GPT9_BASE 0x40322900UL +#define R_GPT_OPS_BASE 0x40323F00UL +#define R_GPT_POEG0_BASE 0x40212000UL +#define R_GPT_POEG1_BASE 0x40212100UL +#define R_GPT_POEG2_BASE 0x40212200UL +#define R_GPT_POEG3_BASE 0x40212300UL +#define R_I3C0_BASE 0x4035F000UL +#define R_I3C1_BASE 0x4035F100UL +#define R_ICU_BASE 0x40006000UL +#define R_IIC0_BASE 0x4025E000UL +#define R_IIC1_BASE 0x4025E100UL +#define R_IIC2_BASE 0x4025E200UL +#define R_IWDT_BASE 0x40202200UL +#define R_MPU_MMPU_BASE 0x40000000UL +#define R_MPU_SPMON_BASE 0x40000D00UL +#define R_MSTP_BASE 0x40203000UL +#define R_OFS_DATAFLASH_BASE 0x27030000UL +#define R_PFS_BASE 0x40400800UL +#define R_PMISC_BASE 0x40400D00UL +#define R_PORT0_BASE 0x40400000UL +#define R_PORT10_BASE 0x40400140UL +#define R_PORT11_BASE 0x40400160UL +#define R_PORT12_BASE 0x40400180UL +#define R_PORT13_BASE 0x404001A0UL +#define R_PORT14_BASE 0x404001C0UL +#define R_PORT1_BASE 0x40400020UL +#define R_PORT2_BASE 0x40400040UL +#define R_PORT3_BASE 0x40400060UL +#define R_PORT4_BASE 0x40400080UL +#define R_PORT5_BASE 0x404000A0UL +#define R_PORT6_BASE 0x404000C0UL +#define R_PORT7_BASE 0x404000E0UL +#define R_PORT8_BASE 0x40400100UL +#define R_PORT9_BASE 0x40400120UL +#define R_PSCU_BASE 0x40204000UL +#define R_RTC_BASE 0x40202000UL +#define R_SCI0_BASE 0x40358000UL +#define R_SCI1_BASE 0x40358100UL +#define R_SCI2_BASE 0x40358200UL +#define R_SCI3_BASE 0x40358300UL +#define R_SCI4_BASE 0x40358400UL +#define R_SCI5_BASE 0x40358500UL +#define R_SCI6_BASE 0x40358600UL +#define R_SCI7_BASE 0x40358700UL +#define R_SCI8_BASE 0x40358800UL +#define R_SCI9_BASE 0x40358900UL +#define R_SCI_B0_BASE 0x40358000UL +#define R_SCI_B1_BASE 0x40358100UL +#define R_SCI_B2_BASE 0x40358200UL +#define R_SCI_B3_BASE 0x40358300UL +#define R_SCI_B4_BASE 0x40358400UL +#define R_SCI_B5_BASE 0x40358500UL +#define R_SCI_B6_BASE 0x40358600UL +#define R_SCI_B7_BASE 0x40358700UL +#define R_SCI_B8_BASE 0x40358800UL +#define R_SCI_B9_BASE 0x40358900UL +#define R_SDHI0_BASE 0x40252000UL +#define R_SDHI1_BASE 0x40252400UL +#define R_SPI0_BASE 0x4035C000UL +#define R_SPI1_BASE 0x4035C100UL +#define R_SPI2_BASE 0x40072200UL +#define R_SPI_B0_BASE 0x4035C000UL +#define R_SPI_B1_BASE 0x4035C100UL +#define R_SRAM_BASE 0x40002000UL +#define R_SSI0_BASE 0x4025D000UL +#define R_SSI1_BASE 0x4025D100UL +#define R_SYSTEM_BASE 0x4001E000UL +#define R_TSN_CAL_BASE 0x4011B17CUL +#define R_TSN_CTRL_BASE 0x40235000UL +#define R_ULPT0_BASE 0x40220000UL +#define R_ULPT1_BASE 0x40220100UL +#define R_USB_FS0_BASE 0x40250000UL +#define R_USB_HS0_BASE 0x40351000UL +#define R_WDT1_BASE 0x40044300UL +#define R_WDT_BASE 0x40202600UL +#define R_XSPI0_BASE 0x40268000UL +#define R_XSPI1_BASE 0x40268400UL + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MEMORYMAP_H */ diff --git a/arch/arm/src/ra8m1/hardware/ra8m1_mstp.h b/arch/arm/src/ra8m1/hardware/ra8m1_mstp.h new file mode 100644 index 00000000000..b956941b3c6 --- /dev/null +++ b/arch/arm/src/ra8m1/hardware/ra8m1_mstp.h @@ -0,0 +1,146 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/hardware/ra8m1_mstp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MSTP_H +#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MSTP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/ra8m1_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define R_MSTP_MSTPCRA_OFFSET 0x0000 /* Module Stop Control Register A (32-bits) */ +#define R_MSTP_MSTPCRB_OFFSET 0x0004 /* Module Stop Control Register B (32-bits) */ +#define R_MSTP_MSTPCRC_OFFSET 0x0008 /* Module Stop Control Register C (32-bits) */ +#define R_MSTP_MSTPCRD_OFFSET 0x000c /* Module Stop Control Register D (32-bits) */ +#define R_MSTP_MSTPCRE_OFFSET 0x0010 /* Module Stop Control Register E (32-bits) */ + +/* Register Addresses *******************************************************/ + +/* MSTP Registers */ + +#define R_MSTP_MSTPCRA (R_MSTP_BASE + R_MSTP_MSTPCRA_OFFSET) +#define R_MSTP_MSTPCRB (R_MSTP_BASE + R_MSTP_MSTPCRB_OFFSET) +#define R_MSTP_MSTPCRC (R_MSTP_BASE + R_MSTP_MSTPCRC_OFFSET) +#define R_MSTP_MSTPCRD (R_MSTP_BASE + R_MSTP_MSTPCRD_OFFSET) +#define R_MSTP_MSTPCRE (R_MSTP_BASE + R_MSTP_MSTPCRE_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Module Stop Control Register A (32-bits) *********************************/ + +#define R_MSTP_MSTPCRA_MSTPA0 (1 << 0) /* 01: SRAM0 Module Stop */ +#define R_MSTP_MSTPCRA_MSTPA1 (1 << 1) /* 02: SRAM1 Module Stop */ +#define R_MSTP_MSTPCRA_MSTPA15 (1 << 15) /* 8000: Standby SRAM Module Module Stop */ +#define R_MSTP_MSTPCRA_MSTPA22 (1 << 22) /* 400000: DMA Controller/Data Transfer Controller unit0 Module Stop */ + +/* Module Stop Control Register B (32-bits) *********************************/ + +#define R_MSTP_MSTPCRB_MSTPB4 (1 << 4) /* 10: I3C Bus Interface Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB8 (1 << 8) /* 100: I2C Bus Interface 1 Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB9 (1 << 9) /* 200: I2C Bus Interface 0 Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB11 (1 << 11) /* 800: Universal Serial Bus 2.0 FS0 Interface Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB12 (1 << 12) /* 1000: Universal Serial Bus 2.0 HS Interface Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB15 (1 << 15) /* 8000: ETHERC0 and EDMAC0 Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB16 (1 << 16) /* 10000: Octa Memory Controller Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB18 (1 << 18) /* 40000: Serial Peripheral Interface 1 Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB19 (1 << 19) /* 80000: Serial Peripheral Interface 0 Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB22 (1 << 22) /* 400000: Serial Communication Interface 9 Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB27 (1 << 27) /* 8000000: Serial Communication Interface 4 Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB28 (1 << 28) /* 10000000: Serial Communication Interface 3 Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB29 (1 << 29) /* 20000000: Serial Communication Interface 2 Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB30 (1 << 30) /* 40000000: Serial Communication Interface 1 Module Stop */ +#define R_MSTP_MSTPCRB_MSTPB31 (1 << 31) /* 80000000: Serial Communication Interface 0 Module Stop */ + +/* Module Stop Control Register C (32-bits) *********************************/ + +#define R_MSTP_MSTPCRC_MSTPC0 (1 << 0) /* 01: Clock Frequency Accuracy Measurement Circuit Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC1 (1 << 1) /* 02: Cyclic Redundancy Check Calculator Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC4 (1 << 4) /* 10: Graphics LCD Controller Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC6 (1 << 6) /* 40: 2D Drawing Engine Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC7 (1 << 7) /* 80: Serial Sound Interface1 Enhanced Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC8 (1 << 8) /* 100: Serial Sound Interface0 Enhanced Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC10 (1 << 10) /* 400: MIPI Display Serial Interface Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC11 (1 << 11) /* 800: Secure Digital Host IF 1 Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC12 (1 << 12) /* 1000: Secure Digital Host IF 0 Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC13 (1 << 13) /* 2000: Data Operation Circuit Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC14 (1 << 14) /* 4000: Event Link Controller Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC16 (1 << 16) /* 10000: CEU Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC26 (1 << 26) /* 4000000: Controller Area Network with Flexible Data-Rate 1 Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC27 (1 << 27) /* 8000000: Controller Area Network with Flexible Data-Rate 0 Module Stop */ +#define R_MSTP_MSTPCRC_MSTPC31 (1 << 31) /* 80000000: SHIP Module Stop */ + +/* Module Stop Control Register D (32-bits) *********************************/ + +#define R_MSTP_MSTPCRD_MSTPD4 (1 << 4) /* 10: Asynchronous General Purpose Timer 1 Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD5 (1 << 5) /* 20: Asynchronous General Purpose Timer 0 Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD11 (1 << 11) /* 800: Port Output Enable for GPT3 Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD12 (1 << 12) /* 1000: Port Output Enable for GPT2 Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD13 (1 << 13) /* 2000: Port Output Enable for GPT1 Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD14 (1 << 14) /* 4000: Port Output Enable for GPT0 Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD15 (1 << 15) /* 8000: 12-bit A/D Converter 1 Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD16 (1 << 16) /* 10000: 12-bit A/D Converter 0 Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD20 (1 << 20) /* 100000: 12-Bit D/A Converter Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD22 (1 << 22) /* 400000: Temperature Sensor Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD27 (1 << 27) /* 8000000: High-Speed Analog Com-parator 1 Module Stop */ +#define R_MSTP_MSTPCRD_MSTPD28 (1 << 28) /* 10000000: High-Speed Analog Com-parator 0 Module Stop */ + +/* Module Stop Control Register E (32-bits) *********************************/ + +#define R_MSTP_MSTPCRE_MSTPE8 (1 << 8) /* 100: Ultra-Low Power Timer 1 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE9 (1 << 9) /* 200: Ultra-Low Power Timer 0 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE18 (1 << 18) /* 40000: General PWM Timer 13 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE19 (1 << 19) /* 80000: General PWM Timer 12 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE20 (1 << 20) /* 100000: General PWM Timer 11 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE21 (1 << 21) /* 200000: General PWM Timer 10 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE22 (1 << 22) /* 400000: General PWM Timer 9 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE23 (1 << 23) /* 800000: General PWM Timer 8 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE24 (1 << 24) /* 1000000: General PWM Timer 7 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE25 (1 << 25) /* 2000000: General PWM Timer 6 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE26 (1 << 26) /* 4000000: General PWM Timer 5 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE27 (1 << 27) /* 8000000: General PWM Timer 4 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE28 (1 << 28) /* 10000000: General PWM Timer 3 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE29 (1 << 29) /* 20000000: General PWM Timer 2 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE30 (1 << 30) /* 40000000: General PWM Timer 1 Module Stop */ +#define R_MSTP_MSTPCRE_MSTPE31 (1 << 31) /* 80000000: General PWM Timer 0 Module Stop */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_MSTP_H */ diff --git a/arch/arm/src/ra8m1/hardware/ra8m1_option_setting.h b/arch/arm/src/ra8m1/hardware/ra8m1_option_setting.h new file mode 100644 index 00000000000..7db36ac4ebb --- /dev/null +++ b/arch/arm/src/ra8m1/hardware/ra8m1_option_setting.h @@ -0,0 +1,175 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/hardware/ra8m1_option_setting.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_OPTION_SETTING_H +#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_OPTION_SETTING_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Option-setting memory registers (RA8M1 User's Manual, chapter 6). + * + * These are not peripheral registers: they are words in the code-flash + * configuration area that the MCU samples at reset, programmed together + * with the image (FACI command / debugger), and read-only at run time. + * The linker script places each one by section name; there are no run-time + * addresses here. + * + * This is a flat (no TrustZone) image, so only the secure-region registers + * are used. OFS1 below is the register at 0x0300_A200 (called OFS1_SEC in + * the manual); the non-secure OFS1 at 0x1300_A180 is not used. + * + * Bits documented as "The program value is read from this bit" are + * reserved: they must be programmed as 1 (note 2 of each register). + */ + +/* Option Function Select Register 0 (OFS0) -- address 0x0300_A100 **********/ + +#define R_OFS0_RESERVED 0xa001a001 /* Bits 31, 29, 16, 15, 13, 0 */ + +/* Independent Watchdog Timer (IWDT) ****************************************/ + +#define R_OFS0_IWDTSTRT (1 << 1) /* 0: Auto start after reset, 1: Register start (stopped) */ + +#define R_OFS0_IWDTTOPS_SHIFT (2) /* Bits 3-2: Timeout period select */ +#define R_OFS0_IWDTTOPS_MASK (0x3) +# define R_OFS0_IWDTTOPS_128 (0 << R_OFS0_IWDTTOPS_SHIFT) /* 128 cycles */ +# define R_OFS0_IWDTTOPS_512 (1 << R_OFS0_IWDTTOPS_SHIFT) /* 512 cycles */ +# define R_OFS0_IWDTTOPS_1024 (2 << R_OFS0_IWDTTOPS_SHIFT) /* 1024 cycles */ +# define R_OFS0_IWDTTOPS_2048 (3 << R_OFS0_IWDTTOPS_SHIFT) /* 2048 cycles */ + +#define R_OFS0_IWDTCKS_SHIFT (4) /* Bits 7-4: Clock division ratio select */ +#define R_OFS0_IWDTCKS_MASK (0xf) +# define R_OFS0_IWDTCKS_DIV1 (0x0 << R_OFS0_IWDTCKS_SHIFT) /* x 1 */ +# define R_OFS0_IWDTCKS_DIV16 (0x2 << R_OFS0_IWDTCKS_SHIFT) /* x 1/16 */ +# define R_OFS0_IWDTCKS_DIV32 (0x3 << R_OFS0_IWDTCKS_SHIFT) /* x 1/32 */ +# define R_OFS0_IWDTCKS_DIV64 (0x4 << R_OFS0_IWDTCKS_SHIFT) /* x 1/64 */ +# define R_OFS0_IWDTCKS_DIV128 (0xf << R_OFS0_IWDTCKS_SHIFT) /* x 1/128 */ +# define R_OFS0_IWDTCKS_DIV256 (0x5 << R_OFS0_IWDTCKS_SHIFT) /* x 1/256 */ + +#define R_OFS0_IWDTRPES_SHIFT (8) /* Bits 9-8: Window end position select */ +#define R_OFS0_IWDTRPES_MASK (0x3) +# define R_OFS0_IWDTRPES_75 (0 << R_OFS0_IWDTRPES_SHIFT) /* 75% */ +# define R_OFS0_IWDTRPES_50 (1 << R_OFS0_IWDTRPES_SHIFT) /* 50% */ +# define R_OFS0_IWDTRPES_25 (2 << R_OFS0_IWDTRPES_SHIFT) /* 25% */ +# define R_OFS0_IWDTRPES_0 (3 << R_OFS0_IWDTRPES_SHIFT) /* 0% (no window end position) */ + +#define R_OFS0_IWDTRPSS_SHIFT (10) /* Bits 11-10: Window start position select */ +#define R_OFS0_IWDTRPSS_MASK (0x3) +# define R_OFS0_IWDTRPSS_25 (0 << R_OFS0_IWDTRPSS_SHIFT) /* 25% */ +# define R_OFS0_IWDTRPSS_50 (1 << R_OFS0_IWDTRPSS_SHIFT) /* 50% */ +# define R_OFS0_IWDTRPSS_75 (2 << R_OFS0_IWDTRPSS_SHIFT) /* 75% */ +# define R_OFS0_IWDTRPSS_100 (3 << R_OFS0_IWDTRPSS_SHIFT) /* 100% (no window start position) */ + +#define R_OFS0_IWDTRSTIRQS (1 << 12) /* 0: Interrupt, 1: Reset on underflow/refresh error */ +#define R_OFS0_IWDTSTPCTL (1 << 14) /* 0: Continue counting, 1: Stop counting in low power modes */ + +/* Watchdog Timer (WDT0) ****************************************************/ + +#define R_OFS0_WDT0STRT (1 << 17) /* 0: Auto start after reset, 1: Register start (stopped) */ + +#define R_OFS0_WDT0TOPS_SHIFT (18) /* Bits 19-18: Timeout period select */ +#define R_OFS0_WDT0TOPS_MASK (0x3) +# define R_OFS0_WDT0TOPS_1024 (0 << R_OFS0_WDT0TOPS_SHIFT) /* 1024 cycles */ +# define R_OFS0_WDT0TOPS_4096 (1 << R_OFS0_WDT0TOPS_SHIFT) /* 4096 cycles */ +# define R_OFS0_WDT0TOPS_8192 (2 << R_OFS0_WDT0TOPS_SHIFT) /* 8192 cycles */ +# define R_OFS0_WDT0TOPS_16384 (3 << R_OFS0_WDT0TOPS_SHIFT) /* 16384 cycles */ + +#define R_OFS0_WDT0CKS_SHIFT (20) /* Bits 23-20: Clock division ratio select */ +#define R_OFS0_WDT0CKS_MASK (0xf) +# define R_OFS0_WDT0CKS_DIV4 (0x1 << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 4 */ +# define R_OFS0_WDT0CKS_DIV64 (0x4 << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 64 */ +# define R_OFS0_WDT0CKS_DIV128 (0xf << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 128 */ +# define R_OFS0_WDT0CKS_DIV512 (0x6 << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 512 */ +# define R_OFS0_WDT0CKS_DIV2048 (0x7 << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 2048 */ +# define R_OFS0_WDT0CKS_DIV8192 (0x8 << R_OFS0_WDT0CKS_SHIFT) /* PCLKB / 8192 */ + +#define R_OFS0_WDT0RPES_SHIFT (24) /* Bits 25-24: Window end position select */ +#define R_OFS0_WDT0RPES_MASK (0x3) +# define R_OFS0_WDT0RPES_75 (0 << R_OFS0_WDT0RPES_SHIFT) /* 75% */ +# define R_OFS0_WDT0RPES_50 (1 << R_OFS0_WDT0RPES_SHIFT) /* 50% */ +# define R_OFS0_WDT0RPES_25 (2 << R_OFS0_WDT0RPES_SHIFT) /* 25% */ +# define R_OFS0_WDT0RPES_0 (3 << R_OFS0_WDT0RPES_SHIFT) /* 0% (no window end position) */ + +#define R_OFS0_WDT0RPSS_SHIFT (26) /* Bits 27-26: Window start position select */ +#define R_OFS0_WDT0RPSS_MASK (0x3) +# define R_OFS0_WDT0RPSS_25 (0 << R_OFS0_WDT0RPSS_SHIFT) /* 25% */ +# define R_OFS0_WDT0RPSS_50 (1 << R_OFS0_WDT0RPSS_SHIFT) /* 50% */ +# define R_OFS0_WDT0RPSS_75 (2 << R_OFS0_WDT0RPSS_SHIFT) /* 75% */ +# define R_OFS0_WDT0RPSS_100 (3 << R_OFS0_WDT0RPSS_SHIFT) /* 100% (no window start position) */ + +#define R_OFS0_WDT0RSTIRQS (1 << 28) /* 0: Interrupt, 1: Reset on underflow/refresh error */ +#define R_OFS0_WDT0STPCTL (1 << 30) /* 0: Continue counting, 1: Stop counting in CPU Sleep/Deep Sleep */ + +/* Option Function Select Register 1 (OFS1) -- address 0x0300_A200 **********/ + +/* Called OFS1_SEC in the manual. *******************************************/ + +#define R_OFS1_RESERVED 0xfcfff0d0 /* Bits 31-26, 23-12, 7-6, 4 */ + +#define R_OFS1_VDSEL_SHIFT (0) /* Bits 2-0: Voltage detection 0 level select */ +#define R_OFS1_VDSEL_MASK (0x7) +# define R_OFS1_VDSEL_2_85V (0 << R_OFS1_VDSEL_SHIFT) /* 2.85 V */ +# define R_OFS1_VDSEL_2_58V (1 << R_OFS1_VDSEL_SHIFT) /* 2.58 V */ +# define R_OFS1_VDSEL_2_15V (2 << R_OFS1_VDSEL_SHIFT) /* 2.15 V */ +# define R_OFS1_VDSEL_2_00V (3 << R_OFS1_VDSEL_SHIFT) /* 2.00 V */ +# define R_OFS1_VDSEL_1_90V (4 << R_OFS1_VDSEL_SHIFT) /* 1.90 V */ +# define R_OFS1_VDSEL_1_80V (5 << R_OFS1_VDSEL_SHIFT) /* 1.80 V */ +# define R_OFS1_VDSEL_1_70V (6 << R_OFS1_VDSEL_SHIFT) /* 1.70 V */ +# define R_OFS1_VDSEL_1_60V (7 << R_OFS1_VDSEL_SHIFT) /* 1.60 V */ + +#define R_OFS1_PVDAS (1 << 3) /* 0: Enable voltage monitor 0 reset after reset, 1: Disable */ +#define R_OFS1_PVDLPSEL (1 << 5) /* 0: Enable PVD0 low power function in DSTBY1/2, 1: Disable */ +#define R_OFS1_HOCOEN (1 << 8) /* 0: Enable HOCO oscillation after reset, 1: Disable */ + +#define R_OFS1_HOCOFRQ0_SHIFT (9) /* Bits 11-9: HOCO frequency setting 0 */ +#define R_OFS1_HOCOFRQ0_MASK (0x7) +# define R_OFS1_HOCOFRQ0_16MHZ (0 << R_OFS1_HOCOFRQ0_SHIFT) /* 16 MHz */ +# define R_OFS1_HOCOFRQ0_18MHZ (1 << R_OFS1_HOCOFRQ0_SHIFT) /* 18 MHz */ +# define R_OFS1_HOCOFRQ0_20MHZ (2 << R_OFS1_HOCOFRQ0_SHIFT) /* 20 MHz */ +# define R_OFS1_HOCOFRQ0_32MHZ (4 << R_OFS1_HOCOFRQ0_SHIFT) /* 32 MHz */ +# define R_OFS1_HOCOFRQ0_48MHZ (7 << R_OFS1_HOCOFRQ0_SHIFT) /* 48 MHz */ + +#define R_OFS1_SWDBG (1 << 24) /* 0: Enable software debug control, 1: Disable */ +#define R_OFS1_INITECCEN (1 << 25) /* 0: Disable TCM/cache ECC, 1: Enable */ + +/* Option Function Select Register 2 (OFS2) -- address 0x0300_A104 **********/ + +#define R_OFS2_RESERVED 0xfffffffe /* Bits 31-1 */ + +#define R_OFS2_DCDCEN (1 << 0) /* 0: Disable DCDC, 1: Enable DCDC */ + +/* OFS1 Security Attribution Register (OFS1_SEL) -- address 0x0300_A280 *****/ + +/* Each bit selects whether the matching OFS1 field comes from OFS1_SEC (0) + * or from the non-secure OFS1 (1). A flat image uses only OFS1 above, so + * the whole register is programmed as 0. + */ + +#define R_OFS1_SEL_ALL_SECURE 0x00000000 + +#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_OPTION_SETTING_H */ diff --git a/arch/arm/src/ra8m1/hardware/ra8m1_pinmap.h b/arch/arm/src/ra8m1/hardware/ra8m1_pinmap.h new file mode 100644 index 00000000000..e60d01d9698 --- /dev/null +++ b/arch/arm/src/ra8m1/hardware/ra8m1_pinmap.h @@ -0,0 +1,274 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/hardware/ra8m1_pinmap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_PINMAP_H +#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/ra8m1_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ +#define R_PFS_PSEL_PORT_OFFSET 0x40 +#define R_PFS_PSEL_PIN_OFFSET 0x04 + +/* RA8M1 has no PMISC peripheral. Its PFS write-protect register (PWPR) + * lives inside the PFS block itself -- User's Manual section 19.2.8. + * + * This port is a flat (no TrustZone) image, which always runs in the + * secure state and uses the secure aliases of every register, so PWPR is + * the secure instance (offset 0x514 from R_PFS_BASE). The manual also + * defines a non-secure PWPR at a different offset (0x50c from PFS_NS); + * it is deliberately not used here. + */ + +#define R_PFS_PWPR_OFFSET 0x0514 + +/* Port Control Registers (PCNTR1-4): confirmed against sections 19.2.1- + * 19.2.4. RA8M1 packs two 16-bit halves into each 32-bit PCNTRn, + * individually accessible at PCNTRn's own offset (low half) and +2 + * (high half). + * PCNTR4/EOSR/EORR only exist on PORT1-4 (ELC port-group function); the + * offsets are still defined generically here since nothing stops issuing + * the access, only the manual limits which ports implement it. + */ + +#define R_PORT_PCNTR1_OFFSET 0x0000 /* PDR (low 16) / PODR (high 16) */ +#define R_PORT_PDR_OFFSET 0x0000 /* Pmn Direction (16-bit) */ +#define R_PORT_PODR_OFFSET 0x0002 /* Pmn Output Data (16-bit) */ +#define R_PORT_PCNTR2_OFFSET 0x0004 /* PIDR (low 16) / EIDR (high 16) */ +#define R_PORT_PIDR_OFFSET 0x0004 /* Pmn State (16-bit, RO) */ +#define R_PORT_EIDR_OFFSET 0x0006 /* Port Event Input Data (16-bit, RO) */ +#define R_PORT_PCNTR3_OFFSET 0x0008 /* POSR (low 16) / PORR (high 16) */ +#define R_PORT_POSR_OFFSET 0x0008 /* Pmn Output Set (16-bit, WO) */ +#define R_PORT_PORR_OFFSET 0x000a /* Pmn Output Reset (16-bit, WO) */ +#define R_PORT_PCNTR4_OFFSET 0x000c /* EOSR (low 16) / EORR (high 16), PORT1-4 only */ +#define R_PORT_EOSR_OFFSET 0x000c /* Pmn Event Output Set (16-bit) */ +#define R_PORT_EORR_OFFSET 0x000e /* Pmn Event Output Reset (16-bit) */ + +/* Register Addresses *******************************************************/ + +#define R_PFS(port,pin) (R_PFS_BASE + (port)*R_PFS_PSEL_PORT_OFFSET + (pin)*R_PFS_PSEL_PIN_OFFSET) + +#define R_PFS_PWPR (R_PFS_BASE + R_PFS_PWPR_OFFSET) + +/* R_PORT0_BASE..R_PORT9_BASE, R_PORT10_BASE (PORTA) and R_PORT11_BASE + * (PORTB) in ra8m1_memorymap.h are all R_PORT0_BASE + port*0x20 -- this + * indexes that uniform stride instead of switching over 12 discrete + * per-instance macros. + */ + +#define R_PORT_BASE(port) (R_PORT0_BASE + (port)*0x20) + +#define R_PORT_PDR(port) (R_PORT_BASE(port) + R_PORT_PDR_OFFSET) +#define R_PORT_PODR(port) (R_PORT_BASE(port) + R_PORT_PODR_OFFSET) +#define R_PORT_PIDR(port) (R_PORT_BASE(port) + R_PORT_PIDR_OFFSET) +#define R_PORT_EIDR(port) (R_PORT_BASE(port) + R_PORT_EIDR_OFFSET) +#define R_PORT_POSR(port) (R_PORT_BASE(port) + R_PORT_POSR_OFFSET) +#define R_PORT_PORR(port) (R_PORT_BASE(port) + R_PORT_PORR_OFFSET) +#define R_PORT_EOSR(port) (R_PORT_BASE(port) + R_PORT_EOSR_OFFSET) +#define R_PORT_EORR(port) (R_PORT_BASE(port) + R_PORT_EORR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* PmnPFS/PmnPFS_HA/PmnPFS_BY - Port mn Pin Function Select Register. + * + * Bit positions confirmed against the RA8M1 User's Manual (R01UH0994EJ0130 + * Rev.1.30), section 19.2.5. + */ + +#define R_PFS_PSEL_SHIFT (24) /* 28:24: Peripheral Select. For individual pin functions, see the tables in RA8M1 User's Manual chapter 19.6 */ +#define R_PFS_PSEL_MASK (0x1f) +#define R_PFS_PMR (1 << 16) /* Bit 16: Port Mode Control */ +#define R_PFS_ASEL (1 << 15) /* Bit 15: Analog Input enable */ +#define R_PFS_ISEL (1 << 14) /* Bit 14: IRQ input enable */ +#define R_PFS_EOR (1 << 13) /* Bit 13: Event on Rising (EOFR[1:0] upper bit) */ +#define R_PFS_EOF (1 << 12) /* Bit 12: Event on Falling (EOFR[1:0] lower bit) */ +#define R_PFS_DSCR1 (1 << 11) /* Bit 11: Port Drive Capability 1 */ +#define R_PFS_DSCR (1 << 10) /* Bit 10: Port Drive Capability */ +#define R_PFS_NCODR (1 << 6) /* Bit 6: N-Channel Open Drain Control */ +#define R_PFS_PCR (1 << 4) /* Bit 4: Pull-up Control */ +#define R_PFS_PDR (1 << 2) /* Bit 2: Port Direction */ +#define R_PFS_PIDR (1 << 1) /* Bit 1: Port Input Data */ +#define R_PFS_PODR (1 << 0) /* Bit 0: Port Output Data */ + +/* PWPR - Write-Protect Register for the PmnPFS registers (section 19.2.8). + * PFSWE can only be set after B0WI has been cleared. + */ + +#define R_PFS_PWPR_B0WI (1 << 7) /* Bit 7: PFSWE Bit Write Disable */ +#define R_PFS_PWPR_PFSWE (1 << 6) /* Bit 6: PmnPFS Register Write Enable */ + +/* PSEL[4:0] peripheral-function values. + * + * RA8M1-specific: confirmed against User's Manual chapter 19.6 + * ("Peripheral Select Settings for Each Product", Tables 19.6-19.17, + * covering PORT0 through PORTB). PSEL is a per-pin, per-port mux slot -- + * the same numeric value means a different peripheral/channel depending on + * which pin it's applied to (e.g. PSEL=00100b is SCI0 on P112/P113 but + * SCI4 on P205/P206) -- so PFS_PSEL_SCI/PFS_PSEL_SCI1 below name the two + * generic "SCI mux slots" a port can offer, not a specific channel; the + * GPIO_RXDn_MISOn_SCLn_x/GPIO_TXDn_MOSIn_SDAn_x macros below already bake + * in which slot each specific pin needs. + * + * Only the SCI slots are defined here -- these are the only PSEL values + * this file's pin macros use, and the only ones confirmed against chapter + * 19.6. Every other peripheral (AGT/GPT/SPI/IIC/CLKOUT/CAN/etc.) has its + * own PSEL value per chapter 19.6 too; add those here once verified the + * same way, rather than guessing. + */ + +#define PFS_PSEL_SCI (0x04 << R_PFS_PSEL_SHIFT) +#define PFS_PSEL_SCI1 (0x05 << R_PFS_PSEL_SHIFT) + +/* GPIO ports and pins. + * + * RA8M1 has PORT0-PORT9 plus PORTA/PORTB (12 ports total, chapter 19.1 + * Table 19.1). PIN0-PIN15 are just the generic 0-15 per-port pin index + * (every RA8M1 port has up to 16 pins, PmnPFS's own n range). + */ + +#define PORT0 (0) +#define PORT1 (1) +#define PORT2 (2) +#define PORT3 (3) +#define PORT4 (4) +#define PORT5 (5) +#define PORT6 (6) +#define PORT7 (7) +#define PORT8 (8) +#define PORT9 (9) +#define PORTA (10) +#define PORTB (11) +#define PORT_INVALID (0xff) + +#define PIN0 (0) +#define PIN1 (1) +#define PIN2 (2) +#define PIN3 (3) +#define PIN4 (4) +#define PIN5 (5) +#define PIN6 (6) +#define PIN7 (7) +#define PIN8 (8) +#define PIN9 (9) +#define PIN10 (10) +#define PIN11 (11) +#define PIN12 (12) +#define PIN13 (13) +#define PIN14 (14) +#define PIN15 (15) +#define PIN_INVALID (0xff) + +/* SCI Alternative ********************************************************* + * + * RA8M1 has SCI0-SCI4 and SCI9 (SCI5-8 do not exist). Each channel's RXD/ + * TXD pair can be routed to one of three alternate pin groups (the + * manual's "_A"/"_B"/"_C" suffixes, numbered _1/_2/_3 below to match this + * port's existing GPIO_RXDn..._x / GPIO_TXDn..._x convention). RXD shares + * its pin with the simple-SPI MISO and simple-I2C SCL alternate functions; + * TXD shares its pin with simple-SPI MOSI and simple-I2C SDA -- the PFS + * PSEL value only selects "SCI" (or "SCI slot 2"); which of RXD/MISO/SCL + * actually drives the pin depends on the SCI's own mode register, not PFS. + * + * Source: RA8M1 User's Manual chapter 19.6, Tables 19.6-19.17 (PORT0- + * PORTB). SCK/CTS/RTS/DE (RS-485 driver-enable) pins exist for every + * channel/group too but are not defined here: no current RA8M1 SCI driver + * code (ra_serial.c) configures synchronous clock, hardware flow control, + * or RS-485 mode, so there is nothing yet to consume them. + */ + +#define GPIO_RXD0_MISO0_SCL0_1 (gpio_pinset_t){ PORT1,PIN13, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_TXD0_MOSI0_SDA0_1 (gpio_pinset_t){ PORT1,PIN12, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_RXD0_MISO0_SCL0_2 (gpio_pinset_t){ PORT6,PIN2, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_TXD0_MOSI0_SDA0_2 (gpio_pinset_t){ PORT6,PIN3, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_RXD0_MISO0_SCL0_3 (gpio_pinset_t){ PORT6,PIN10, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_TXD0_MOSI0_SDA0_3 (gpio_pinset_t){ PORT6,PIN9, (PFS_PSEL_SCI | R_PFS_PMR)} + +#define GPIO_RXD1_MISO1_SCL1_1 (gpio_pinset_t){ PORT4,PIN1, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_TXD1_MOSI1_SDA1_1 (gpio_pinset_t){ PORT4,PIN0, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_RXD1_MISO1_SCL1_2 (gpio_pinset_t){ PORT7,PIN6, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_TXD1_MOSI1_SDA1_2 (gpio_pinset_t){ PORT7,PIN7, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_RXD1_MISO1_SCL1_3 (gpio_pinset_t){ PORT2,PIN12, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_TXD1_MOSI1_SDA1_3 (gpio_pinset_t){ PORT2,PIN13, (PFS_PSEL_SCI1 | R_PFS_PMR)} + +#define GPIO_RXD2_MISO2_SCL2_1 (gpio_pinset_t){ PORT8,PIN2, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_TXD2_MOSI2_SDA2_1 (gpio_pinset_t){ PORT8,PIN1, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_RXD2_MISO2_SCL2_2 (gpio_pinset_t){ PORT7,PIN0, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_TXD2_MOSI2_SDA2_2 (gpio_pinset_t){ PORT4,PIN6, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_RXD2_MISO2_SCL2_3 (gpio_pinset_t){ PORTA,PIN2, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_TXD2_MOSI2_SDA2_3 (gpio_pinset_t){ PORTA,PIN3, (PFS_PSEL_SCI | R_PFS_PMR)} + +#define GPIO_RXD3_MISO3_SCL3_1 (gpio_pinset_t){ PORT4,PIN8, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_TXD3_MOSI3_SDA3_1 (gpio_pinset_t){ PORT4,PIN9, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_RXD3_MISO3_SCL3_2 (gpio_pinset_t){ PORT3,PIN9, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_TXD3_MOSI3_SDA3_2 (gpio_pinset_t){ PORT3,PIN10, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_RXD3_MISO3_SCL3_3 (gpio_pinset_t){ PORT9,PIN1, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_TXD3_MOSI3_SDA3_3 (gpio_pinset_t){ PORT9,PIN0, (PFS_PSEL_SCI1 | R_PFS_PMR)} + +#define GPIO_RXD4_MISO4_SCL4_1 (gpio_pinset_t){ PORT2,PIN6, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_TXD4_MOSI4_SDA4_1 (gpio_pinset_t){ PORT2,PIN5, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_RXD4_MISO4_SCL4_2 (gpio_pinset_t){ PORT4,PIN14, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_TXD4_MOSI4_SDA4_2 (gpio_pinset_t){ PORT4,PIN15, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_RXD4_MISO4_SCL4_3 (gpio_pinset_t){ PORT7,PIN15, (PFS_PSEL_SCI | R_PFS_PMR)} +#define GPIO_TXD4_MOSI4_SDA4_3 (gpio_pinset_t){ PORT7,PIN14, (PFS_PSEL_SCI | R_PFS_PMR)} + +#define GPIO_RXD9_MISO9_SCL9_1 (gpio_pinset_t){ PORT1,PIN1, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_TXD9_MOSI9_SDA9_1 (gpio_pinset_t){ PORT1,PIN2, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_RXD9_MISO9_SCL9_2 (gpio_pinset_t){ PORT2,PIN8, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_TXD9_MOSI9_SDA9_2 (gpio_pinset_t){ PORT2,PIN9, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_RXD9_MISO9_SCL9_3 (gpio_pinset_t){ PORTA,PIN15, (PFS_PSEL_SCI1 | R_PFS_PMR)} +#define GPIO_TXD9_MOSI9_SDA9_3 (gpio_pinset_t){ PORTA,PIN14, (PFS_PSEL_SCI1 | R_PFS_PMR)} + +/* GPIO Configuration */ + +#define GPIO_OUTPUT R_PFS_PDR +#define GPIO_INPUT ~(R_PFS_PDR | 0xFFFFFFFF) + +#define GPIO_LOW_DRIVE ~(R_PFS_DSCR | 0xFFFFFFFF) +#define GPIO_MIDDLE_DRIVE R_PFS_DSCR + +#define GPIO_OUTPUT_HIGH R_PFS_PODR +#define GPIO_OUTPUT_LOW ~(R_PFS_PODR | 0xFFFFFFFF) + +#define GPIO_PIN_INVALID (gpio_pinset_t){ PORT_INVALID, PIN_INVALID, 0xFFFFFFFF } + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_PINMAP_H */ diff --git a/arch/arm/src/ra8m1/hardware/ra8m1_sci.h b/arch/arm/src/ra8m1/hardware/ra8m1_sci.h new file mode 100644 index 00000000000..0c7918e493e --- /dev/null +++ b/arch/arm/src/ra8m1/hardware/ra8m1_sci.h @@ -0,0 +1,1989 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/hardware/ra8m1_sci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_SCI_H +#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_SCI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/ra8m1_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define R_SCI_B_RDR_OFFSET 0x0000 /* Received Data Register (32-bits) */ +#define R_SCI_B_TDR_OFFSET 0x0004 /* Transmission Data Register (32-bits) */ +#define R_SCI_B_TDR_HA_L_OFFSET 0x0004 /* Transmission Data Register (16-bits) */ +#define R_SCI_B_TDR_BY_LL_OFFSET 0x0004 /* Transmission Data Register (8-bits) */ +#define R_SCI_B_TDR_BY_LH_OFFSET 0x0005 /* Transmission Data Register (8-bits) */ +#define R_SCI_B_CCR0_OFFSET 0x0008 /* Common Control Register 0 (32-bits) */ +#define R_SCI_B_CCR0_HA_L_OFFSET 0x0008 /* Common Control Register 0 (16-bits) */ +#define R_SCI_B_CCR0_BY_LL_OFFSET 0x0008 /* Common Control Register 0 (8-bits) */ +#define R_SCI_B_CCR0_BY_LH_OFFSET 0x0009 /* Common Control Register 0 (8-bits) */ +#define R_SCI_B_CCR0_HA_H_OFFSET 0x000a /* Common Control Register 0 (16-bits) */ +#define R_SCI_B_CCR0_BY_HL_OFFSET 0x000a /* Common Control Register 0 (8-bits) */ +#define R_SCI_B_CCR0_BY_HH_OFFSET 0x000b /* Common Control Register 0 (8-bits) */ +#define R_SCI_B_CCR1_OFFSET 0x000c /* Common Control Register 1 (32-bits) */ +#define R_SCI_B_CCR1_HA_L_OFFSET 0x000c /* Common Control Register 1 (16-bits) */ +#define R_SCI_B_CCR1_BY_LL_OFFSET 0x000c /* Common Control Register 1 (8-bits) */ +#define R_SCI_B_CCR1_BY_LH_OFFSET 0x000d /* Common Control Register 1 (8-bits) */ +#define R_SCI_B_CCR1_HA_H_OFFSET 0x000e /* Common Control Register 1 (16-bits) */ +#define R_SCI_B_CCR1_BY_HL_OFFSET 0x000e /* Common Control Register 1 (8-bits) */ +#define R_SCI_B_CCR1_BY_HH_OFFSET 0x000f /* Common Control Register 1 (8-bits) */ +#define R_SCI_B_CCR2_OFFSET 0x0010 /* Common Control Register 2 (32-bits) */ +#define R_SCI_B_CCR2_HA_L_OFFSET 0x0010 /* Common Control Register 2 (16-bits) */ +#define R_SCI_B_CCR2_BY_LL_OFFSET 0x0010 /* Common Control Register 2 (8-bits) */ +#define R_SCI_B_CCR2_BY_LH_OFFSET 0x0011 /* Common Control Register 2 (8-bits) */ +#define R_SCI_B_CCR2_HA_H_OFFSET 0x0012 /* Common Control Register 2 (16-bits) */ +#define R_SCI_B_CCR2_BY_HL_OFFSET 0x0012 /* Common Control Register 2 (8-bits) */ +#define R_SCI_B_CCR2_BY_HH_OFFSET 0x0013 /* Common Control Register 2 (8-bits) */ +#define R_SCI_B_CCR3_OFFSET 0x0014 /* Common Control Register 3 (32-bits) */ +#define R_SCI_B_CCR3_HA_L_OFFSET 0x0014 /* Common Control Register 3 (16-bits) */ +#define R_SCI_B_CCR3_BY_LL_OFFSET 0x0014 /* Common Control Register 3 (8-bits) */ +#define R_SCI_B_CCR3_BY_LH_OFFSET 0x0015 /* Common Control Register 3 (8-bits) */ +#define R_SCI_B_CCR3_HA_H_OFFSET 0x0016 /* Common Control Register 3 (16-bits) */ +#define R_SCI_B_CCR3_BY_HL_OFFSET 0x0016 /* Common Control Register 3 (8-bits) */ +#define R_SCI_B_CCR3_BY_HH_OFFSET 0x0017 /* Common Control Register 3 (8-bits) */ +#define R_SCI_B_CCR4_OFFSET 0x0018 /* Common Control Register 4 (32-bits) */ +#define R_SCI_B_CCR4_HA_L_OFFSET 0x0018 /* Common Control Register 4 (16-bits) */ +#define R_SCI_B_CCR4_BY_LL_OFFSET 0x0018 /* Common Control Register 4 (8-bits) */ +#define R_SCI_B_CCR4_BY_LH_OFFSET 0x0019 /* Common Control Register 4 (8-bits) */ +#define R_SCI_B_CCR4_HA_H_OFFSET 0x001a /* Common Control Register 4 (16-bits) */ +#define R_SCI_B_CCR4_BY_HL_OFFSET 0x001a /* Common Control Register 4 (8-bits) */ +#define R_SCI_B_CCR4_BY_HH_OFFSET 0x001b /* Common Control Register 4 (8-bits) */ +#define R_SCI_B_CESR_OFFSET 0x001c /* Communication Enable Status Register (8-bits) */ +#define R_SCI_B_HCR_OFFSET 0x001e /* HBS valid mode Control Register (8-bits) */ +#define R_SCI_B_ICR_OFFSET 0x0020 /* Simple-I2C Control Register (32-bits) */ +#define R_SCI_B_ICR_HA_L_OFFSET 0x0020 /* Simple-I2C Control Register (16-bits) */ +#define R_SCI_B_ICR_BY_LL_OFFSET 0x0020 /* Simple-I2C Control Register (8-bits) */ +#define R_SCI_B_ICR_BY_LH_OFFSET 0x0021 /* Simple-I2C Control Register (8-bits) */ +#define R_SCI_B_ICR_HA_H_OFFSET 0x0022 /* Simple-I2C Control Register (16-bits) */ +#define R_SCI_B_ICR_BY_HL_OFFSET 0x0022 /* Simple-I2C Control Register (8-bits) */ +#define R_SCI_B_FCR_OFFSET 0x0024 /* FIFO Control Register (32-bits) */ +#define R_SCI_B_FCR_HA_L_OFFSET 0x0024 /* FIFO Control Register (16-bits) */ +#define R_SCI_B_FCR_BY_LL_OFFSET 0x0024 /* FIFO Control Register (8-bits) */ +#define R_SCI_B_FCR_BY_LH_OFFSET 0x0025 /* FIFO Control Register (8-bits) */ +#define R_SCI_B_FCR_HA_H_OFFSET 0x0026 /* FIFO Control Register (16-bits) */ +#define R_SCI_B_FCR_BY_HL_OFFSET 0x0026 /* FIFO Control Register (8-bits) */ +#define R_SCI_B_FCR_BY_HH_OFFSET 0x0027 /* FIFO Control Register (8-bits) */ +#define R_SCI_B_MCR_OFFSET 0x002c /* Manchester Control Register (32-bits) */ +#define R_SCI_B_MCR_HA_L_OFFSET 0x002c /* Manchester Control Register (16-bits) */ +#define R_SCI_B_MCR_BY_LL_OFFSET 0x002c /* Manchester Control Register (8-bits) */ +#define R_SCI_B_MCR_BY_LH_OFFSET 0x002d /* Manchester Control Register (8-bits) */ +#define R_SCI_B_MCR_HA_H_OFFSET 0x002e /* Manchester Control Register (16-bits) */ +#define R_SCI_B_MCR_BY_HL_OFFSET 0x002e /* Manchester Control Register (8-bits) */ +#define R_SCI_B_MCR_BY_HH_OFFSET 0x002f /* Manchester Control Register (8-bits) */ +#define R_SCI_B_DCR_OFFSET 0x0030 /* Driver Control Register (32-bits) */ +#define R_SCI_B_DCR_HA_L_OFFSET 0x0030 /* Driver Control Register (16-bits) */ +#define R_SCI_B_DCR_BY_LL_OFFSET 0x0030 /* Driver Control Register (8-bits) */ +#define R_SCI_B_DCR_BY_LH_OFFSET 0x0031 /* Driver Control Register (8-bits) */ +#define R_SCI_B_DCR_HA_H_OFFSET 0x0032 /* Driver Control Register (16-bits) */ +#define R_SCI_B_DCR_BY_HL_OFFSET 0x0032 /* Driver Control Register (8-bits) */ +#define R_SCI_B_XCR0_OFFSET 0x0034 /* Simple-LIN(SCIX) Control Register 0 (32-bits) */ +#define R_SCI_B_XCR0_HA_L_OFFSET 0x0034 /* Simple-LIN(SCIX) Control Register 0 (16-bits) */ +#define R_SCI_B_XCR0_BY_LL_OFFSET 0x0034 /* Simple-LIN(SCIX) Control Register 0 (8-bits) */ +#define R_SCI_B_XCR0_BY_LH_OFFSET 0x0035 /* Simple-LIN(SCIX) Control Register 0 (8-bits) */ +#define R_SCI_B_XCR0_HA_H_OFFSET 0x0036 /* Simple-LIN(SCIX) Control Register 0 (16-bits) */ +#define R_SCI_B_XCR0_BY_HL_OFFSET 0x0036 /* Simple-LIN(SCIX) Control Register 0 (8-bits) */ +#define R_SCI_B_XCR0_BY_HH_OFFSET 0x0037 /* Simple-LIN(SCIX) Control Register 0 (8-bits) */ +#define R_SCI_B_XCR1_OFFSET 0x0038 /* Simple-LIN(SCIX) Control Register 1 (32-bits) */ +#define R_SCI_B_XCR1_HA_L_OFFSET 0x0038 /* Simple-LIN(SCIX) Control Register 1 (16-bits) */ +#define R_SCI_B_XCR1_BY_LL_OFFSET 0x0038 /* Simple-LIN(SCIX) Control Register 1 (8-bits) */ +#define R_SCI_B_XCR1_BY_LH_OFFSET 0x0039 /* Simple-LIN(SCIX) Control Register 1 (8-bits) */ +#define R_SCI_B_XCR1_HA_H_OFFSET 0x003a /* Simple-LIN(SCIX) Control Register 1 (16-bits) */ +#define R_SCI_B_XCR1_BY_HL_OFFSET 0x003a /* Simple-LIN(SCIX) Control Register 1 (8-bits) */ +#define R_SCI_B_XCR1_BY_HH_OFFSET 0x003b /* Simple-LIN(SCIX) Control Register 1 (8-bits) */ +#define R_SCI_B_XCR2_OFFSET 0x003c /* Simple-LIN(SCIX) Control Register 2 (32-bits) */ +#define R_SCI_B_XCR2_HA_L_OFFSET 0x003c /* Simple-LIN(SCIX) Control Register 2 (16-bits) */ +#define R_SCI_B_XCR2_BY_LL_OFFSET 0x003c /* Simple-LIN(SCIX) Control Register 2 (8-bits) */ +#define R_SCI_B_XCR2_BY_LH_OFFSET 0x003d /* Simple-LIN(SCIX) Control Register 2 (8-bits) */ +#define R_SCI_B_XCR2_HA_H_OFFSET 0x003e /* Simple-LIN(SCIX) Control Register 2 (16-bits) */ +#define R_SCI_B_XCR2_BY_HL_OFFSET 0x003e /* Simple-LIN(SCIX) Control Register 2 (8-bits) */ +#define R_SCI_B_XCR2_BY_HH_OFFSET 0x003f /* Simple-LIN(SCIX) Control Register 2 (8-bits) */ +#define R_SCI_B_CSR_OFFSET 0x0048 /* Common Status Register (32-bits) */ +#define R_SCI_B_ISR_OFFSET 0x004c /* Simple-I2C Status Register (32-bits) */ +#define R_SCI_B_FRSR_OFFSET 0x0050 /* FIFO Receive Status Register (32-bits) */ +#define R_SCI_B_FTSR_OFFSET 0x0054 /* FIFO Transmit Status Register (32-bits) */ +#define R_SCI_B_MSR_OFFSET 0x0058 /* Manchester Status Register (32-bits) */ +#define R_SCI_B_XSR0_OFFSET 0x005c /* Simple-LIN(SCIX) Status Register 0 (32-bits) */ +#define R_SCI_B_XSR1_OFFSET 0x0060 /* Simple-LIN(SCIX) Status Register 1 (32-bits) */ +#define R_SCI_B_CFCLR_OFFSET 0x0068 /* Common Flag Clear Register (32-bits) */ +#define R_SCI_B_CFCLR_HA_L_OFFSET 0x0068 /* Common Flag Clear Register (16-bits) */ +#define R_SCI_B_CFCLR_BY_LL_OFFSET 0x0068 /* Common Flag Clear Register (8-bits) */ +#define R_SCI_B_CFCLR_HA_H_OFFSET 0x006a /* Common Flag Clear Register (16-bits) */ +#define R_SCI_B_CFCLR_BY_HL_OFFSET 0x006a /* Common Flag Clear Register (8-bits) */ +#define R_SCI_B_CFCLR_BY_HH_OFFSET 0x006b /* Common Flag Clear Register (8-bits) */ +#define R_SCI_B_ICFCLR_OFFSET 0x006c /* Simple-I2C Flag Clear Register (32-bits) */ +#define R_SCI_B_ICFCLR_HA_L_OFFSET 0x006c /* Simple-I2C Flag Clear Register (16-bits) */ +#define R_SCI_B_ICFCLR_BY_LL_OFFSET 0x006c /* Simple-I2C Flag Clear Register (8-bits) */ +#define R_SCI_B_FFCLR_OFFSET 0x0070 /* FIFO Flag Clear Register (32-bits) */ +#define R_SCI_B_FFCLR_HA_L_OFFSET 0x0070 /* FIFO Flag Clear Register (16-bits) */ +#define R_SCI_B_FFCLR_BY_LL_OFFSET 0x0070 /* FIFO Flag Clear Register (8-bits) */ +#define R_SCI_B_MFCLR_OFFSET 0x0074 /* Manchester Flag Clear Register (32-bits) */ +#define R_SCI_B_MFCLR_HA_L_OFFSET 0x0074 /* Manchester Flag Clear Register (16-bits) */ +#define R_SCI_B_MFCLR_BY_LL_OFFSET 0x0074 /* Manchester Flag Clear Register (8-bits) */ +#define R_SCI_B_XFCLR_OFFSET 0x0078 /* Simpe-LIN(SCIX) Flag Clear Register (32-bits) */ +#define R_SCI_B_XFCLR_HA_L_OFFSET 0x0078 /* Simpe-LIN(SCIX) Flag Clear Register (16-bits) */ +#define R_SCI_B_XFCLR_BY_LH_OFFSET 0x0079 /* Simpe-LIN(SCIX) Flag Clear Register (8-bits) */ + +/* Register Addresses *******************************************************/ + +/* SCI_B0 Registers */ + +#define R_SCI_B0_RDR (R_SCI_B0_BASE + R_SCI_B_RDR_OFFSET) +#define R_SCI_B0_TDR (R_SCI_B0_BASE + R_SCI_B_TDR_OFFSET) +#define R_SCI_B0_TDR_HA_L (R_SCI_B0_BASE + R_SCI_B_TDR_HA_L_OFFSET) +#define R_SCI_B0_TDR_BY_LL (R_SCI_B0_BASE + R_SCI_B_TDR_BY_LL_OFFSET) +#define R_SCI_B0_TDR_BY_LH (R_SCI_B0_BASE + R_SCI_B_TDR_BY_LH_OFFSET) +#define R_SCI_B0_CCR0 (R_SCI_B0_BASE + R_SCI_B_CCR0_OFFSET) +#define R_SCI_B0_CCR0_HA_L (R_SCI_B0_BASE + R_SCI_B_CCR0_HA_L_OFFSET) +#define R_SCI_B0_CCR0_BY_LL (R_SCI_B0_BASE + R_SCI_B_CCR0_BY_LL_OFFSET) +#define R_SCI_B0_CCR0_BY_LH (R_SCI_B0_BASE + R_SCI_B_CCR0_BY_LH_OFFSET) +#define R_SCI_B0_CCR0_HA_H (R_SCI_B0_BASE + R_SCI_B_CCR0_HA_H_OFFSET) +#define R_SCI_B0_CCR0_BY_HL (R_SCI_B0_BASE + R_SCI_B_CCR0_BY_HL_OFFSET) +#define R_SCI_B0_CCR0_BY_HH (R_SCI_B0_BASE + R_SCI_B_CCR0_BY_HH_OFFSET) +#define R_SCI_B0_CCR1 (R_SCI_B0_BASE + R_SCI_B_CCR1_OFFSET) +#define R_SCI_B0_CCR1_HA_L (R_SCI_B0_BASE + R_SCI_B_CCR1_HA_L_OFFSET) +#define R_SCI_B0_CCR1_BY_LL (R_SCI_B0_BASE + R_SCI_B_CCR1_BY_LL_OFFSET) +#define R_SCI_B0_CCR1_BY_LH (R_SCI_B0_BASE + R_SCI_B_CCR1_BY_LH_OFFSET) +#define R_SCI_B0_CCR1_HA_H (R_SCI_B0_BASE + R_SCI_B_CCR1_HA_H_OFFSET) +#define R_SCI_B0_CCR1_BY_HL (R_SCI_B0_BASE + R_SCI_B_CCR1_BY_HL_OFFSET) +#define R_SCI_B0_CCR1_BY_HH (R_SCI_B0_BASE + R_SCI_B_CCR1_BY_HH_OFFSET) +#define R_SCI_B0_CCR2 (R_SCI_B0_BASE + R_SCI_B_CCR2_OFFSET) +#define R_SCI_B0_CCR2_HA_L (R_SCI_B0_BASE + R_SCI_B_CCR2_HA_L_OFFSET) +#define R_SCI_B0_CCR2_BY_LL (R_SCI_B0_BASE + R_SCI_B_CCR2_BY_LL_OFFSET) +#define R_SCI_B0_CCR2_BY_LH (R_SCI_B0_BASE + R_SCI_B_CCR2_BY_LH_OFFSET) +#define R_SCI_B0_CCR2_HA_H (R_SCI_B0_BASE + R_SCI_B_CCR2_HA_H_OFFSET) +#define R_SCI_B0_CCR2_BY_HL (R_SCI_B0_BASE + R_SCI_B_CCR2_BY_HL_OFFSET) +#define R_SCI_B0_CCR2_BY_HH (R_SCI_B0_BASE + R_SCI_B_CCR2_BY_HH_OFFSET) +#define R_SCI_B0_CCR3 (R_SCI_B0_BASE + R_SCI_B_CCR3_OFFSET) +#define R_SCI_B0_CCR3_HA_L (R_SCI_B0_BASE + R_SCI_B_CCR3_HA_L_OFFSET) +#define R_SCI_B0_CCR3_BY_LL (R_SCI_B0_BASE + R_SCI_B_CCR3_BY_LL_OFFSET) +#define R_SCI_B0_CCR3_BY_LH (R_SCI_B0_BASE + R_SCI_B_CCR3_BY_LH_OFFSET) +#define R_SCI_B0_CCR3_HA_H (R_SCI_B0_BASE + R_SCI_B_CCR3_HA_H_OFFSET) +#define R_SCI_B0_CCR3_BY_HL (R_SCI_B0_BASE + R_SCI_B_CCR3_BY_HL_OFFSET) +#define R_SCI_B0_CCR3_BY_HH (R_SCI_B0_BASE + R_SCI_B_CCR3_BY_HH_OFFSET) +#define R_SCI_B0_CCR4 (R_SCI_B0_BASE + R_SCI_B_CCR4_OFFSET) +#define R_SCI_B0_CCR4_HA_L (R_SCI_B0_BASE + R_SCI_B_CCR4_HA_L_OFFSET) +#define R_SCI_B0_CCR4_BY_LL (R_SCI_B0_BASE + R_SCI_B_CCR4_BY_LL_OFFSET) +#define R_SCI_B0_CCR4_BY_LH (R_SCI_B0_BASE + R_SCI_B_CCR4_BY_LH_OFFSET) +#define R_SCI_B0_CCR4_HA_H (R_SCI_B0_BASE + R_SCI_B_CCR4_HA_H_OFFSET) +#define R_SCI_B0_CCR4_BY_HL (R_SCI_B0_BASE + R_SCI_B_CCR4_BY_HL_OFFSET) +#define R_SCI_B0_CCR4_BY_HH (R_SCI_B0_BASE + R_SCI_B_CCR4_BY_HH_OFFSET) +#define R_SCI_B0_CESR (R_SCI_B0_BASE + R_SCI_B_CESR_OFFSET) +#define R_SCI_B0_HCR (R_SCI_B0_BASE + R_SCI_B_HCR_OFFSET) +#define R_SCI_B0_ICR (R_SCI_B0_BASE + R_SCI_B_ICR_OFFSET) +#define R_SCI_B0_ICR_HA_L (R_SCI_B0_BASE + R_SCI_B_ICR_HA_L_OFFSET) +#define R_SCI_B0_ICR_BY_LL (R_SCI_B0_BASE + R_SCI_B_ICR_BY_LL_OFFSET) +#define R_SCI_B0_ICR_BY_LH (R_SCI_B0_BASE + R_SCI_B_ICR_BY_LH_OFFSET) +#define R_SCI_B0_ICR_HA_H (R_SCI_B0_BASE + R_SCI_B_ICR_HA_H_OFFSET) +#define R_SCI_B0_ICR_BY_HL (R_SCI_B0_BASE + R_SCI_B_ICR_BY_HL_OFFSET) +#define R_SCI_B0_FCR (R_SCI_B0_BASE + R_SCI_B_FCR_OFFSET) +#define R_SCI_B0_FCR_HA_L (R_SCI_B0_BASE + R_SCI_B_FCR_HA_L_OFFSET) +#define R_SCI_B0_FCR_BY_LL (R_SCI_B0_BASE + R_SCI_B_FCR_BY_LL_OFFSET) +#define R_SCI_B0_FCR_BY_LH (R_SCI_B0_BASE + R_SCI_B_FCR_BY_LH_OFFSET) +#define R_SCI_B0_FCR_HA_H (R_SCI_B0_BASE + R_SCI_B_FCR_HA_H_OFFSET) +#define R_SCI_B0_FCR_BY_HL (R_SCI_B0_BASE + R_SCI_B_FCR_BY_HL_OFFSET) +#define R_SCI_B0_FCR_BY_HH (R_SCI_B0_BASE + R_SCI_B_FCR_BY_HH_OFFSET) +#define R_SCI_B0_MCR (R_SCI_B0_BASE + R_SCI_B_MCR_OFFSET) +#define R_SCI_B0_MCR_HA_L (R_SCI_B0_BASE + R_SCI_B_MCR_HA_L_OFFSET) +#define R_SCI_B0_MCR_BY_LL (R_SCI_B0_BASE + R_SCI_B_MCR_BY_LL_OFFSET) +#define R_SCI_B0_MCR_BY_LH (R_SCI_B0_BASE + R_SCI_B_MCR_BY_LH_OFFSET) +#define R_SCI_B0_MCR_HA_H (R_SCI_B0_BASE + R_SCI_B_MCR_HA_H_OFFSET) +#define R_SCI_B0_MCR_BY_HL (R_SCI_B0_BASE + R_SCI_B_MCR_BY_HL_OFFSET) +#define R_SCI_B0_MCR_BY_HH (R_SCI_B0_BASE + R_SCI_B_MCR_BY_HH_OFFSET) +#define R_SCI_B0_DCR (R_SCI_B0_BASE + R_SCI_B_DCR_OFFSET) +#define R_SCI_B0_DCR_HA_L (R_SCI_B0_BASE + R_SCI_B_DCR_HA_L_OFFSET) +#define R_SCI_B0_DCR_BY_LL (R_SCI_B0_BASE + R_SCI_B_DCR_BY_LL_OFFSET) +#define R_SCI_B0_DCR_BY_LH (R_SCI_B0_BASE + R_SCI_B_DCR_BY_LH_OFFSET) +#define R_SCI_B0_DCR_HA_H (R_SCI_B0_BASE + R_SCI_B_DCR_HA_H_OFFSET) +#define R_SCI_B0_DCR_BY_HL (R_SCI_B0_BASE + R_SCI_B_DCR_BY_HL_OFFSET) +#define R_SCI_B0_XCR0 (R_SCI_B0_BASE + R_SCI_B_XCR0_OFFSET) +#define R_SCI_B0_XCR0_HA_L (R_SCI_B0_BASE + R_SCI_B_XCR0_HA_L_OFFSET) +#define R_SCI_B0_XCR0_BY_LL (R_SCI_B0_BASE + R_SCI_B_XCR0_BY_LL_OFFSET) +#define R_SCI_B0_XCR0_BY_LH (R_SCI_B0_BASE + R_SCI_B_XCR0_BY_LH_OFFSET) +#define R_SCI_B0_XCR0_HA_H (R_SCI_B0_BASE + R_SCI_B_XCR0_HA_H_OFFSET) +#define R_SCI_B0_XCR0_BY_HL (R_SCI_B0_BASE + R_SCI_B_XCR0_BY_HL_OFFSET) +#define R_SCI_B0_XCR0_BY_HH (R_SCI_B0_BASE + R_SCI_B_XCR0_BY_HH_OFFSET) +#define R_SCI_B0_XCR1 (R_SCI_B0_BASE + R_SCI_B_XCR1_OFFSET) +#define R_SCI_B0_XCR1_HA_L (R_SCI_B0_BASE + R_SCI_B_XCR1_HA_L_OFFSET) +#define R_SCI_B0_XCR1_BY_LL (R_SCI_B0_BASE + R_SCI_B_XCR1_BY_LL_OFFSET) +#define R_SCI_B0_XCR1_BY_LH (R_SCI_B0_BASE + R_SCI_B_XCR1_BY_LH_OFFSET) +#define R_SCI_B0_XCR1_HA_H (R_SCI_B0_BASE + R_SCI_B_XCR1_HA_H_OFFSET) +#define R_SCI_B0_XCR1_BY_HL (R_SCI_B0_BASE + R_SCI_B_XCR1_BY_HL_OFFSET) +#define R_SCI_B0_XCR1_BY_HH (R_SCI_B0_BASE + R_SCI_B_XCR1_BY_HH_OFFSET) +#define R_SCI_B0_XCR2 (R_SCI_B0_BASE + R_SCI_B_XCR2_OFFSET) +#define R_SCI_B0_XCR2_HA_L (R_SCI_B0_BASE + R_SCI_B_XCR2_HA_L_OFFSET) +#define R_SCI_B0_XCR2_BY_LL (R_SCI_B0_BASE + R_SCI_B_XCR2_BY_LL_OFFSET) +#define R_SCI_B0_XCR2_BY_LH (R_SCI_B0_BASE + R_SCI_B_XCR2_BY_LH_OFFSET) +#define R_SCI_B0_XCR2_HA_H (R_SCI_B0_BASE + R_SCI_B_XCR2_HA_H_OFFSET) +#define R_SCI_B0_XCR2_BY_HL (R_SCI_B0_BASE + R_SCI_B_XCR2_BY_HL_OFFSET) +#define R_SCI_B0_XCR2_BY_HH (R_SCI_B0_BASE + R_SCI_B_XCR2_BY_HH_OFFSET) +#define R_SCI_B0_CSR (R_SCI_B0_BASE + R_SCI_B_CSR_OFFSET) +#define R_SCI_B0_ISR (R_SCI_B0_BASE + R_SCI_B_ISR_OFFSET) +#define R_SCI_B0_FRSR (R_SCI_B0_BASE + R_SCI_B_FRSR_OFFSET) +#define R_SCI_B0_FTSR (R_SCI_B0_BASE + R_SCI_B_FTSR_OFFSET) +#define R_SCI_B0_MSR (R_SCI_B0_BASE + R_SCI_B_MSR_OFFSET) +#define R_SCI_B0_XSR0 (R_SCI_B0_BASE + R_SCI_B_XSR0_OFFSET) +#define R_SCI_B0_XSR1 (R_SCI_B0_BASE + R_SCI_B_XSR1_OFFSET) +#define R_SCI_B0_CFCLR (R_SCI_B0_BASE + R_SCI_B_CFCLR_OFFSET) +#define R_SCI_B0_CFCLR_HA_L (R_SCI_B0_BASE + R_SCI_B_CFCLR_HA_L_OFFSET) +#define R_SCI_B0_CFCLR_BY_LL (R_SCI_B0_BASE + R_SCI_B_CFCLR_BY_LL_OFFSET) +#define R_SCI_B0_CFCLR_HA_H (R_SCI_B0_BASE + R_SCI_B_CFCLR_HA_H_OFFSET) +#define R_SCI_B0_CFCLR_BY_HL (R_SCI_B0_BASE + R_SCI_B_CFCLR_BY_HL_OFFSET) +#define R_SCI_B0_CFCLR_BY_HH (R_SCI_B0_BASE + R_SCI_B_CFCLR_BY_HH_OFFSET) +#define R_SCI_B0_ICFCLR (R_SCI_B0_BASE + R_SCI_B_ICFCLR_OFFSET) +#define R_SCI_B0_ICFCLR_HA_L (R_SCI_B0_BASE + R_SCI_B_ICFCLR_HA_L_OFFSET) +#define R_SCI_B0_ICFCLR_BY_LL (R_SCI_B0_BASE + R_SCI_B_ICFCLR_BY_LL_OFFSET) +#define R_SCI_B0_FFCLR (R_SCI_B0_BASE + R_SCI_B_FFCLR_OFFSET) +#define R_SCI_B0_FFCLR_HA_L (R_SCI_B0_BASE + R_SCI_B_FFCLR_HA_L_OFFSET) +#define R_SCI_B0_FFCLR_BY_LL (R_SCI_B0_BASE + R_SCI_B_FFCLR_BY_LL_OFFSET) +#define R_SCI_B0_MFCLR (R_SCI_B0_BASE + R_SCI_B_MFCLR_OFFSET) +#define R_SCI_B0_MFCLR_HA_L (R_SCI_B0_BASE + R_SCI_B_MFCLR_HA_L_OFFSET) +#define R_SCI_B0_MFCLR_BY_LL (R_SCI_B0_BASE + R_SCI_B_MFCLR_BY_LL_OFFSET) +#define R_SCI_B0_XFCLR (R_SCI_B0_BASE + R_SCI_B_XFCLR_OFFSET) +#define R_SCI_B0_XFCLR_HA_L (R_SCI_B0_BASE + R_SCI_B_XFCLR_HA_L_OFFSET) +#define R_SCI_B0_XFCLR_BY_LH (R_SCI_B0_BASE + R_SCI_B_XFCLR_BY_LH_OFFSET) + +/* SCI_B1 Registers */ + +#define R_SCI_B1_RDR (R_SCI_B1_BASE + R_SCI_B_RDR_OFFSET) +#define R_SCI_B1_TDR (R_SCI_B1_BASE + R_SCI_B_TDR_OFFSET) +#define R_SCI_B1_TDR_HA_L (R_SCI_B1_BASE + R_SCI_B_TDR_HA_L_OFFSET) +#define R_SCI_B1_TDR_BY_LL (R_SCI_B1_BASE + R_SCI_B_TDR_BY_LL_OFFSET) +#define R_SCI_B1_TDR_BY_LH (R_SCI_B1_BASE + R_SCI_B_TDR_BY_LH_OFFSET) +#define R_SCI_B1_CCR0 (R_SCI_B1_BASE + R_SCI_B_CCR0_OFFSET) +#define R_SCI_B1_CCR0_HA_L (R_SCI_B1_BASE + R_SCI_B_CCR0_HA_L_OFFSET) +#define R_SCI_B1_CCR0_BY_LL (R_SCI_B1_BASE + R_SCI_B_CCR0_BY_LL_OFFSET) +#define R_SCI_B1_CCR0_BY_LH (R_SCI_B1_BASE + R_SCI_B_CCR0_BY_LH_OFFSET) +#define R_SCI_B1_CCR0_HA_H (R_SCI_B1_BASE + R_SCI_B_CCR0_HA_H_OFFSET) +#define R_SCI_B1_CCR0_BY_HL (R_SCI_B1_BASE + R_SCI_B_CCR0_BY_HL_OFFSET) +#define R_SCI_B1_CCR0_BY_HH (R_SCI_B1_BASE + R_SCI_B_CCR0_BY_HH_OFFSET) +#define R_SCI_B1_CCR1 (R_SCI_B1_BASE + R_SCI_B_CCR1_OFFSET) +#define R_SCI_B1_CCR1_HA_L (R_SCI_B1_BASE + R_SCI_B_CCR1_HA_L_OFFSET) +#define R_SCI_B1_CCR1_BY_LL (R_SCI_B1_BASE + R_SCI_B_CCR1_BY_LL_OFFSET) +#define R_SCI_B1_CCR1_BY_LH (R_SCI_B1_BASE + R_SCI_B_CCR1_BY_LH_OFFSET) +#define R_SCI_B1_CCR1_HA_H (R_SCI_B1_BASE + R_SCI_B_CCR1_HA_H_OFFSET) +#define R_SCI_B1_CCR1_BY_HL (R_SCI_B1_BASE + R_SCI_B_CCR1_BY_HL_OFFSET) +#define R_SCI_B1_CCR1_BY_HH (R_SCI_B1_BASE + R_SCI_B_CCR1_BY_HH_OFFSET) +#define R_SCI_B1_CCR2 (R_SCI_B1_BASE + R_SCI_B_CCR2_OFFSET) +#define R_SCI_B1_CCR2_HA_L (R_SCI_B1_BASE + R_SCI_B_CCR2_HA_L_OFFSET) +#define R_SCI_B1_CCR2_BY_LL (R_SCI_B1_BASE + R_SCI_B_CCR2_BY_LL_OFFSET) +#define R_SCI_B1_CCR2_BY_LH (R_SCI_B1_BASE + R_SCI_B_CCR2_BY_LH_OFFSET) +#define R_SCI_B1_CCR2_HA_H (R_SCI_B1_BASE + R_SCI_B_CCR2_HA_H_OFFSET) +#define R_SCI_B1_CCR2_BY_HL (R_SCI_B1_BASE + R_SCI_B_CCR2_BY_HL_OFFSET) +#define R_SCI_B1_CCR2_BY_HH (R_SCI_B1_BASE + R_SCI_B_CCR2_BY_HH_OFFSET) +#define R_SCI_B1_CCR3 (R_SCI_B1_BASE + R_SCI_B_CCR3_OFFSET) +#define R_SCI_B1_CCR3_HA_L (R_SCI_B1_BASE + R_SCI_B_CCR3_HA_L_OFFSET) +#define R_SCI_B1_CCR3_BY_LL (R_SCI_B1_BASE + R_SCI_B_CCR3_BY_LL_OFFSET) +#define R_SCI_B1_CCR3_BY_LH (R_SCI_B1_BASE + R_SCI_B_CCR3_BY_LH_OFFSET) +#define R_SCI_B1_CCR3_HA_H (R_SCI_B1_BASE + R_SCI_B_CCR3_HA_H_OFFSET) +#define R_SCI_B1_CCR3_BY_HL (R_SCI_B1_BASE + R_SCI_B_CCR3_BY_HL_OFFSET) +#define R_SCI_B1_CCR3_BY_HH (R_SCI_B1_BASE + R_SCI_B_CCR3_BY_HH_OFFSET) +#define R_SCI_B1_CCR4 (R_SCI_B1_BASE + R_SCI_B_CCR4_OFFSET) +#define R_SCI_B1_CCR4_HA_L (R_SCI_B1_BASE + R_SCI_B_CCR4_HA_L_OFFSET) +#define R_SCI_B1_CCR4_BY_LL (R_SCI_B1_BASE + R_SCI_B_CCR4_BY_LL_OFFSET) +#define R_SCI_B1_CCR4_BY_LH (R_SCI_B1_BASE + R_SCI_B_CCR4_BY_LH_OFFSET) +#define R_SCI_B1_CCR4_HA_H (R_SCI_B1_BASE + R_SCI_B_CCR4_HA_H_OFFSET) +#define R_SCI_B1_CCR4_BY_HL (R_SCI_B1_BASE + R_SCI_B_CCR4_BY_HL_OFFSET) +#define R_SCI_B1_CCR4_BY_HH (R_SCI_B1_BASE + R_SCI_B_CCR4_BY_HH_OFFSET) +#define R_SCI_B1_CESR (R_SCI_B1_BASE + R_SCI_B_CESR_OFFSET) +#define R_SCI_B1_HCR (R_SCI_B1_BASE + R_SCI_B_HCR_OFFSET) +#define R_SCI_B1_ICR (R_SCI_B1_BASE + R_SCI_B_ICR_OFFSET) +#define R_SCI_B1_ICR_HA_L (R_SCI_B1_BASE + R_SCI_B_ICR_HA_L_OFFSET) +#define R_SCI_B1_ICR_BY_LL (R_SCI_B1_BASE + R_SCI_B_ICR_BY_LL_OFFSET) +#define R_SCI_B1_ICR_BY_LH (R_SCI_B1_BASE + R_SCI_B_ICR_BY_LH_OFFSET) +#define R_SCI_B1_ICR_HA_H (R_SCI_B1_BASE + R_SCI_B_ICR_HA_H_OFFSET) +#define R_SCI_B1_ICR_BY_HL (R_SCI_B1_BASE + R_SCI_B_ICR_BY_HL_OFFSET) +#define R_SCI_B1_FCR (R_SCI_B1_BASE + R_SCI_B_FCR_OFFSET) +#define R_SCI_B1_FCR_HA_L (R_SCI_B1_BASE + R_SCI_B_FCR_HA_L_OFFSET) +#define R_SCI_B1_FCR_BY_LL (R_SCI_B1_BASE + R_SCI_B_FCR_BY_LL_OFFSET) +#define R_SCI_B1_FCR_BY_LH (R_SCI_B1_BASE + R_SCI_B_FCR_BY_LH_OFFSET) +#define R_SCI_B1_FCR_HA_H (R_SCI_B1_BASE + R_SCI_B_FCR_HA_H_OFFSET) +#define R_SCI_B1_FCR_BY_HL (R_SCI_B1_BASE + R_SCI_B_FCR_BY_HL_OFFSET) +#define R_SCI_B1_FCR_BY_HH (R_SCI_B1_BASE + R_SCI_B_FCR_BY_HH_OFFSET) +#define R_SCI_B1_MCR (R_SCI_B1_BASE + R_SCI_B_MCR_OFFSET) +#define R_SCI_B1_MCR_HA_L (R_SCI_B1_BASE + R_SCI_B_MCR_HA_L_OFFSET) +#define R_SCI_B1_MCR_BY_LL (R_SCI_B1_BASE + R_SCI_B_MCR_BY_LL_OFFSET) +#define R_SCI_B1_MCR_BY_LH (R_SCI_B1_BASE + R_SCI_B_MCR_BY_LH_OFFSET) +#define R_SCI_B1_MCR_HA_H (R_SCI_B1_BASE + R_SCI_B_MCR_HA_H_OFFSET) +#define R_SCI_B1_MCR_BY_HL (R_SCI_B1_BASE + R_SCI_B_MCR_BY_HL_OFFSET) +#define R_SCI_B1_MCR_BY_HH (R_SCI_B1_BASE + R_SCI_B_MCR_BY_HH_OFFSET) +#define R_SCI_B1_DCR (R_SCI_B1_BASE + R_SCI_B_DCR_OFFSET) +#define R_SCI_B1_DCR_HA_L (R_SCI_B1_BASE + R_SCI_B_DCR_HA_L_OFFSET) +#define R_SCI_B1_DCR_BY_LL (R_SCI_B1_BASE + R_SCI_B_DCR_BY_LL_OFFSET) +#define R_SCI_B1_DCR_BY_LH (R_SCI_B1_BASE + R_SCI_B_DCR_BY_LH_OFFSET) +#define R_SCI_B1_DCR_HA_H (R_SCI_B1_BASE + R_SCI_B_DCR_HA_H_OFFSET) +#define R_SCI_B1_DCR_BY_HL (R_SCI_B1_BASE + R_SCI_B_DCR_BY_HL_OFFSET) +#define R_SCI_B1_XCR0 (R_SCI_B1_BASE + R_SCI_B_XCR0_OFFSET) +#define R_SCI_B1_XCR0_HA_L (R_SCI_B1_BASE + R_SCI_B_XCR0_HA_L_OFFSET) +#define R_SCI_B1_XCR0_BY_LL (R_SCI_B1_BASE + R_SCI_B_XCR0_BY_LL_OFFSET) +#define R_SCI_B1_XCR0_BY_LH (R_SCI_B1_BASE + R_SCI_B_XCR0_BY_LH_OFFSET) +#define R_SCI_B1_XCR0_HA_H (R_SCI_B1_BASE + R_SCI_B_XCR0_HA_H_OFFSET) +#define R_SCI_B1_XCR0_BY_HL (R_SCI_B1_BASE + R_SCI_B_XCR0_BY_HL_OFFSET) +#define R_SCI_B1_XCR0_BY_HH (R_SCI_B1_BASE + R_SCI_B_XCR0_BY_HH_OFFSET) +#define R_SCI_B1_XCR1 (R_SCI_B1_BASE + R_SCI_B_XCR1_OFFSET) +#define R_SCI_B1_XCR1_HA_L (R_SCI_B1_BASE + R_SCI_B_XCR1_HA_L_OFFSET) +#define R_SCI_B1_XCR1_BY_LL (R_SCI_B1_BASE + R_SCI_B_XCR1_BY_LL_OFFSET) +#define R_SCI_B1_XCR1_BY_LH (R_SCI_B1_BASE + R_SCI_B_XCR1_BY_LH_OFFSET) +#define R_SCI_B1_XCR1_HA_H (R_SCI_B1_BASE + R_SCI_B_XCR1_HA_H_OFFSET) +#define R_SCI_B1_XCR1_BY_HL (R_SCI_B1_BASE + R_SCI_B_XCR1_BY_HL_OFFSET) +#define R_SCI_B1_XCR1_BY_HH (R_SCI_B1_BASE + R_SCI_B_XCR1_BY_HH_OFFSET) +#define R_SCI_B1_XCR2 (R_SCI_B1_BASE + R_SCI_B_XCR2_OFFSET) +#define R_SCI_B1_XCR2_HA_L (R_SCI_B1_BASE + R_SCI_B_XCR2_HA_L_OFFSET) +#define R_SCI_B1_XCR2_BY_LL (R_SCI_B1_BASE + R_SCI_B_XCR2_BY_LL_OFFSET) +#define R_SCI_B1_XCR2_BY_LH (R_SCI_B1_BASE + R_SCI_B_XCR2_BY_LH_OFFSET) +#define R_SCI_B1_XCR2_HA_H (R_SCI_B1_BASE + R_SCI_B_XCR2_HA_H_OFFSET) +#define R_SCI_B1_XCR2_BY_HL (R_SCI_B1_BASE + R_SCI_B_XCR2_BY_HL_OFFSET) +#define R_SCI_B1_XCR2_BY_HH (R_SCI_B1_BASE + R_SCI_B_XCR2_BY_HH_OFFSET) +#define R_SCI_B1_CSR (R_SCI_B1_BASE + R_SCI_B_CSR_OFFSET) +#define R_SCI_B1_ISR (R_SCI_B1_BASE + R_SCI_B_ISR_OFFSET) +#define R_SCI_B1_FRSR (R_SCI_B1_BASE + R_SCI_B_FRSR_OFFSET) +#define R_SCI_B1_FTSR (R_SCI_B1_BASE + R_SCI_B_FTSR_OFFSET) +#define R_SCI_B1_MSR (R_SCI_B1_BASE + R_SCI_B_MSR_OFFSET) +#define R_SCI_B1_XSR0 (R_SCI_B1_BASE + R_SCI_B_XSR0_OFFSET) +#define R_SCI_B1_XSR1 (R_SCI_B1_BASE + R_SCI_B_XSR1_OFFSET) +#define R_SCI_B1_CFCLR (R_SCI_B1_BASE + R_SCI_B_CFCLR_OFFSET) +#define R_SCI_B1_CFCLR_HA_L (R_SCI_B1_BASE + R_SCI_B_CFCLR_HA_L_OFFSET) +#define R_SCI_B1_CFCLR_BY_LL (R_SCI_B1_BASE + R_SCI_B_CFCLR_BY_LL_OFFSET) +#define R_SCI_B1_CFCLR_HA_H (R_SCI_B1_BASE + R_SCI_B_CFCLR_HA_H_OFFSET) +#define R_SCI_B1_CFCLR_BY_HL (R_SCI_B1_BASE + R_SCI_B_CFCLR_BY_HL_OFFSET) +#define R_SCI_B1_CFCLR_BY_HH (R_SCI_B1_BASE + R_SCI_B_CFCLR_BY_HH_OFFSET) +#define R_SCI_B1_ICFCLR (R_SCI_B1_BASE + R_SCI_B_ICFCLR_OFFSET) +#define R_SCI_B1_ICFCLR_HA_L (R_SCI_B1_BASE + R_SCI_B_ICFCLR_HA_L_OFFSET) +#define R_SCI_B1_ICFCLR_BY_LL (R_SCI_B1_BASE + R_SCI_B_ICFCLR_BY_LL_OFFSET) +#define R_SCI_B1_FFCLR (R_SCI_B1_BASE + R_SCI_B_FFCLR_OFFSET) +#define R_SCI_B1_FFCLR_HA_L (R_SCI_B1_BASE + R_SCI_B_FFCLR_HA_L_OFFSET) +#define R_SCI_B1_FFCLR_BY_LL (R_SCI_B1_BASE + R_SCI_B_FFCLR_BY_LL_OFFSET) +#define R_SCI_B1_MFCLR (R_SCI_B1_BASE + R_SCI_B_MFCLR_OFFSET) +#define R_SCI_B1_MFCLR_HA_L (R_SCI_B1_BASE + R_SCI_B_MFCLR_HA_L_OFFSET) +#define R_SCI_B1_MFCLR_BY_LL (R_SCI_B1_BASE + R_SCI_B_MFCLR_BY_LL_OFFSET) +#define R_SCI_B1_XFCLR (R_SCI_B1_BASE + R_SCI_B_XFCLR_OFFSET) +#define R_SCI_B1_XFCLR_HA_L (R_SCI_B1_BASE + R_SCI_B_XFCLR_HA_L_OFFSET) +#define R_SCI_B1_XFCLR_BY_LH (R_SCI_B1_BASE + R_SCI_B_XFCLR_BY_LH_OFFSET) + +/* SCI_B2 Registers */ + +#define R_SCI_B2_RDR (R_SCI_B2_BASE + R_SCI_B_RDR_OFFSET) +#define R_SCI_B2_TDR (R_SCI_B2_BASE + R_SCI_B_TDR_OFFSET) +#define R_SCI_B2_TDR_HA_L (R_SCI_B2_BASE + R_SCI_B_TDR_HA_L_OFFSET) +#define R_SCI_B2_TDR_BY_LL (R_SCI_B2_BASE + R_SCI_B_TDR_BY_LL_OFFSET) +#define R_SCI_B2_TDR_BY_LH (R_SCI_B2_BASE + R_SCI_B_TDR_BY_LH_OFFSET) +#define R_SCI_B2_CCR0 (R_SCI_B2_BASE + R_SCI_B_CCR0_OFFSET) +#define R_SCI_B2_CCR0_HA_L (R_SCI_B2_BASE + R_SCI_B_CCR0_HA_L_OFFSET) +#define R_SCI_B2_CCR0_BY_LL (R_SCI_B2_BASE + R_SCI_B_CCR0_BY_LL_OFFSET) +#define R_SCI_B2_CCR0_BY_LH (R_SCI_B2_BASE + R_SCI_B_CCR0_BY_LH_OFFSET) +#define R_SCI_B2_CCR0_HA_H (R_SCI_B2_BASE + R_SCI_B_CCR0_HA_H_OFFSET) +#define R_SCI_B2_CCR0_BY_HL (R_SCI_B2_BASE + R_SCI_B_CCR0_BY_HL_OFFSET) +#define R_SCI_B2_CCR0_BY_HH (R_SCI_B2_BASE + R_SCI_B_CCR0_BY_HH_OFFSET) +#define R_SCI_B2_CCR1 (R_SCI_B2_BASE + R_SCI_B_CCR1_OFFSET) +#define R_SCI_B2_CCR1_HA_L (R_SCI_B2_BASE + R_SCI_B_CCR1_HA_L_OFFSET) +#define R_SCI_B2_CCR1_BY_LL (R_SCI_B2_BASE + R_SCI_B_CCR1_BY_LL_OFFSET) +#define R_SCI_B2_CCR1_BY_LH (R_SCI_B2_BASE + R_SCI_B_CCR1_BY_LH_OFFSET) +#define R_SCI_B2_CCR1_HA_H (R_SCI_B2_BASE + R_SCI_B_CCR1_HA_H_OFFSET) +#define R_SCI_B2_CCR1_BY_HL (R_SCI_B2_BASE + R_SCI_B_CCR1_BY_HL_OFFSET) +#define R_SCI_B2_CCR1_BY_HH (R_SCI_B2_BASE + R_SCI_B_CCR1_BY_HH_OFFSET) +#define R_SCI_B2_CCR2 (R_SCI_B2_BASE + R_SCI_B_CCR2_OFFSET) +#define R_SCI_B2_CCR2_HA_L (R_SCI_B2_BASE + R_SCI_B_CCR2_HA_L_OFFSET) +#define R_SCI_B2_CCR2_BY_LL (R_SCI_B2_BASE + R_SCI_B_CCR2_BY_LL_OFFSET) +#define R_SCI_B2_CCR2_BY_LH (R_SCI_B2_BASE + R_SCI_B_CCR2_BY_LH_OFFSET) +#define R_SCI_B2_CCR2_HA_H (R_SCI_B2_BASE + R_SCI_B_CCR2_HA_H_OFFSET) +#define R_SCI_B2_CCR2_BY_HL (R_SCI_B2_BASE + R_SCI_B_CCR2_BY_HL_OFFSET) +#define R_SCI_B2_CCR2_BY_HH (R_SCI_B2_BASE + R_SCI_B_CCR2_BY_HH_OFFSET) +#define R_SCI_B2_CCR3 (R_SCI_B2_BASE + R_SCI_B_CCR3_OFFSET) +#define R_SCI_B2_CCR3_HA_L (R_SCI_B2_BASE + R_SCI_B_CCR3_HA_L_OFFSET) +#define R_SCI_B2_CCR3_BY_LL (R_SCI_B2_BASE + R_SCI_B_CCR3_BY_LL_OFFSET) +#define R_SCI_B2_CCR3_BY_LH (R_SCI_B2_BASE + R_SCI_B_CCR3_BY_LH_OFFSET) +#define R_SCI_B2_CCR3_HA_H (R_SCI_B2_BASE + R_SCI_B_CCR3_HA_H_OFFSET) +#define R_SCI_B2_CCR3_BY_HL (R_SCI_B2_BASE + R_SCI_B_CCR3_BY_HL_OFFSET) +#define R_SCI_B2_CCR3_BY_HH (R_SCI_B2_BASE + R_SCI_B_CCR3_BY_HH_OFFSET) +#define R_SCI_B2_CCR4 (R_SCI_B2_BASE + R_SCI_B_CCR4_OFFSET) +#define R_SCI_B2_CCR4_HA_L (R_SCI_B2_BASE + R_SCI_B_CCR4_HA_L_OFFSET) +#define R_SCI_B2_CCR4_BY_LL (R_SCI_B2_BASE + R_SCI_B_CCR4_BY_LL_OFFSET) +#define R_SCI_B2_CCR4_BY_LH (R_SCI_B2_BASE + R_SCI_B_CCR4_BY_LH_OFFSET) +#define R_SCI_B2_CCR4_HA_H (R_SCI_B2_BASE + R_SCI_B_CCR4_HA_H_OFFSET) +#define R_SCI_B2_CCR4_BY_HL (R_SCI_B2_BASE + R_SCI_B_CCR4_BY_HL_OFFSET) +#define R_SCI_B2_CCR4_BY_HH (R_SCI_B2_BASE + R_SCI_B_CCR4_BY_HH_OFFSET) +#define R_SCI_B2_CESR (R_SCI_B2_BASE + R_SCI_B_CESR_OFFSET) +#define R_SCI_B2_HCR (R_SCI_B2_BASE + R_SCI_B_HCR_OFFSET) +#define R_SCI_B2_ICR (R_SCI_B2_BASE + R_SCI_B_ICR_OFFSET) +#define R_SCI_B2_ICR_HA_L (R_SCI_B2_BASE + R_SCI_B_ICR_HA_L_OFFSET) +#define R_SCI_B2_ICR_BY_LL (R_SCI_B2_BASE + R_SCI_B_ICR_BY_LL_OFFSET) +#define R_SCI_B2_ICR_BY_LH (R_SCI_B2_BASE + R_SCI_B_ICR_BY_LH_OFFSET) +#define R_SCI_B2_ICR_HA_H (R_SCI_B2_BASE + R_SCI_B_ICR_HA_H_OFFSET) +#define R_SCI_B2_ICR_BY_HL (R_SCI_B2_BASE + R_SCI_B_ICR_BY_HL_OFFSET) +#define R_SCI_B2_FCR (R_SCI_B2_BASE + R_SCI_B_FCR_OFFSET) +#define R_SCI_B2_FCR_HA_L (R_SCI_B2_BASE + R_SCI_B_FCR_HA_L_OFFSET) +#define R_SCI_B2_FCR_BY_LL (R_SCI_B2_BASE + R_SCI_B_FCR_BY_LL_OFFSET) +#define R_SCI_B2_FCR_BY_LH (R_SCI_B2_BASE + R_SCI_B_FCR_BY_LH_OFFSET) +#define R_SCI_B2_FCR_HA_H (R_SCI_B2_BASE + R_SCI_B_FCR_HA_H_OFFSET) +#define R_SCI_B2_FCR_BY_HL (R_SCI_B2_BASE + R_SCI_B_FCR_BY_HL_OFFSET) +#define R_SCI_B2_FCR_BY_HH (R_SCI_B2_BASE + R_SCI_B_FCR_BY_HH_OFFSET) +#define R_SCI_B2_MCR (R_SCI_B2_BASE + R_SCI_B_MCR_OFFSET) +#define R_SCI_B2_MCR_HA_L (R_SCI_B2_BASE + R_SCI_B_MCR_HA_L_OFFSET) +#define R_SCI_B2_MCR_BY_LL (R_SCI_B2_BASE + R_SCI_B_MCR_BY_LL_OFFSET) +#define R_SCI_B2_MCR_BY_LH (R_SCI_B2_BASE + R_SCI_B_MCR_BY_LH_OFFSET) +#define R_SCI_B2_MCR_HA_H (R_SCI_B2_BASE + R_SCI_B_MCR_HA_H_OFFSET) +#define R_SCI_B2_MCR_BY_HL (R_SCI_B2_BASE + R_SCI_B_MCR_BY_HL_OFFSET) +#define R_SCI_B2_MCR_BY_HH (R_SCI_B2_BASE + R_SCI_B_MCR_BY_HH_OFFSET) +#define R_SCI_B2_DCR (R_SCI_B2_BASE + R_SCI_B_DCR_OFFSET) +#define R_SCI_B2_DCR_HA_L (R_SCI_B2_BASE + R_SCI_B_DCR_HA_L_OFFSET) +#define R_SCI_B2_DCR_BY_LL (R_SCI_B2_BASE + R_SCI_B_DCR_BY_LL_OFFSET) +#define R_SCI_B2_DCR_BY_LH (R_SCI_B2_BASE + R_SCI_B_DCR_BY_LH_OFFSET) +#define R_SCI_B2_DCR_HA_H (R_SCI_B2_BASE + R_SCI_B_DCR_HA_H_OFFSET) +#define R_SCI_B2_DCR_BY_HL (R_SCI_B2_BASE + R_SCI_B_DCR_BY_HL_OFFSET) +#define R_SCI_B2_XCR0 (R_SCI_B2_BASE + R_SCI_B_XCR0_OFFSET) +#define R_SCI_B2_XCR0_HA_L (R_SCI_B2_BASE + R_SCI_B_XCR0_HA_L_OFFSET) +#define R_SCI_B2_XCR0_BY_LL (R_SCI_B2_BASE + R_SCI_B_XCR0_BY_LL_OFFSET) +#define R_SCI_B2_XCR0_BY_LH (R_SCI_B2_BASE + R_SCI_B_XCR0_BY_LH_OFFSET) +#define R_SCI_B2_XCR0_HA_H (R_SCI_B2_BASE + R_SCI_B_XCR0_HA_H_OFFSET) +#define R_SCI_B2_XCR0_BY_HL (R_SCI_B2_BASE + R_SCI_B_XCR0_BY_HL_OFFSET) +#define R_SCI_B2_XCR0_BY_HH (R_SCI_B2_BASE + R_SCI_B_XCR0_BY_HH_OFFSET) +#define R_SCI_B2_XCR1 (R_SCI_B2_BASE + R_SCI_B_XCR1_OFFSET) +#define R_SCI_B2_XCR1_HA_L (R_SCI_B2_BASE + R_SCI_B_XCR1_HA_L_OFFSET) +#define R_SCI_B2_XCR1_BY_LL (R_SCI_B2_BASE + R_SCI_B_XCR1_BY_LL_OFFSET) +#define R_SCI_B2_XCR1_BY_LH (R_SCI_B2_BASE + R_SCI_B_XCR1_BY_LH_OFFSET) +#define R_SCI_B2_XCR1_HA_H (R_SCI_B2_BASE + R_SCI_B_XCR1_HA_H_OFFSET) +#define R_SCI_B2_XCR1_BY_HL (R_SCI_B2_BASE + R_SCI_B_XCR1_BY_HL_OFFSET) +#define R_SCI_B2_XCR1_BY_HH (R_SCI_B2_BASE + R_SCI_B_XCR1_BY_HH_OFFSET) +#define R_SCI_B2_XCR2 (R_SCI_B2_BASE + R_SCI_B_XCR2_OFFSET) +#define R_SCI_B2_XCR2_HA_L (R_SCI_B2_BASE + R_SCI_B_XCR2_HA_L_OFFSET) +#define R_SCI_B2_XCR2_BY_LL (R_SCI_B2_BASE + R_SCI_B_XCR2_BY_LL_OFFSET) +#define R_SCI_B2_XCR2_BY_LH (R_SCI_B2_BASE + R_SCI_B_XCR2_BY_LH_OFFSET) +#define R_SCI_B2_XCR2_HA_H (R_SCI_B2_BASE + R_SCI_B_XCR2_HA_H_OFFSET) +#define R_SCI_B2_XCR2_BY_HL (R_SCI_B2_BASE + R_SCI_B_XCR2_BY_HL_OFFSET) +#define R_SCI_B2_XCR2_BY_HH (R_SCI_B2_BASE + R_SCI_B_XCR2_BY_HH_OFFSET) +#define R_SCI_B2_CSR (R_SCI_B2_BASE + R_SCI_B_CSR_OFFSET) +#define R_SCI_B2_ISR (R_SCI_B2_BASE + R_SCI_B_ISR_OFFSET) +#define R_SCI_B2_FRSR (R_SCI_B2_BASE + R_SCI_B_FRSR_OFFSET) +#define R_SCI_B2_FTSR (R_SCI_B2_BASE + R_SCI_B_FTSR_OFFSET) +#define R_SCI_B2_MSR (R_SCI_B2_BASE + R_SCI_B_MSR_OFFSET) +#define R_SCI_B2_XSR0 (R_SCI_B2_BASE + R_SCI_B_XSR0_OFFSET) +#define R_SCI_B2_XSR1 (R_SCI_B2_BASE + R_SCI_B_XSR1_OFFSET) +#define R_SCI_B2_CFCLR (R_SCI_B2_BASE + R_SCI_B_CFCLR_OFFSET) +#define R_SCI_B2_CFCLR_HA_L (R_SCI_B2_BASE + R_SCI_B_CFCLR_HA_L_OFFSET) +#define R_SCI_B2_CFCLR_BY_LL (R_SCI_B2_BASE + R_SCI_B_CFCLR_BY_LL_OFFSET) +#define R_SCI_B2_CFCLR_HA_H (R_SCI_B2_BASE + R_SCI_B_CFCLR_HA_H_OFFSET) +#define R_SCI_B2_CFCLR_BY_HL (R_SCI_B2_BASE + R_SCI_B_CFCLR_BY_HL_OFFSET) +#define R_SCI_B2_CFCLR_BY_HH (R_SCI_B2_BASE + R_SCI_B_CFCLR_BY_HH_OFFSET) +#define R_SCI_B2_ICFCLR (R_SCI_B2_BASE + R_SCI_B_ICFCLR_OFFSET) +#define R_SCI_B2_ICFCLR_HA_L (R_SCI_B2_BASE + R_SCI_B_ICFCLR_HA_L_OFFSET) +#define R_SCI_B2_ICFCLR_BY_LL (R_SCI_B2_BASE + R_SCI_B_ICFCLR_BY_LL_OFFSET) +#define R_SCI_B2_FFCLR (R_SCI_B2_BASE + R_SCI_B_FFCLR_OFFSET) +#define R_SCI_B2_FFCLR_HA_L (R_SCI_B2_BASE + R_SCI_B_FFCLR_HA_L_OFFSET) +#define R_SCI_B2_FFCLR_BY_LL (R_SCI_B2_BASE + R_SCI_B_FFCLR_BY_LL_OFFSET) +#define R_SCI_B2_MFCLR (R_SCI_B2_BASE + R_SCI_B_MFCLR_OFFSET) +#define R_SCI_B2_MFCLR_HA_L (R_SCI_B2_BASE + R_SCI_B_MFCLR_HA_L_OFFSET) +#define R_SCI_B2_MFCLR_BY_LL (R_SCI_B2_BASE + R_SCI_B_MFCLR_BY_LL_OFFSET) +#define R_SCI_B2_XFCLR (R_SCI_B2_BASE + R_SCI_B_XFCLR_OFFSET) +#define R_SCI_B2_XFCLR_HA_L (R_SCI_B2_BASE + R_SCI_B_XFCLR_HA_L_OFFSET) +#define R_SCI_B2_XFCLR_BY_LH (R_SCI_B2_BASE + R_SCI_B_XFCLR_BY_LH_OFFSET) + +/* SCI_B3 Registers */ + +#define R_SCI_B3_RDR (R_SCI_B3_BASE + R_SCI_B_RDR_OFFSET) +#define R_SCI_B3_TDR (R_SCI_B3_BASE + R_SCI_B_TDR_OFFSET) +#define R_SCI_B3_TDR_HA_L (R_SCI_B3_BASE + R_SCI_B_TDR_HA_L_OFFSET) +#define R_SCI_B3_TDR_BY_LL (R_SCI_B3_BASE + R_SCI_B_TDR_BY_LL_OFFSET) +#define R_SCI_B3_TDR_BY_LH (R_SCI_B3_BASE + R_SCI_B_TDR_BY_LH_OFFSET) +#define R_SCI_B3_CCR0 (R_SCI_B3_BASE + R_SCI_B_CCR0_OFFSET) +#define R_SCI_B3_CCR0_HA_L (R_SCI_B3_BASE + R_SCI_B_CCR0_HA_L_OFFSET) +#define R_SCI_B3_CCR0_BY_LL (R_SCI_B3_BASE + R_SCI_B_CCR0_BY_LL_OFFSET) +#define R_SCI_B3_CCR0_BY_LH (R_SCI_B3_BASE + R_SCI_B_CCR0_BY_LH_OFFSET) +#define R_SCI_B3_CCR0_HA_H (R_SCI_B3_BASE + R_SCI_B_CCR0_HA_H_OFFSET) +#define R_SCI_B3_CCR0_BY_HL (R_SCI_B3_BASE + R_SCI_B_CCR0_BY_HL_OFFSET) +#define R_SCI_B3_CCR0_BY_HH (R_SCI_B3_BASE + R_SCI_B_CCR0_BY_HH_OFFSET) +#define R_SCI_B3_CCR1 (R_SCI_B3_BASE + R_SCI_B_CCR1_OFFSET) +#define R_SCI_B3_CCR1_HA_L (R_SCI_B3_BASE + R_SCI_B_CCR1_HA_L_OFFSET) +#define R_SCI_B3_CCR1_BY_LL (R_SCI_B3_BASE + R_SCI_B_CCR1_BY_LL_OFFSET) +#define R_SCI_B3_CCR1_BY_LH (R_SCI_B3_BASE + R_SCI_B_CCR1_BY_LH_OFFSET) +#define R_SCI_B3_CCR1_HA_H (R_SCI_B3_BASE + R_SCI_B_CCR1_HA_H_OFFSET) +#define R_SCI_B3_CCR1_BY_HL (R_SCI_B3_BASE + R_SCI_B_CCR1_BY_HL_OFFSET) +#define R_SCI_B3_CCR1_BY_HH (R_SCI_B3_BASE + R_SCI_B_CCR1_BY_HH_OFFSET) +#define R_SCI_B3_CCR2 (R_SCI_B3_BASE + R_SCI_B_CCR2_OFFSET) +#define R_SCI_B3_CCR2_HA_L (R_SCI_B3_BASE + R_SCI_B_CCR2_HA_L_OFFSET) +#define R_SCI_B3_CCR2_BY_LL (R_SCI_B3_BASE + R_SCI_B_CCR2_BY_LL_OFFSET) +#define R_SCI_B3_CCR2_BY_LH (R_SCI_B3_BASE + R_SCI_B_CCR2_BY_LH_OFFSET) +#define R_SCI_B3_CCR2_HA_H (R_SCI_B3_BASE + R_SCI_B_CCR2_HA_H_OFFSET) +#define R_SCI_B3_CCR2_BY_HL (R_SCI_B3_BASE + R_SCI_B_CCR2_BY_HL_OFFSET) +#define R_SCI_B3_CCR2_BY_HH (R_SCI_B3_BASE + R_SCI_B_CCR2_BY_HH_OFFSET) +#define R_SCI_B3_CCR3 (R_SCI_B3_BASE + R_SCI_B_CCR3_OFFSET) +#define R_SCI_B3_CCR3_HA_L (R_SCI_B3_BASE + R_SCI_B_CCR3_HA_L_OFFSET) +#define R_SCI_B3_CCR3_BY_LL (R_SCI_B3_BASE + R_SCI_B_CCR3_BY_LL_OFFSET) +#define R_SCI_B3_CCR3_BY_LH (R_SCI_B3_BASE + R_SCI_B_CCR3_BY_LH_OFFSET) +#define R_SCI_B3_CCR3_HA_H (R_SCI_B3_BASE + R_SCI_B_CCR3_HA_H_OFFSET) +#define R_SCI_B3_CCR3_BY_HL (R_SCI_B3_BASE + R_SCI_B_CCR3_BY_HL_OFFSET) +#define R_SCI_B3_CCR3_BY_HH (R_SCI_B3_BASE + R_SCI_B_CCR3_BY_HH_OFFSET) +#define R_SCI_B3_CCR4 (R_SCI_B3_BASE + R_SCI_B_CCR4_OFFSET) +#define R_SCI_B3_CCR4_HA_L (R_SCI_B3_BASE + R_SCI_B_CCR4_HA_L_OFFSET) +#define R_SCI_B3_CCR4_BY_LL (R_SCI_B3_BASE + R_SCI_B_CCR4_BY_LL_OFFSET) +#define R_SCI_B3_CCR4_BY_LH (R_SCI_B3_BASE + R_SCI_B_CCR4_BY_LH_OFFSET) +#define R_SCI_B3_CCR4_HA_H (R_SCI_B3_BASE + R_SCI_B_CCR4_HA_H_OFFSET) +#define R_SCI_B3_CCR4_BY_HL (R_SCI_B3_BASE + R_SCI_B_CCR4_BY_HL_OFFSET) +#define R_SCI_B3_CCR4_BY_HH (R_SCI_B3_BASE + R_SCI_B_CCR4_BY_HH_OFFSET) +#define R_SCI_B3_CESR (R_SCI_B3_BASE + R_SCI_B_CESR_OFFSET) +#define R_SCI_B3_HCR (R_SCI_B3_BASE + R_SCI_B_HCR_OFFSET) +#define R_SCI_B3_ICR (R_SCI_B3_BASE + R_SCI_B_ICR_OFFSET) +#define R_SCI_B3_ICR_HA_L (R_SCI_B3_BASE + R_SCI_B_ICR_HA_L_OFFSET) +#define R_SCI_B3_ICR_BY_LL (R_SCI_B3_BASE + R_SCI_B_ICR_BY_LL_OFFSET) +#define R_SCI_B3_ICR_BY_LH (R_SCI_B3_BASE + R_SCI_B_ICR_BY_LH_OFFSET) +#define R_SCI_B3_ICR_HA_H (R_SCI_B3_BASE + R_SCI_B_ICR_HA_H_OFFSET) +#define R_SCI_B3_ICR_BY_HL (R_SCI_B3_BASE + R_SCI_B_ICR_BY_HL_OFFSET) +#define R_SCI_B3_FCR (R_SCI_B3_BASE + R_SCI_B_FCR_OFFSET) +#define R_SCI_B3_FCR_HA_L (R_SCI_B3_BASE + R_SCI_B_FCR_HA_L_OFFSET) +#define R_SCI_B3_FCR_BY_LL (R_SCI_B3_BASE + R_SCI_B_FCR_BY_LL_OFFSET) +#define R_SCI_B3_FCR_BY_LH (R_SCI_B3_BASE + R_SCI_B_FCR_BY_LH_OFFSET) +#define R_SCI_B3_FCR_HA_H (R_SCI_B3_BASE + R_SCI_B_FCR_HA_H_OFFSET) +#define R_SCI_B3_FCR_BY_HL (R_SCI_B3_BASE + R_SCI_B_FCR_BY_HL_OFFSET) +#define R_SCI_B3_FCR_BY_HH (R_SCI_B3_BASE + R_SCI_B_FCR_BY_HH_OFFSET) +#define R_SCI_B3_MCR (R_SCI_B3_BASE + R_SCI_B_MCR_OFFSET) +#define R_SCI_B3_MCR_HA_L (R_SCI_B3_BASE + R_SCI_B_MCR_HA_L_OFFSET) +#define R_SCI_B3_MCR_BY_LL (R_SCI_B3_BASE + R_SCI_B_MCR_BY_LL_OFFSET) +#define R_SCI_B3_MCR_BY_LH (R_SCI_B3_BASE + R_SCI_B_MCR_BY_LH_OFFSET) +#define R_SCI_B3_MCR_HA_H (R_SCI_B3_BASE + R_SCI_B_MCR_HA_H_OFFSET) +#define R_SCI_B3_MCR_BY_HL (R_SCI_B3_BASE + R_SCI_B_MCR_BY_HL_OFFSET) +#define R_SCI_B3_MCR_BY_HH (R_SCI_B3_BASE + R_SCI_B_MCR_BY_HH_OFFSET) +#define R_SCI_B3_DCR (R_SCI_B3_BASE + R_SCI_B_DCR_OFFSET) +#define R_SCI_B3_DCR_HA_L (R_SCI_B3_BASE + R_SCI_B_DCR_HA_L_OFFSET) +#define R_SCI_B3_DCR_BY_LL (R_SCI_B3_BASE + R_SCI_B_DCR_BY_LL_OFFSET) +#define R_SCI_B3_DCR_BY_LH (R_SCI_B3_BASE + R_SCI_B_DCR_BY_LH_OFFSET) +#define R_SCI_B3_DCR_HA_H (R_SCI_B3_BASE + R_SCI_B_DCR_HA_H_OFFSET) +#define R_SCI_B3_DCR_BY_HL (R_SCI_B3_BASE + R_SCI_B_DCR_BY_HL_OFFSET) +#define R_SCI_B3_XCR0 (R_SCI_B3_BASE + R_SCI_B_XCR0_OFFSET) +#define R_SCI_B3_XCR0_HA_L (R_SCI_B3_BASE + R_SCI_B_XCR0_HA_L_OFFSET) +#define R_SCI_B3_XCR0_BY_LL (R_SCI_B3_BASE + R_SCI_B_XCR0_BY_LL_OFFSET) +#define R_SCI_B3_XCR0_BY_LH (R_SCI_B3_BASE + R_SCI_B_XCR0_BY_LH_OFFSET) +#define R_SCI_B3_XCR0_HA_H (R_SCI_B3_BASE + R_SCI_B_XCR0_HA_H_OFFSET) +#define R_SCI_B3_XCR0_BY_HL (R_SCI_B3_BASE + R_SCI_B_XCR0_BY_HL_OFFSET) +#define R_SCI_B3_XCR0_BY_HH (R_SCI_B3_BASE + R_SCI_B_XCR0_BY_HH_OFFSET) +#define R_SCI_B3_XCR1 (R_SCI_B3_BASE + R_SCI_B_XCR1_OFFSET) +#define R_SCI_B3_XCR1_HA_L (R_SCI_B3_BASE + R_SCI_B_XCR1_HA_L_OFFSET) +#define R_SCI_B3_XCR1_BY_LL (R_SCI_B3_BASE + R_SCI_B_XCR1_BY_LL_OFFSET) +#define R_SCI_B3_XCR1_BY_LH (R_SCI_B3_BASE + R_SCI_B_XCR1_BY_LH_OFFSET) +#define R_SCI_B3_XCR1_HA_H (R_SCI_B3_BASE + R_SCI_B_XCR1_HA_H_OFFSET) +#define R_SCI_B3_XCR1_BY_HL (R_SCI_B3_BASE + R_SCI_B_XCR1_BY_HL_OFFSET) +#define R_SCI_B3_XCR1_BY_HH (R_SCI_B3_BASE + R_SCI_B_XCR1_BY_HH_OFFSET) +#define R_SCI_B3_XCR2 (R_SCI_B3_BASE + R_SCI_B_XCR2_OFFSET) +#define R_SCI_B3_XCR2_HA_L (R_SCI_B3_BASE + R_SCI_B_XCR2_HA_L_OFFSET) +#define R_SCI_B3_XCR2_BY_LL (R_SCI_B3_BASE + R_SCI_B_XCR2_BY_LL_OFFSET) +#define R_SCI_B3_XCR2_BY_LH (R_SCI_B3_BASE + R_SCI_B_XCR2_BY_LH_OFFSET) +#define R_SCI_B3_XCR2_HA_H (R_SCI_B3_BASE + R_SCI_B_XCR2_HA_H_OFFSET) +#define R_SCI_B3_XCR2_BY_HL (R_SCI_B3_BASE + R_SCI_B_XCR2_BY_HL_OFFSET) +#define R_SCI_B3_XCR2_BY_HH (R_SCI_B3_BASE + R_SCI_B_XCR2_BY_HH_OFFSET) +#define R_SCI_B3_CSR (R_SCI_B3_BASE + R_SCI_B_CSR_OFFSET) +#define R_SCI_B3_ISR (R_SCI_B3_BASE + R_SCI_B_ISR_OFFSET) +#define R_SCI_B3_FRSR (R_SCI_B3_BASE + R_SCI_B_FRSR_OFFSET) +#define R_SCI_B3_FTSR (R_SCI_B3_BASE + R_SCI_B_FTSR_OFFSET) +#define R_SCI_B3_MSR (R_SCI_B3_BASE + R_SCI_B_MSR_OFFSET) +#define R_SCI_B3_XSR0 (R_SCI_B3_BASE + R_SCI_B_XSR0_OFFSET) +#define R_SCI_B3_XSR1 (R_SCI_B3_BASE + R_SCI_B_XSR1_OFFSET) +#define R_SCI_B3_CFCLR (R_SCI_B3_BASE + R_SCI_B_CFCLR_OFFSET) +#define R_SCI_B3_CFCLR_HA_L (R_SCI_B3_BASE + R_SCI_B_CFCLR_HA_L_OFFSET) +#define R_SCI_B3_CFCLR_BY_LL (R_SCI_B3_BASE + R_SCI_B_CFCLR_BY_LL_OFFSET) +#define R_SCI_B3_CFCLR_HA_H (R_SCI_B3_BASE + R_SCI_B_CFCLR_HA_H_OFFSET) +#define R_SCI_B3_CFCLR_BY_HL (R_SCI_B3_BASE + R_SCI_B_CFCLR_BY_HL_OFFSET) +#define R_SCI_B3_CFCLR_BY_HH (R_SCI_B3_BASE + R_SCI_B_CFCLR_BY_HH_OFFSET) +#define R_SCI_B3_ICFCLR (R_SCI_B3_BASE + R_SCI_B_ICFCLR_OFFSET) +#define R_SCI_B3_ICFCLR_HA_L (R_SCI_B3_BASE + R_SCI_B_ICFCLR_HA_L_OFFSET) +#define R_SCI_B3_ICFCLR_BY_LL (R_SCI_B3_BASE + R_SCI_B_ICFCLR_BY_LL_OFFSET) +#define R_SCI_B3_FFCLR (R_SCI_B3_BASE + R_SCI_B_FFCLR_OFFSET) +#define R_SCI_B3_FFCLR_HA_L (R_SCI_B3_BASE + R_SCI_B_FFCLR_HA_L_OFFSET) +#define R_SCI_B3_FFCLR_BY_LL (R_SCI_B3_BASE + R_SCI_B_FFCLR_BY_LL_OFFSET) +#define R_SCI_B3_MFCLR (R_SCI_B3_BASE + R_SCI_B_MFCLR_OFFSET) +#define R_SCI_B3_MFCLR_HA_L (R_SCI_B3_BASE + R_SCI_B_MFCLR_HA_L_OFFSET) +#define R_SCI_B3_MFCLR_BY_LL (R_SCI_B3_BASE + R_SCI_B_MFCLR_BY_LL_OFFSET) +#define R_SCI_B3_XFCLR (R_SCI_B3_BASE + R_SCI_B_XFCLR_OFFSET) +#define R_SCI_B3_XFCLR_HA_L (R_SCI_B3_BASE + R_SCI_B_XFCLR_HA_L_OFFSET) +#define R_SCI_B3_XFCLR_BY_LH (R_SCI_B3_BASE + R_SCI_B_XFCLR_BY_LH_OFFSET) + +/* SCI_B4 Registers */ + +#define R_SCI_B4_RDR (R_SCI_B4_BASE + R_SCI_B_RDR_OFFSET) +#define R_SCI_B4_TDR (R_SCI_B4_BASE + R_SCI_B_TDR_OFFSET) +#define R_SCI_B4_TDR_HA_L (R_SCI_B4_BASE + R_SCI_B_TDR_HA_L_OFFSET) +#define R_SCI_B4_TDR_BY_LL (R_SCI_B4_BASE + R_SCI_B_TDR_BY_LL_OFFSET) +#define R_SCI_B4_TDR_BY_LH (R_SCI_B4_BASE + R_SCI_B_TDR_BY_LH_OFFSET) +#define R_SCI_B4_CCR0 (R_SCI_B4_BASE + R_SCI_B_CCR0_OFFSET) +#define R_SCI_B4_CCR0_HA_L (R_SCI_B4_BASE + R_SCI_B_CCR0_HA_L_OFFSET) +#define R_SCI_B4_CCR0_BY_LL (R_SCI_B4_BASE + R_SCI_B_CCR0_BY_LL_OFFSET) +#define R_SCI_B4_CCR0_BY_LH (R_SCI_B4_BASE + R_SCI_B_CCR0_BY_LH_OFFSET) +#define R_SCI_B4_CCR0_HA_H (R_SCI_B4_BASE + R_SCI_B_CCR0_HA_H_OFFSET) +#define R_SCI_B4_CCR0_BY_HL (R_SCI_B4_BASE + R_SCI_B_CCR0_BY_HL_OFFSET) +#define R_SCI_B4_CCR0_BY_HH (R_SCI_B4_BASE + R_SCI_B_CCR0_BY_HH_OFFSET) +#define R_SCI_B4_CCR1 (R_SCI_B4_BASE + R_SCI_B_CCR1_OFFSET) +#define R_SCI_B4_CCR1_HA_L (R_SCI_B4_BASE + R_SCI_B_CCR1_HA_L_OFFSET) +#define R_SCI_B4_CCR1_BY_LL (R_SCI_B4_BASE + R_SCI_B_CCR1_BY_LL_OFFSET) +#define R_SCI_B4_CCR1_BY_LH (R_SCI_B4_BASE + R_SCI_B_CCR1_BY_LH_OFFSET) +#define R_SCI_B4_CCR1_HA_H (R_SCI_B4_BASE + R_SCI_B_CCR1_HA_H_OFFSET) +#define R_SCI_B4_CCR1_BY_HL (R_SCI_B4_BASE + R_SCI_B_CCR1_BY_HL_OFFSET) +#define R_SCI_B4_CCR1_BY_HH (R_SCI_B4_BASE + R_SCI_B_CCR1_BY_HH_OFFSET) +#define R_SCI_B4_CCR2 (R_SCI_B4_BASE + R_SCI_B_CCR2_OFFSET) +#define R_SCI_B4_CCR2_HA_L (R_SCI_B4_BASE + R_SCI_B_CCR2_HA_L_OFFSET) +#define R_SCI_B4_CCR2_BY_LL (R_SCI_B4_BASE + R_SCI_B_CCR2_BY_LL_OFFSET) +#define R_SCI_B4_CCR2_BY_LH (R_SCI_B4_BASE + R_SCI_B_CCR2_BY_LH_OFFSET) +#define R_SCI_B4_CCR2_HA_H (R_SCI_B4_BASE + R_SCI_B_CCR2_HA_H_OFFSET) +#define R_SCI_B4_CCR2_BY_HL (R_SCI_B4_BASE + R_SCI_B_CCR2_BY_HL_OFFSET) +#define R_SCI_B4_CCR2_BY_HH (R_SCI_B4_BASE + R_SCI_B_CCR2_BY_HH_OFFSET) +#define R_SCI_B4_CCR3 (R_SCI_B4_BASE + R_SCI_B_CCR3_OFFSET) +#define R_SCI_B4_CCR3_HA_L (R_SCI_B4_BASE + R_SCI_B_CCR3_HA_L_OFFSET) +#define R_SCI_B4_CCR3_BY_LL (R_SCI_B4_BASE + R_SCI_B_CCR3_BY_LL_OFFSET) +#define R_SCI_B4_CCR3_BY_LH (R_SCI_B4_BASE + R_SCI_B_CCR3_BY_LH_OFFSET) +#define R_SCI_B4_CCR3_HA_H (R_SCI_B4_BASE + R_SCI_B_CCR3_HA_H_OFFSET) +#define R_SCI_B4_CCR3_BY_HL (R_SCI_B4_BASE + R_SCI_B_CCR3_BY_HL_OFFSET) +#define R_SCI_B4_CCR3_BY_HH (R_SCI_B4_BASE + R_SCI_B_CCR3_BY_HH_OFFSET) +#define R_SCI_B4_CCR4 (R_SCI_B4_BASE + R_SCI_B_CCR4_OFFSET) +#define R_SCI_B4_CCR4_HA_L (R_SCI_B4_BASE + R_SCI_B_CCR4_HA_L_OFFSET) +#define R_SCI_B4_CCR4_BY_LL (R_SCI_B4_BASE + R_SCI_B_CCR4_BY_LL_OFFSET) +#define R_SCI_B4_CCR4_BY_LH (R_SCI_B4_BASE + R_SCI_B_CCR4_BY_LH_OFFSET) +#define R_SCI_B4_CCR4_HA_H (R_SCI_B4_BASE + R_SCI_B_CCR4_HA_H_OFFSET) +#define R_SCI_B4_CCR4_BY_HL (R_SCI_B4_BASE + R_SCI_B_CCR4_BY_HL_OFFSET) +#define R_SCI_B4_CCR4_BY_HH (R_SCI_B4_BASE + R_SCI_B_CCR4_BY_HH_OFFSET) +#define R_SCI_B4_CESR (R_SCI_B4_BASE + R_SCI_B_CESR_OFFSET) +#define R_SCI_B4_HCR (R_SCI_B4_BASE + R_SCI_B_HCR_OFFSET) +#define R_SCI_B4_ICR (R_SCI_B4_BASE + R_SCI_B_ICR_OFFSET) +#define R_SCI_B4_ICR_HA_L (R_SCI_B4_BASE + R_SCI_B_ICR_HA_L_OFFSET) +#define R_SCI_B4_ICR_BY_LL (R_SCI_B4_BASE + R_SCI_B_ICR_BY_LL_OFFSET) +#define R_SCI_B4_ICR_BY_LH (R_SCI_B4_BASE + R_SCI_B_ICR_BY_LH_OFFSET) +#define R_SCI_B4_ICR_HA_H (R_SCI_B4_BASE + R_SCI_B_ICR_HA_H_OFFSET) +#define R_SCI_B4_ICR_BY_HL (R_SCI_B4_BASE + R_SCI_B_ICR_BY_HL_OFFSET) +#define R_SCI_B4_FCR (R_SCI_B4_BASE + R_SCI_B_FCR_OFFSET) +#define R_SCI_B4_FCR_HA_L (R_SCI_B4_BASE + R_SCI_B_FCR_HA_L_OFFSET) +#define R_SCI_B4_FCR_BY_LL (R_SCI_B4_BASE + R_SCI_B_FCR_BY_LL_OFFSET) +#define R_SCI_B4_FCR_BY_LH (R_SCI_B4_BASE + R_SCI_B_FCR_BY_LH_OFFSET) +#define R_SCI_B4_FCR_HA_H (R_SCI_B4_BASE + R_SCI_B_FCR_HA_H_OFFSET) +#define R_SCI_B4_FCR_BY_HL (R_SCI_B4_BASE + R_SCI_B_FCR_BY_HL_OFFSET) +#define R_SCI_B4_FCR_BY_HH (R_SCI_B4_BASE + R_SCI_B_FCR_BY_HH_OFFSET) +#define R_SCI_B4_MCR (R_SCI_B4_BASE + R_SCI_B_MCR_OFFSET) +#define R_SCI_B4_MCR_HA_L (R_SCI_B4_BASE + R_SCI_B_MCR_HA_L_OFFSET) +#define R_SCI_B4_MCR_BY_LL (R_SCI_B4_BASE + R_SCI_B_MCR_BY_LL_OFFSET) +#define R_SCI_B4_MCR_BY_LH (R_SCI_B4_BASE + R_SCI_B_MCR_BY_LH_OFFSET) +#define R_SCI_B4_MCR_HA_H (R_SCI_B4_BASE + R_SCI_B_MCR_HA_H_OFFSET) +#define R_SCI_B4_MCR_BY_HL (R_SCI_B4_BASE + R_SCI_B_MCR_BY_HL_OFFSET) +#define R_SCI_B4_MCR_BY_HH (R_SCI_B4_BASE + R_SCI_B_MCR_BY_HH_OFFSET) +#define R_SCI_B4_DCR (R_SCI_B4_BASE + R_SCI_B_DCR_OFFSET) +#define R_SCI_B4_DCR_HA_L (R_SCI_B4_BASE + R_SCI_B_DCR_HA_L_OFFSET) +#define R_SCI_B4_DCR_BY_LL (R_SCI_B4_BASE + R_SCI_B_DCR_BY_LL_OFFSET) +#define R_SCI_B4_DCR_BY_LH (R_SCI_B4_BASE + R_SCI_B_DCR_BY_LH_OFFSET) +#define R_SCI_B4_DCR_HA_H (R_SCI_B4_BASE + R_SCI_B_DCR_HA_H_OFFSET) +#define R_SCI_B4_DCR_BY_HL (R_SCI_B4_BASE + R_SCI_B_DCR_BY_HL_OFFSET) +#define R_SCI_B4_XCR0 (R_SCI_B4_BASE + R_SCI_B_XCR0_OFFSET) +#define R_SCI_B4_XCR0_HA_L (R_SCI_B4_BASE + R_SCI_B_XCR0_HA_L_OFFSET) +#define R_SCI_B4_XCR0_BY_LL (R_SCI_B4_BASE + R_SCI_B_XCR0_BY_LL_OFFSET) +#define R_SCI_B4_XCR0_BY_LH (R_SCI_B4_BASE + R_SCI_B_XCR0_BY_LH_OFFSET) +#define R_SCI_B4_XCR0_HA_H (R_SCI_B4_BASE + R_SCI_B_XCR0_HA_H_OFFSET) +#define R_SCI_B4_XCR0_BY_HL (R_SCI_B4_BASE + R_SCI_B_XCR0_BY_HL_OFFSET) +#define R_SCI_B4_XCR0_BY_HH (R_SCI_B4_BASE + R_SCI_B_XCR0_BY_HH_OFFSET) +#define R_SCI_B4_XCR1 (R_SCI_B4_BASE + R_SCI_B_XCR1_OFFSET) +#define R_SCI_B4_XCR1_HA_L (R_SCI_B4_BASE + R_SCI_B_XCR1_HA_L_OFFSET) +#define R_SCI_B4_XCR1_BY_LL (R_SCI_B4_BASE + R_SCI_B_XCR1_BY_LL_OFFSET) +#define R_SCI_B4_XCR1_BY_LH (R_SCI_B4_BASE + R_SCI_B_XCR1_BY_LH_OFFSET) +#define R_SCI_B4_XCR1_HA_H (R_SCI_B4_BASE + R_SCI_B_XCR1_HA_H_OFFSET) +#define R_SCI_B4_XCR1_BY_HL (R_SCI_B4_BASE + R_SCI_B_XCR1_BY_HL_OFFSET) +#define R_SCI_B4_XCR1_BY_HH (R_SCI_B4_BASE + R_SCI_B_XCR1_BY_HH_OFFSET) +#define R_SCI_B4_XCR2 (R_SCI_B4_BASE + R_SCI_B_XCR2_OFFSET) +#define R_SCI_B4_XCR2_HA_L (R_SCI_B4_BASE + R_SCI_B_XCR2_HA_L_OFFSET) +#define R_SCI_B4_XCR2_BY_LL (R_SCI_B4_BASE + R_SCI_B_XCR2_BY_LL_OFFSET) +#define R_SCI_B4_XCR2_BY_LH (R_SCI_B4_BASE + R_SCI_B_XCR2_BY_LH_OFFSET) +#define R_SCI_B4_XCR2_HA_H (R_SCI_B4_BASE + R_SCI_B_XCR2_HA_H_OFFSET) +#define R_SCI_B4_XCR2_BY_HL (R_SCI_B4_BASE + R_SCI_B_XCR2_BY_HL_OFFSET) +#define R_SCI_B4_XCR2_BY_HH (R_SCI_B4_BASE + R_SCI_B_XCR2_BY_HH_OFFSET) +#define R_SCI_B4_CSR (R_SCI_B4_BASE + R_SCI_B_CSR_OFFSET) +#define R_SCI_B4_ISR (R_SCI_B4_BASE + R_SCI_B_ISR_OFFSET) +#define R_SCI_B4_FRSR (R_SCI_B4_BASE + R_SCI_B_FRSR_OFFSET) +#define R_SCI_B4_FTSR (R_SCI_B4_BASE + R_SCI_B_FTSR_OFFSET) +#define R_SCI_B4_MSR (R_SCI_B4_BASE + R_SCI_B_MSR_OFFSET) +#define R_SCI_B4_XSR0 (R_SCI_B4_BASE + R_SCI_B_XSR0_OFFSET) +#define R_SCI_B4_XSR1 (R_SCI_B4_BASE + R_SCI_B_XSR1_OFFSET) +#define R_SCI_B4_CFCLR (R_SCI_B4_BASE + R_SCI_B_CFCLR_OFFSET) +#define R_SCI_B4_CFCLR_HA_L (R_SCI_B4_BASE + R_SCI_B_CFCLR_HA_L_OFFSET) +#define R_SCI_B4_CFCLR_BY_LL (R_SCI_B4_BASE + R_SCI_B_CFCLR_BY_LL_OFFSET) +#define R_SCI_B4_CFCLR_HA_H (R_SCI_B4_BASE + R_SCI_B_CFCLR_HA_H_OFFSET) +#define R_SCI_B4_CFCLR_BY_HL (R_SCI_B4_BASE + R_SCI_B_CFCLR_BY_HL_OFFSET) +#define R_SCI_B4_CFCLR_BY_HH (R_SCI_B4_BASE + R_SCI_B_CFCLR_BY_HH_OFFSET) +#define R_SCI_B4_ICFCLR (R_SCI_B4_BASE + R_SCI_B_ICFCLR_OFFSET) +#define R_SCI_B4_ICFCLR_HA_L (R_SCI_B4_BASE + R_SCI_B_ICFCLR_HA_L_OFFSET) +#define R_SCI_B4_ICFCLR_BY_LL (R_SCI_B4_BASE + R_SCI_B_ICFCLR_BY_LL_OFFSET) +#define R_SCI_B4_FFCLR (R_SCI_B4_BASE + R_SCI_B_FFCLR_OFFSET) +#define R_SCI_B4_FFCLR_HA_L (R_SCI_B4_BASE + R_SCI_B_FFCLR_HA_L_OFFSET) +#define R_SCI_B4_FFCLR_BY_LL (R_SCI_B4_BASE + R_SCI_B_FFCLR_BY_LL_OFFSET) +#define R_SCI_B4_MFCLR (R_SCI_B4_BASE + R_SCI_B_MFCLR_OFFSET) +#define R_SCI_B4_MFCLR_HA_L (R_SCI_B4_BASE + R_SCI_B_MFCLR_HA_L_OFFSET) +#define R_SCI_B4_MFCLR_BY_LL (R_SCI_B4_BASE + R_SCI_B_MFCLR_BY_LL_OFFSET) +#define R_SCI_B4_XFCLR (R_SCI_B4_BASE + R_SCI_B_XFCLR_OFFSET) +#define R_SCI_B4_XFCLR_HA_L (R_SCI_B4_BASE + R_SCI_B_XFCLR_HA_L_OFFSET) +#define R_SCI_B4_XFCLR_BY_LH (R_SCI_B4_BASE + R_SCI_B_XFCLR_BY_LH_OFFSET) + +/* SCI_B9 Registers */ + +#define R_SCI_B9_RDR (R_SCI_B9_BASE + R_SCI_B_RDR_OFFSET) +#define R_SCI_B9_TDR (R_SCI_B9_BASE + R_SCI_B_TDR_OFFSET) +#define R_SCI_B9_TDR_HA_L (R_SCI_B9_BASE + R_SCI_B_TDR_HA_L_OFFSET) +#define R_SCI_B9_TDR_BY_LL (R_SCI_B9_BASE + R_SCI_B_TDR_BY_LL_OFFSET) +#define R_SCI_B9_TDR_BY_LH (R_SCI_B9_BASE + R_SCI_B_TDR_BY_LH_OFFSET) +#define R_SCI_B9_CCR0 (R_SCI_B9_BASE + R_SCI_B_CCR0_OFFSET) +#define R_SCI_B9_CCR0_HA_L (R_SCI_B9_BASE + R_SCI_B_CCR0_HA_L_OFFSET) +#define R_SCI_B9_CCR0_BY_LL (R_SCI_B9_BASE + R_SCI_B_CCR0_BY_LL_OFFSET) +#define R_SCI_B9_CCR0_BY_LH (R_SCI_B9_BASE + R_SCI_B_CCR0_BY_LH_OFFSET) +#define R_SCI_B9_CCR0_HA_H (R_SCI_B9_BASE + R_SCI_B_CCR0_HA_H_OFFSET) +#define R_SCI_B9_CCR0_BY_HL (R_SCI_B9_BASE + R_SCI_B_CCR0_BY_HL_OFFSET) +#define R_SCI_B9_CCR0_BY_HH (R_SCI_B9_BASE + R_SCI_B_CCR0_BY_HH_OFFSET) +#define R_SCI_B9_CCR1 (R_SCI_B9_BASE + R_SCI_B_CCR1_OFFSET) +#define R_SCI_B9_CCR1_HA_L (R_SCI_B9_BASE + R_SCI_B_CCR1_HA_L_OFFSET) +#define R_SCI_B9_CCR1_BY_LL (R_SCI_B9_BASE + R_SCI_B_CCR1_BY_LL_OFFSET) +#define R_SCI_B9_CCR1_BY_LH (R_SCI_B9_BASE + R_SCI_B_CCR1_BY_LH_OFFSET) +#define R_SCI_B9_CCR1_HA_H (R_SCI_B9_BASE + R_SCI_B_CCR1_HA_H_OFFSET) +#define R_SCI_B9_CCR1_BY_HL (R_SCI_B9_BASE + R_SCI_B_CCR1_BY_HL_OFFSET) +#define R_SCI_B9_CCR1_BY_HH (R_SCI_B9_BASE + R_SCI_B_CCR1_BY_HH_OFFSET) +#define R_SCI_B9_CCR2 (R_SCI_B9_BASE + R_SCI_B_CCR2_OFFSET) +#define R_SCI_B9_CCR2_HA_L (R_SCI_B9_BASE + R_SCI_B_CCR2_HA_L_OFFSET) +#define R_SCI_B9_CCR2_BY_LL (R_SCI_B9_BASE + R_SCI_B_CCR2_BY_LL_OFFSET) +#define R_SCI_B9_CCR2_BY_LH (R_SCI_B9_BASE + R_SCI_B_CCR2_BY_LH_OFFSET) +#define R_SCI_B9_CCR2_HA_H (R_SCI_B9_BASE + R_SCI_B_CCR2_HA_H_OFFSET) +#define R_SCI_B9_CCR2_BY_HL (R_SCI_B9_BASE + R_SCI_B_CCR2_BY_HL_OFFSET) +#define R_SCI_B9_CCR2_BY_HH (R_SCI_B9_BASE + R_SCI_B_CCR2_BY_HH_OFFSET) +#define R_SCI_B9_CCR3 (R_SCI_B9_BASE + R_SCI_B_CCR3_OFFSET) +#define R_SCI_B9_CCR3_HA_L (R_SCI_B9_BASE + R_SCI_B_CCR3_HA_L_OFFSET) +#define R_SCI_B9_CCR3_BY_LL (R_SCI_B9_BASE + R_SCI_B_CCR3_BY_LL_OFFSET) +#define R_SCI_B9_CCR3_BY_LH (R_SCI_B9_BASE + R_SCI_B_CCR3_BY_LH_OFFSET) +#define R_SCI_B9_CCR3_HA_H (R_SCI_B9_BASE + R_SCI_B_CCR3_HA_H_OFFSET) +#define R_SCI_B9_CCR3_BY_HL (R_SCI_B9_BASE + R_SCI_B_CCR3_BY_HL_OFFSET) +#define R_SCI_B9_CCR3_BY_HH (R_SCI_B9_BASE + R_SCI_B_CCR3_BY_HH_OFFSET) +#define R_SCI_B9_CCR4 (R_SCI_B9_BASE + R_SCI_B_CCR4_OFFSET) +#define R_SCI_B9_CCR4_HA_L (R_SCI_B9_BASE + R_SCI_B_CCR4_HA_L_OFFSET) +#define R_SCI_B9_CCR4_BY_LL (R_SCI_B9_BASE + R_SCI_B_CCR4_BY_LL_OFFSET) +#define R_SCI_B9_CCR4_BY_LH (R_SCI_B9_BASE + R_SCI_B_CCR4_BY_LH_OFFSET) +#define R_SCI_B9_CCR4_HA_H (R_SCI_B9_BASE + R_SCI_B_CCR4_HA_H_OFFSET) +#define R_SCI_B9_CCR4_BY_HL (R_SCI_B9_BASE + R_SCI_B_CCR4_BY_HL_OFFSET) +#define R_SCI_B9_CCR4_BY_HH (R_SCI_B9_BASE + R_SCI_B_CCR4_BY_HH_OFFSET) +#define R_SCI_B9_CESR (R_SCI_B9_BASE + R_SCI_B_CESR_OFFSET) +#define R_SCI_B9_HCR (R_SCI_B9_BASE + R_SCI_B_HCR_OFFSET) +#define R_SCI_B9_ICR (R_SCI_B9_BASE + R_SCI_B_ICR_OFFSET) +#define R_SCI_B9_ICR_HA_L (R_SCI_B9_BASE + R_SCI_B_ICR_HA_L_OFFSET) +#define R_SCI_B9_ICR_BY_LL (R_SCI_B9_BASE + R_SCI_B_ICR_BY_LL_OFFSET) +#define R_SCI_B9_ICR_BY_LH (R_SCI_B9_BASE + R_SCI_B_ICR_BY_LH_OFFSET) +#define R_SCI_B9_ICR_HA_H (R_SCI_B9_BASE + R_SCI_B_ICR_HA_H_OFFSET) +#define R_SCI_B9_ICR_BY_HL (R_SCI_B9_BASE + R_SCI_B_ICR_BY_HL_OFFSET) +#define R_SCI_B9_FCR (R_SCI_B9_BASE + R_SCI_B_FCR_OFFSET) +#define R_SCI_B9_FCR_HA_L (R_SCI_B9_BASE + R_SCI_B_FCR_HA_L_OFFSET) +#define R_SCI_B9_FCR_BY_LL (R_SCI_B9_BASE + R_SCI_B_FCR_BY_LL_OFFSET) +#define R_SCI_B9_FCR_BY_LH (R_SCI_B9_BASE + R_SCI_B_FCR_BY_LH_OFFSET) +#define R_SCI_B9_FCR_HA_H (R_SCI_B9_BASE + R_SCI_B_FCR_HA_H_OFFSET) +#define R_SCI_B9_FCR_BY_HL (R_SCI_B9_BASE + R_SCI_B_FCR_BY_HL_OFFSET) +#define R_SCI_B9_FCR_BY_HH (R_SCI_B9_BASE + R_SCI_B_FCR_BY_HH_OFFSET) +#define R_SCI_B9_MCR (R_SCI_B9_BASE + R_SCI_B_MCR_OFFSET) +#define R_SCI_B9_MCR_HA_L (R_SCI_B9_BASE + R_SCI_B_MCR_HA_L_OFFSET) +#define R_SCI_B9_MCR_BY_LL (R_SCI_B9_BASE + R_SCI_B_MCR_BY_LL_OFFSET) +#define R_SCI_B9_MCR_BY_LH (R_SCI_B9_BASE + R_SCI_B_MCR_BY_LH_OFFSET) +#define R_SCI_B9_MCR_HA_H (R_SCI_B9_BASE + R_SCI_B_MCR_HA_H_OFFSET) +#define R_SCI_B9_MCR_BY_HL (R_SCI_B9_BASE + R_SCI_B_MCR_BY_HL_OFFSET) +#define R_SCI_B9_MCR_BY_HH (R_SCI_B9_BASE + R_SCI_B_MCR_BY_HH_OFFSET) +#define R_SCI_B9_DCR (R_SCI_B9_BASE + R_SCI_B_DCR_OFFSET) +#define R_SCI_B9_DCR_HA_L (R_SCI_B9_BASE + R_SCI_B_DCR_HA_L_OFFSET) +#define R_SCI_B9_DCR_BY_LL (R_SCI_B9_BASE + R_SCI_B_DCR_BY_LL_OFFSET) +#define R_SCI_B9_DCR_BY_LH (R_SCI_B9_BASE + R_SCI_B_DCR_BY_LH_OFFSET) +#define R_SCI_B9_DCR_HA_H (R_SCI_B9_BASE + R_SCI_B_DCR_HA_H_OFFSET) +#define R_SCI_B9_DCR_BY_HL (R_SCI_B9_BASE + R_SCI_B_DCR_BY_HL_OFFSET) +#define R_SCI_B9_XCR0 (R_SCI_B9_BASE + R_SCI_B_XCR0_OFFSET) +#define R_SCI_B9_XCR0_HA_L (R_SCI_B9_BASE + R_SCI_B_XCR0_HA_L_OFFSET) +#define R_SCI_B9_XCR0_BY_LL (R_SCI_B9_BASE + R_SCI_B_XCR0_BY_LL_OFFSET) +#define R_SCI_B9_XCR0_BY_LH (R_SCI_B9_BASE + R_SCI_B_XCR0_BY_LH_OFFSET) +#define R_SCI_B9_XCR0_HA_H (R_SCI_B9_BASE + R_SCI_B_XCR0_HA_H_OFFSET) +#define R_SCI_B9_XCR0_BY_HL (R_SCI_B9_BASE + R_SCI_B_XCR0_BY_HL_OFFSET) +#define R_SCI_B9_XCR0_BY_HH (R_SCI_B9_BASE + R_SCI_B_XCR0_BY_HH_OFFSET) +#define R_SCI_B9_XCR1 (R_SCI_B9_BASE + R_SCI_B_XCR1_OFFSET) +#define R_SCI_B9_XCR1_HA_L (R_SCI_B9_BASE + R_SCI_B_XCR1_HA_L_OFFSET) +#define R_SCI_B9_XCR1_BY_LL (R_SCI_B9_BASE + R_SCI_B_XCR1_BY_LL_OFFSET) +#define R_SCI_B9_XCR1_BY_LH (R_SCI_B9_BASE + R_SCI_B_XCR1_BY_LH_OFFSET) +#define R_SCI_B9_XCR1_HA_H (R_SCI_B9_BASE + R_SCI_B_XCR1_HA_H_OFFSET) +#define R_SCI_B9_XCR1_BY_HL (R_SCI_B9_BASE + R_SCI_B_XCR1_BY_HL_OFFSET) +#define R_SCI_B9_XCR1_BY_HH (R_SCI_B9_BASE + R_SCI_B_XCR1_BY_HH_OFFSET) +#define R_SCI_B9_XCR2 (R_SCI_B9_BASE + R_SCI_B_XCR2_OFFSET) +#define R_SCI_B9_XCR2_HA_L (R_SCI_B9_BASE + R_SCI_B_XCR2_HA_L_OFFSET) +#define R_SCI_B9_XCR2_BY_LL (R_SCI_B9_BASE + R_SCI_B_XCR2_BY_LL_OFFSET) +#define R_SCI_B9_XCR2_BY_LH (R_SCI_B9_BASE + R_SCI_B_XCR2_BY_LH_OFFSET) +#define R_SCI_B9_XCR2_HA_H (R_SCI_B9_BASE + R_SCI_B_XCR2_HA_H_OFFSET) +#define R_SCI_B9_XCR2_BY_HL (R_SCI_B9_BASE + R_SCI_B_XCR2_BY_HL_OFFSET) +#define R_SCI_B9_XCR2_BY_HH (R_SCI_B9_BASE + R_SCI_B_XCR2_BY_HH_OFFSET) +#define R_SCI_B9_CSR (R_SCI_B9_BASE + R_SCI_B_CSR_OFFSET) +#define R_SCI_B9_ISR (R_SCI_B9_BASE + R_SCI_B_ISR_OFFSET) +#define R_SCI_B9_FRSR (R_SCI_B9_BASE + R_SCI_B_FRSR_OFFSET) +#define R_SCI_B9_FTSR (R_SCI_B9_BASE + R_SCI_B_FTSR_OFFSET) +#define R_SCI_B9_MSR (R_SCI_B9_BASE + R_SCI_B_MSR_OFFSET) +#define R_SCI_B9_XSR0 (R_SCI_B9_BASE + R_SCI_B_XSR0_OFFSET) +#define R_SCI_B9_XSR1 (R_SCI_B9_BASE + R_SCI_B_XSR1_OFFSET) +#define R_SCI_B9_CFCLR (R_SCI_B9_BASE + R_SCI_B_CFCLR_OFFSET) +#define R_SCI_B9_CFCLR_HA_L (R_SCI_B9_BASE + R_SCI_B_CFCLR_HA_L_OFFSET) +#define R_SCI_B9_CFCLR_BY_LL (R_SCI_B9_BASE + R_SCI_B_CFCLR_BY_LL_OFFSET) +#define R_SCI_B9_CFCLR_HA_H (R_SCI_B9_BASE + R_SCI_B_CFCLR_HA_H_OFFSET) +#define R_SCI_B9_CFCLR_BY_HL (R_SCI_B9_BASE + R_SCI_B_CFCLR_BY_HL_OFFSET) +#define R_SCI_B9_CFCLR_BY_HH (R_SCI_B9_BASE + R_SCI_B_CFCLR_BY_HH_OFFSET) +#define R_SCI_B9_ICFCLR (R_SCI_B9_BASE + R_SCI_B_ICFCLR_OFFSET) +#define R_SCI_B9_ICFCLR_HA_L (R_SCI_B9_BASE + R_SCI_B_ICFCLR_HA_L_OFFSET) +#define R_SCI_B9_ICFCLR_BY_LL (R_SCI_B9_BASE + R_SCI_B_ICFCLR_BY_LL_OFFSET) +#define R_SCI_B9_FFCLR (R_SCI_B9_BASE + R_SCI_B_FFCLR_OFFSET) +#define R_SCI_B9_FFCLR_HA_L (R_SCI_B9_BASE + R_SCI_B_FFCLR_HA_L_OFFSET) +#define R_SCI_B9_FFCLR_BY_LL (R_SCI_B9_BASE + R_SCI_B_FFCLR_BY_LL_OFFSET) +#define R_SCI_B9_MFCLR (R_SCI_B9_BASE + R_SCI_B_MFCLR_OFFSET) +#define R_SCI_B9_MFCLR_HA_L (R_SCI_B9_BASE + R_SCI_B_MFCLR_HA_L_OFFSET) +#define R_SCI_B9_MFCLR_BY_LL (R_SCI_B9_BASE + R_SCI_B_MFCLR_BY_LL_OFFSET) +#define R_SCI_B9_XFCLR (R_SCI_B9_BASE + R_SCI_B_XFCLR_OFFSET) +#define R_SCI_B9_XFCLR_HA_L (R_SCI_B9_BASE + R_SCI_B_XFCLR_HA_L_OFFSET) +#define R_SCI_B9_XFCLR_BY_LH (R_SCI_B9_BASE + R_SCI_B_XFCLR_BY_LH_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Received Data Register (32-bits) *****************************************/ + +#define R_SCI_B_RDR_RDAT_SHIFT (0) +#define R_SCI_B_RDR_RDAT_MASK (0x1ff) +#define R_SCI_B_RDR_MPB (1 << 9) /* 200: Multiprocessor bit flag */ +#define R_SCI_B_RDR_DR (1 << 10) /* 400: Receive data ready flag */ +#define R_SCI_B_RDR_FPER (1 << 11) /* 800: Parity error flag */ +#define R_SCI_B_RDR_FFER (1 << 12) /* 1000: Framing error flag */ +#define R_SCI_B_RDR_ORER (1 << 24) /* 1000000: Overrun error flag */ +#define R_SCI_B_RDR_PER (1 << 27) /* 8000000: Parity Error Flag */ +#define R_SCI_B_RDR_FER (1 << 28) /* 10000000: Framing Error Flag */ + +/* Transmission Data Register (32-bits) *************************************/ + +#define R_SCI_B_TDR_TDAT_SHIFT (0) +#define R_SCI_B_TDR_TDAT_MASK (0x1ff) +#define R_SCI_B_TDR_MPBT (1 << 9) /* 200: Multi-processor transfer bit flag */ +#define R_SCI_B_TDR_TSYNC (1 << 12) /* 1000: Transmit sync data bit. */ + +/* Transmission Data Register (16-bits) *************************************/ + +#define R_SCI_B_TDR_HA_L_TDAT_SHIFT (0) +#define R_SCI_B_TDR_HA_L_TDAT_MASK (0x1ff) +#define R_SCI_B_TDR_HA_L_MPBT (1 << 9) /* 200: Multi-processor transfer bit flag */ +#define R_SCI_B_TDR_HA_L_TSYNC (1 << 12) /* 1000: Transmit sync data bit. */ + +/* Transmission Data Register (8-bits) **************************************/ + +#define R_SCI_B_TDR_BY_LL_TDAT_SHIFT (0) +#define R_SCI_B_TDR_BY_LL_TDAT_MASK (0xff) + +/* Transmission Data Register (8-bits) **************************************/ + +#define R_SCI_B_TDR_BY_LH_TDAT (1 << 0) /* 01: Transmission data. */ +#define R_SCI_B_TDR_BY_LH_MPBT (1 << 1) /* 02: Multi-processor transfer bit flag */ +#define R_SCI_B_TDR_BY_LH_TSYNC (1 << 4) /* 10: Transmit sync data bit. */ + +/* Common Control Register 0 (32-bits) **************************************/ + +#define R_SCI_B_CCR0_RE (1 << 0) /* 01: Receive Enable */ +#define R_SCI_B_CCR0_TE (1 << 4) /* 10: Transmit Enable */ +#define R_SCI_B_CCR0_MPIE (1 << 8) /* 100: Multi-Processor Interrupt Enable */ +#define R_SCI_B_CCR0_DCME (1 << 9) /* 200: Data Compare Match Enable */ +#define R_SCI_B_CCR0_IDSEL (1 << 10) /* 400: ID frame select Bit */ +#define R_SCI_B_CCR0_RIE (1 << 16) /* 10000: Receive Interrupt Enable */ +#define R_SCI_B_CCR0_TIE (1 << 20) /* 100000: Transmit Interrupt Enable */ +#define R_SCI_B_CCR0_TEIE (1 << 21) /* 200000: Transmit End Interrupt Enable */ +#define R_SCI_B_CCR0_SSE (1 << 24) /* 1000000: SSn# Pin Function Enable */ + +/* Common Control Register 0 (16-bits) **************************************/ + +#define R_SCI_B_CCR0_HA_L_RE (1 << 0) /* 01: Receive Enable */ +#define R_SCI_B_CCR0_HA_L_TE (1 << 4) /* 10: Transmit Enable */ +#define R_SCI_B_CCR0_HA_L_MPIE (1 << 8) /* 100: Multi-Processor Interrupt Enable */ +#define R_SCI_B_CCR0_HA_L_DCME (1 << 9) /* 200: Data Compare Match Enable */ +#define R_SCI_B_CCR0_HA_L_IDSEL (1 << 10) /* 400: ID frame select Bit */ + +/* Common Control Register 0 (8-bits) ***************************************/ + +#define R_SCI_B_CCR0_BY_LL_RE (1 << 0) /* 01: Receive Enable */ +#define R_SCI_B_CCR0_BY_LL_TE (1 << 4) /* 10: Transmit Enable */ + +/* Common Control Register 0 (8-bits) ***************************************/ + +#define R_SCI_B_CCR0_BY_LH_MPIE (1 << 0) /* 01: Multi-Processor Interrupt Enable */ +#define R_SCI_B_CCR0_BY_LH_DCME (1 << 1) /* 02: Data Compare Match Enable */ +#define R_SCI_B_CCR0_BY_LH_IDSEL (1 << 2) /* 04: ID frame select Bit */ + +/* Common Control Register 0 (16-bits) **************************************/ + +#define R_SCI_B_CCR0_HA_H_RIE (1 << 0) /* 01: Receive Interrupt Enable */ +#define R_SCI_B_CCR0_HA_H_TIE (1 << 4) /* 10: Transmit Interrupt Enable */ +#define R_SCI_B_CCR0_HA_H_TEIE (1 << 5) /* 20: Transmit End Interrupt Enable */ +#define R_SCI_B_CCR0_HA_H_SSE (1 << 8) /* 100: SSn# Pin Function Enable */ + +/* Common Control Register 0 (8-bits) ***************************************/ + +#define R_SCI_B_CCR0_BY_HL_RIE (1 << 0) /* 01: Receive Interrupt Enable */ +#define R_SCI_B_CCR0_BY_HL_TIE (1 << 4) /* 10: Transmit Interrupt Enable */ +#define R_SCI_B_CCR0_BY_HL_TEIE (1 << 5) /* 20: Transmit End Interrupt Enable */ + +/* Common Control Register 0 (8-bits) ***************************************/ + +#define R_SCI_B_CCR0_BY_HH_SSE (1 << 0) /* 01: SSn# Pin Function Enable */ + +/* Common Control Register 1 (32-bits) **************************************/ + +#define R_SCI_B_CCR1_CTSE (1 << 0) /* 01: CTS Enable */ +#define R_SCI_B_CCR1_CTSPEN (1 << 1) /* 02: CTS external terminal enable bit. */ +#define R_SCI_B_CCR1_SPB2DT (1 << 4) /* 10: Serial port break data select bit */ +#define R_SCI_B_CCR1_SPB2IO (1 << 5) /* 20: Serial port break I/O bit */ +#define R_SCI_B_CCR1_PE (1 << 8) /* 100: Parity Enable */ +#define R_SCI_B_CCR1_PM (1 << 9) /* 200: Parity Mode */ +#define R_SCI_B_CCR1_TINV (1 << 12) /* 1000: TxD invert bit */ +#define R_SCI_B_CCR1_RINV (1 << 13) /* 2000: RxD invert bit */ +#define R_SCI_B_CCR1_SPLP (1 << 16) /* 10000: Serial communication Port LoopBack */ +#define R_SCI_B_CCR1_SHARPS (1 << 20) /* 100000: TxD/RxD Pin Multiplexing Select */ +#define R_SCI_B_CCR1_NFCS_SHIFT (24) +#define R_SCI_B_CCR1_NFCS_MASK (0x7) +# define R_SCI_B_CCR1_NFCS_V000 (0 << R_SCI_B_CCR1_NFCS_SHIFT) /* The base clock divided by 1 is used with the noise filter. */ +# define R_SCI_B_CCR1_NFCS_V001 (1 << R_SCI_B_CCR1_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 1 is used */ +# define R_SCI_B_CCR1_NFCS_V010 (2 << R_SCI_B_CCR1_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 2 is used */ +# define R_SCI_B_CCR1_NFCS_V011 (3 << R_SCI_B_CCR1_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 4 is used */ +# define R_SCI_B_CCR1_NFCS_V100 (4 << R_SCI_B_CCR1_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 8 is used */ +#define R_SCI_B_CCR1_NFEN (1 << 28) /* 10000000: Digital Noise Filter Function Enable */ + +/* Common Control Register 1 (16-bits) **************************************/ + +#define R_SCI_B_CCR1_HA_L_CTSE (1 << 0) /* 01: CTS Enable */ +#define R_SCI_B_CCR1_HA_L_CTSPEN (1 << 1) /* 02: CTS external terminal enable bit. */ +#define R_SCI_B_CCR1_HA_L_SPB2DT (1 << 4) /* 10: Serial port break data select bit */ +#define R_SCI_B_CCR1_HA_L_SPB2IO (1 << 5) /* 20: Serial port break I/O bit */ +#define R_SCI_B_CCR1_HA_L_PE (1 << 8) /* 100: Parity Enable */ +#define R_SCI_B_CCR1_HA_L_PM (1 << 9) /* 200: Parity Mode */ +#define R_SCI_B_CCR1_HA_L_TINV (1 << 12) /* 1000: TxD invert bit */ +#define R_SCI_B_CCR1_HA_L_RINV (1 << 13) /* 2000: RxD invert bit */ + +/* Common Control Register 1 (8-bits) ***************************************/ + +#define R_SCI_B_CCR1_BY_LL_CTSE (1 << 0) /* 01: CTS Enable */ +#define R_SCI_B_CCR1_BY_LL_CTSPEN (1 << 1) /* 02: CTS external terminal enable bit. */ +#define R_SCI_B_CCR1_BY_LL_SPB2DT (1 << 4) /* 10: Serial port break data select bit */ +#define R_SCI_B_CCR1_BY_LL_SPB2IO (1 << 5) /* 20: Serial port break I/O bit */ + +/* Common Control Register 1 (8-bits) ***************************************/ + +#define R_SCI_B_CCR1_BY_LH_PE (1 << 0) /* 01: Parity Enable */ +#define R_SCI_B_CCR1_BY_LH_PM (1 << 1) /* 02: Parity Mode */ +#define R_SCI_B_CCR1_BY_LH_TINV (1 << 4) /* 10: TxD invert bit */ +#define R_SCI_B_CCR1_BY_LH_RINV (1 << 5) /* 20: RxD invert bit */ + +/* Common Control Register 1 (16-bits) **************************************/ + +#define R_SCI_B_CCR1_HA_H_SPLP (1 << 0) /* 01: Serial communication Port LoopBack */ +#define R_SCI_B_CCR1_HA_H_SHARPS (1 << 4) /* 10: TxD/RxD Pin Multiplexing Select */ +#define R_SCI_B_CCR1_HA_H_NFCS_SHIFT (8) +#define R_SCI_B_CCR1_HA_H_NFCS_MASK (0x7) +# define R_SCI_B_CCR1_HA_H_NFCS_V000 (0 << R_SCI_B_CCR1_HA_H_NFCS_SHIFT) /* The base clock divided by 1 is used with the noise filter. */ +# define R_SCI_B_CCR1_HA_H_NFCS_V001 (1 << R_SCI_B_CCR1_HA_H_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 1 is used */ +# define R_SCI_B_CCR1_HA_H_NFCS_V010 (2 << R_SCI_B_CCR1_HA_H_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 2 is used */ +# define R_SCI_B_CCR1_HA_H_NFCS_V011 (3 << R_SCI_B_CCR1_HA_H_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 4 is used */ +# define R_SCI_B_CCR1_HA_H_NFCS_V100 (4 << R_SCI_B_CCR1_HA_H_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 8 is used */ +#define R_SCI_B_CCR1_HA_H_NFEN (1 << 12) /* 1000: Digital Noise Filter Function Enable */ + +/* Common Control Register 1 (8-bits) ***************************************/ + +#define R_SCI_B_CCR1_BY_HL_SPLP (1 << 0) /* 01: Serial communication Port LoopBack */ +#define R_SCI_B_CCR1_BY_HL_SHARPS (1 << 4) /* 10: TxD/RxD Pin Multiplexing Select */ + +/* Common Control Register 1 (8-bits) ***************************************/ + +#define R_SCI_B_CCR1_BY_HH_NFCS_SHIFT (0) +#define R_SCI_B_CCR1_BY_HH_NFCS_MASK (0x7) +# define R_SCI_B_CCR1_BY_HH_NFCS_V000 (0 << R_SCI_B_CCR1_BY_HH_NFCS_SHIFT) /* The base clock divided by 1 is used with the noise filter. */ +# define R_SCI_B_CCR1_BY_HH_NFCS_V001 (1 << R_SCI_B_CCR1_BY_HH_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 1 is used */ +# define R_SCI_B_CCR1_BY_HH_NFCS_V010 (2 << R_SCI_B_CCR1_BY_HH_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 2 is used */ +# define R_SCI_B_CCR1_BY_HH_NFCS_V011 (3 << R_SCI_B_CCR1_BY_HH_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 4 is used */ +# define R_SCI_B_CCR1_BY_HH_NFCS_V100 (4 << R_SCI_B_CCR1_BY_HH_NFCS_SHIFT) /* The on-chip baud rate generator clock divided by 8 is used */ +#define R_SCI_B_CCR1_BY_HH_NFEN (1 << 4) /* 10: Digital Noise Filter Function Enable */ + +/* Common Control Register 2 (32-bits) **************************************/ + +#define R_SCI_B_CCR2_BCP_SHIFT (0) +#define R_SCI_B_CCR2_BCP_MASK (0x7) +#define R_SCI_B_CCR2_BGDM (1 << 4) /* 10: Baud Rate Generator Double-Speed Mode Select */ +#define R_SCI_B_CCR2_ABCS (1 << 5) /* 20: Asynchronous Mode Base Clock Select */ +#define R_SCI_B_CCR2_ABCSE (1 << 6) /* 40: Asynchronous Mode Base Clock Select1 */ +#define R_SCI_B_CCR2_BRR_SHIFT (8) +#define R_SCI_B_CCR2_BRR_MASK (0xff) +#define R_SCI_B_CCR2_BRME (1 << 16) /* 10000: Bit Modulation Enable */ +#define R_SCI_B_CCR2_CKS_SHIFT (20) +#define R_SCI_B_CCR2_CKS_MASK (0x3) +# define R_SCI_B_CCR2_CKS_TCLK_CLOCK (0 << R_SCI_B_CCR2_CKS_SHIFT) /* TCLK clock */ +# define R_SCI_B_CCR2_CKS_TCLK_4_CLOCK (1 << R_SCI_B_CCR2_CKS_SHIFT) /* TCLK/4 clock */ +# define R_SCI_B_CCR2_CKS_TCLK_16_CLOCK (2 << R_SCI_B_CCR2_CKS_SHIFT) /* TCLK/16 clock */ +# define R_SCI_B_CCR2_CKS_TCLK_64_CLOCK (3 << R_SCI_B_CCR2_CKS_SHIFT) /* TCLK/64 clock */ +#define R_SCI_B_CCR2_MDDR_SHIFT (24) +#define R_SCI_B_CCR2_MDDR_MASK (0xff) + +/* Common Control Register 2 (16-bits) **************************************/ + +#define R_SCI_B_CCR2_HA_L_BCP_SHIFT (0) +#define R_SCI_B_CCR2_HA_L_BCP_MASK (0x7) +#define R_SCI_B_CCR2_HA_L_BGDM (1 << 4) /* 10: Baud Rate Generator Double-Speed Mode Select */ +#define R_SCI_B_CCR2_HA_L_ABCS (1 << 5) /* 20: Asynchronous Mode Base Clock Select */ +#define R_SCI_B_CCR2_HA_L_ABCSE (1 << 6) /* 40: Asynchronous Mode Base Clock Select1 */ +#define R_SCI_B_CCR2_HA_L_BRR_SHIFT (8) +#define R_SCI_B_CCR2_HA_L_BRR_MASK (0xff) + +/* Common Control Register 2 (8-bits) ***************************************/ + +#define R_SCI_B_CCR2_BY_LL_BCP_SHIFT (0) +#define R_SCI_B_CCR2_BY_LL_BCP_MASK (0x7) +#define R_SCI_B_CCR2_BY_LL_BGDM (1 << 4) /* 10: Baud Rate Generator Double-Speed Mode Select */ +#define R_SCI_B_CCR2_BY_LL_ABCS (1 << 5) /* 20: Asynchronous Mode Base Clock Select */ +#define R_SCI_B_CCR2_BY_LL_ABCSE (1 << 6) /* 40: Asynchronous Mode Base Clock Select1 */ + +/* Common Control Register 2 (8-bits) ***************************************/ + +#define R_SCI_B_CCR2_BY_LH_BRR_SHIFT (0) +#define R_SCI_B_CCR2_BY_LH_BRR_MASK (0xff) + +/* Common Control Register 2 (16-bits) **************************************/ + +#define R_SCI_B_CCR2_HA_H_BRME (1 << 0) /* 01: Bit Modulation Enable */ +#define R_SCI_B_CCR2_HA_H_CKS_SHIFT (4) +#define R_SCI_B_CCR2_HA_H_CKS_MASK (0x3) +# define R_SCI_B_CCR2_HA_H_CKS_TCLK_CLOCK (0 << R_SCI_B_CCR2_HA_H_CKS_SHIFT) /* TCLK clock */ +# define R_SCI_B_CCR2_HA_H_CKS_TCLK_4_CLOCK (1 << R_SCI_B_CCR2_HA_H_CKS_SHIFT) /* TCLK/4 clock */ +# define R_SCI_B_CCR2_HA_H_CKS_TCLK_16_CLOCK (2 << R_SCI_B_CCR2_HA_H_CKS_SHIFT) /* TCLK/16 clock */ +# define R_SCI_B_CCR2_HA_H_CKS_TCLK_64_CLOCK (3 << R_SCI_B_CCR2_HA_H_CKS_SHIFT) /* TCLK/64 clock */ +#define R_SCI_B_CCR2_HA_H_MDDR_SHIFT (8) +#define R_SCI_B_CCR2_HA_H_MDDR_MASK (0xff) + +/* Common Control Register 2 (8-bits) ***************************************/ + +#define R_SCI_B_CCR2_BY_HL_BRME (1 << 0) /* 01: Bit Modulation Enable */ +#define R_SCI_B_CCR2_BY_HL_CKS_SHIFT (4) +#define R_SCI_B_CCR2_BY_HL_CKS_MASK (0x3) +# define R_SCI_B_CCR2_BY_HL_CKS_TCLK_CLOCK (0 << R_SCI_B_CCR2_BY_HL_CKS_SHIFT) /* TCLK clock */ +# define R_SCI_B_CCR2_BY_HL_CKS_TCLK_4_CLOCK (1 << R_SCI_B_CCR2_BY_HL_CKS_SHIFT) /* TCLK/4 clock */ +# define R_SCI_B_CCR2_BY_HL_CKS_TCLK_16_CLOCK (2 << R_SCI_B_CCR2_BY_HL_CKS_SHIFT) /* TCLK/16 clock */ +# define R_SCI_B_CCR2_BY_HL_CKS_TCLK_64_CLOCK (3 << R_SCI_B_CCR2_BY_HL_CKS_SHIFT) /* TCLK/64 clock */ + +/* Common Control Register 2 (8-bits) ***************************************/ + +#define R_SCI_B_CCR2_BY_HH_MDDR_SHIFT (0) +#define R_SCI_B_CCR2_BY_HH_MDDR_MASK (0xff) + +/* Common Control Register 3 (32-bits) **************************************/ + +#define R_SCI_B_CCR3_CPHA (1 << 0) /* 01: Clock Phase Setting */ +#define R_SCI_B_CCR3_CPOL (1 << 1) /* 02: Clock Polarity Setting */ +#define R_SCI_B_CCR3_BPEN (1 << 7) /* 80: Synchronizer ByPass Enable */ +#define R_SCI_B_CCR3_CHR_SHIFT (8) +#define R_SCI_B_CCR3_CHR_MASK (0x3) +# define R_SCI_B_CCR3_CHR_V00 (0 << R_SCI_B_CCR3_CHR_SHIFT) /* Transmit/receive in 9-bit length */ +# define R_SCI_B_CCR3_CHR_V01 (1 << R_SCI_B_CCR3_CHR_SHIFT) /* Transmit/receive in 9-bit length */ +# define R_SCI_B_CCR3_CHR_V10 (2 << R_SCI_B_CCR3_CHR_SHIFT) /* Transmit/receive in 8-bit length */ +# define R_SCI_B_CCR3_CHR_V11 (3 << R_SCI_B_CCR3_CHR_SHIFT) /* Transmit/receive in 7-bit length */ +#define R_SCI_B_CCR3_LSBF (1 << 12) /* 1000: LSB first select bit */ +#define R_SCI_B_CCR3_SINV (1 << 13) /* 2000: Transmitted/Received Data Invert */ +#define R_SCI_B_CCR3_STP (1 << 14) /* 4000: Stop Bit Length */ +#define R_SCI_B_CCR3_RXDESEL (1 << 15) /* 8000: Asynchronous Start Bit Edge Detection Select */ +#define R_SCI_B_CCR3_MOD_SHIFT (16) +#define R_SCI_B_CCR3_MOD_MASK (0x7) +# define R_SCI_B_CCR3_MOD_ASYNCHRONOUS (0 << R_SCI_B_CCR3_MOD_SHIFT) /* Asynchronous */ +# define R_SCI_B_CCR3_MOD_SMART_CARD_INTERFACE (1 << R_SCI_B_CCR3_MOD_SHIFT) /* Smart card interface */ +# define R_SCI_B_CCR3_MOD_CLOCK_SNCHRONOUS (2 << R_SCI_B_CCR3_MOD_SHIFT) /* Clock snchronous */ +# define R_SCI_B_CCR3_MOD_SIMPLE_SPI (3 << R_SCI_B_CCR3_MOD_SHIFT) /* Simple-SPI */ +# define R_SCI_B_CCR3_MOD_SIMPLE_I2C (4 << R_SCI_B_CCR3_MOD_SHIFT) /* Simple-I2C */ +# define R_SCI_B_CCR3_MOD_MANCHESTER (5 << R_SCI_B_CCR3_MOD_SHIFT) /* Manchester */ +# define R_SCI_B_CCR3_MOD_SIMPLE_LIN (6 << R_SCI_B_CCR3_MOD_SHIFT) /* Simple-LIN */ +# define R_SCI_B_CCR3_MOD_PROHIBIT (7 << R_SCI_B_CCR3_MOD_SHIFT) /* Prohibit */ +#define R_SCI_B_CCR3_MP (1 << 19) /* 80000: Multi-Processor mode */ +#define R_SCI_B_CCR3_FM (1 << 20) /* 100000: FIFO Mode Select */ +#define R_SCI_B_CCR3_DEN (1 << 21) /* 200000: Driver control Enable */ +#define R_SCI_B_CCR3_CKE_SHIFT (24) +#define R_SCI_B_CCR3_CKE_MASK (0x3) +# define R_SCI_B_CCR3_CKE_V00 (0 << R_SCI_B_CCR3_CKE_SHIFT) /* On-chip baud rate generator / On-chip baud rate generator The SCKn pin functions as I/O port. / Output disabled (The SCKn pin is available for use as an I/O port */ +# define R_SCI_B_CCR3_CKE_V01 (1 << R_SCI_B_CCR3_CKE_SHIFT) /* On-chip baud rate generator */ +# define R_SCI_B_CCR3_CKE_CLOCK_OUTPUT (1 << R_SCI_B_CCR3_CKE_SHIFT) /* Clock output */ +# define R_SCI_B_CCR3_CKE_OUTPUT_FIXED_LOW (0 << R_SCI_B_CCR3_CKE_SHIFT) /* Output fixed low */ +# define R_SCI_B_CCR3_CKE_OUTPUT_FIXED_HIGH (2 << R_SCI_B_CCR3_CKE_SHIFT) /* Output fixed high */ +#define R_SCI_B_CCR3_ACS0 (1 << 26) /* 4000000: Asynchronous Mode Clock Source Select */ +#define R_SCI_B_CCR3_GM (1 << 28) /* 10000000: GSM Mode */ +#define R_SCI_B_CCR3_BLK (1 << 29) /* 20000000: Block transfer mode */ + +/* Common Control Register 3 (16-bits) **************************************/ + +#define R_SCI_B_CCR3_HA_L_CPHA (1 << 0) /* 01: Clock Phase Setting */ +#define R_SCI_B_CCR3_HA_L_CPOL (1 << 1) /* 02: Clock Polarity Setting */ +#define R_SCI_B_CCR3_HA_L_BPEN (1 << 7) /* 80: Synchronizer ByPass Enable */ +#define R_SCI_B_CCR3_HA_L_CHR_SHIFT (8) +#define R_SCI_B_CCR3_HA_L_CHR_MASK (0x3) +# define R_SCI_B_CCR3_HA_L_CHR_V00 (0 << R_SCI_B_CCR3_HA_L_CHR_SHIFT) /* Transmit/receive in 9-bit length */ +# define R_SCI_B_CCR3_HA_L_CHR_V01 (1 << R_SCI_B_CCR3_HA_L_CHR_SHIFT) /* Transmit/receive in 9-bit length */ +# define R_SCI_B_CCR3_HA_L_CHR_V10 (2 << R_SCI_B_CCR3_HA_L_CHR_SHIFT) /* Transmit/receive in 8-bit length */ +# define R_SCI_B_CCR3_HA_L_CHR_V11 (3 << R_SCI_B_CCR3_HA_L_CHR_SHIFT) /* Transmit/receive in 7-bit length */ +#define R_SCI_B_CCR3_HA_L_LSBF (1 << 12) /* 1000: LSB first select bit */ +#define R_SCI_B_CCR3_HA_L_SINV (1 << 13) /* 2000: Transmitted/Received Data Invert */ +#define R_SCI_B_CCR3_HA_L_STP (1 << 14) /* 4000: Stop Bit Length */ +#define R_SCI_B_CCR3_HA_L_RXDESEL (1 << 15) /* 8000: Asynchronous Start Bit Edge Detection Select */ + +/* Common Control Register 3 (8-bits) ***************************************/ + +#define R_SCI_B_CCR3_BY_LL_CPHA (1 << 0) /* 01: Clock Phase Setting */ +#define R_SCI_B_CCR3_BY_LL_CPOL (1 << 1) /* 02: Clock Polarity Setting */ +#define R_SCI_B_CCR3_BY_LL_BPEN (1 << 7) /* 80: Synchronizer ByPass Enable */ + +/* Common Control Register 3 (8-bits) ***************************************/ + +#define R_SCI_B_CCR3_BY_LH_CHR_SHIFT (0) +#define R_SCI_B_CCR3_BY_LH_CHR_MASK (0x3) +# define R_SCI_B_CCR3_BY_LH_CHR_V00 (0 << R_SCI_B_CCR3_BY_LH_CHR_SHIFT) /* Transmit/receive in 9-bit length */ +# define R_SCI_B_CCR3_BY_LH_CHR_V01 (1 << R_SCI_B_CCR3_BY_LH_CHR_SHIFT) /* Transmit/receive in 9-bit length */ +# define R_SCI_B_CCR3_BY_LH_CHR_V10 (2 << R_SCI_B_CCR3_BY_LH_CHR_SHIFT) /* Transmit/receive in 8-bit length */ +# define R_SCI_B_CCR3_BY_LH_CHR_V11 (3 << R_SCI_B_CCR3_BY_LH_CHR_SHIFT) /* Transmit/receive in 7-bit length */ +#define R_SCI_B_CCR3_BY_LH_LSBF (1 << 4) /* 10: LSB first select bit */ +#define R_SCI_B_CCR3_BY_LH_SINV (1 << 5) /* 20: Transmitted/Received Data Invert */ +#define R_SCI_B_CCR3_BY_LH_STP (1 << 6) /* 40: Stop Bit Length */ +#define R_SCI_B_CCR3_BY_LH_RXDESEL (1 << 7) /* 80: Asynchronous Start Bit Edge Detection Select */ + +/* Common Control Register 3 (16-bits) **************************************/ + +#define R_SCI_B_CCR3_HA_H_MOD_SHIFT (0) +#define R_SCI_B_CCR3_HA_H_MOD_MASK (0x7) +# define R_SCI_B_CCR3_HA_H_MOD_ASYNCHRONOUS (0 << R_SCI_B_CCR3_HA_H_MOD_SHIFT) /* Asynchronous */ +# define R_SCI_B_CCR3_HA_H_MOD_SMART_CARD_INTERFACE (1 << R_SCI_B_CCR3_HA_H_MOD_SHIFT) /* Smart card interface */ +# define R_SCI_B_CCR3_HA_H_MOD_CLOCK_SNCHRONOUS (2 << R_SCI_B_CCR3_HA_H_MOD_SHIFT) /* Clock snchronous */ +# define R_SCI_B_CCR3_HA_H_MOD_SIMPLE_SPI (3 << R_SCI_B_CCR3_HA_H_MOD_SHIFT) /* Simple-SPI */ +# define R_SCI_B_CCR3_HA_H_MOD_SIMPLE_I2C (4 << R_SCI_B_CCR3_HA_H_MOD_SHIFT) /* Simple-I2C */ +# define R_SCI_B_CCR3_HA_H_MOD_MANCHESTER (5 << R_SCI_B_CCR3_HA_H_MOD_SHIFT) /* Manchester */ +# define R_SCI_B_CCR3_HA_H_MOD_SIMPLE_LIN (6 << R_SCI_B_CCR3_HA_H_MOD_SHIFT) /* Simple-LIN */ +# define R_SCI_B_CCR3_HA_H_MOD_PROHIBIT (7 << R_SCI_B_CCR3_HA_H_MOD_SHIFT) /* Prohibit */ +#define R_SCI_B_CCR3_HA_H_MP (1 << 3) /* 08: Multi-Processor mode */ +#define R_SCI_B_CCR3_HA_H_FM (1 << 4) /* 10: FIFO Mode Select */ +#define R_SCI_B_CCR3_HA_H_DEN (1 << 5) /* 20: Driver control Enable */ +#define R_SCI_B_CCR3_HA_H_CKE_SHIFT (8) +#define R_SCI_B_CCR3_HA_H_CKE_MASK (0x3) +# define R_SCI_B_CCR3_HA_H_CKE_V00 (0 << R_SCI_B_CCR3_HA_H_CKE_SHIFT) /* On-chip baud rate generator / On-chip baud rate generator The SCKn pin functions as I/O port. / Output disabled (The SCKn pin is available for use as an I/O port */ +# define R_SCI_B_CCR3_HA_H_CKE_V01 (1 << R_SCI_B_CCR3_HA_H_CKE_SHIFT) /* On-chip baud rate generator */ +# define R_SCI_B_CCR3_HA_H_CKE_CLOCK_OUTPUT (1 << R_SCI_B_CCR3_HA_H_CKE_SHIFT) /* Clock output */ +# define R_SCI_B_CCR3_HA_H_CKE_OUTPUT_FIXED_LOW (0 << R_SCI_B_CCR3_HA_H_CKE_SHIFT) /* Output fixed low */ +# define R_SCI_B_CCR3_HA_H_CKE_OUTPUT_FIXED_HIGH (2 << R_SCI_B_CCR3_HA_H_CKE_SHIFT) /* Output fixed high */ +#define R_SCI_B_CCR3_HA_H_ACS0 (1 << 10) /* 400: Asynchronous Mode Clock Source Select */ +#define R_SCI_B_CCR3_HA_H_GM (1 << 12) /* 1000: GSM Mode */ +#define R_SCI_B_CCR3_HA_H_BLK (1 << 13) /* 2000: Block transfer mode */ + +/* Common Control Register 3 (8-bits) ***************************************/ + +#define R_SCI_B_CCR3_BY_HL_MOD_SHIFT (0) +#define R_SCI_B_CCR3_BY_HL_MOD_MASK (0x7) +# define R_SCI_B_CCR3_BY_HL_MOD_ASYNCHRONOUS (0 << R_SCI_B_CCR3_BY_HL_MOD_SHIFT) /* Asynchronous */ +# define R_SCI_B_CCR3_BY_HL_MOD_SMART_CARD_INTERFACE (1 << R_SCI_B_CCR3_BY_HL_MOD_SHIFT) /* Smart card interface */ +# define R_SCI_B_CCR3_BY_HL_MOD_CLOCK_SNCHRONOUS (2 << R_SCI_B_CCR3_BY_HL_MOD_SHIFT) /* Clock snchronous */ +# define R_SCI_B_CCR3_BY_HL_MOD_SIMPLE_SPI (3 << R_SCI_B_CCR3_BY_HL_MOD_SHIFT) /* Simple-SPI */ +# define R_SCI_B_CCR3_BY_HL_MOD_SIMPLE_I2C (4 << R_SCI_B_CCR3_BY_HL_MOD_SHIFT) /* Simple-I2C */ +# define R_SCI_B_CCR3_BY_HL_MOD_MANCHESTER (5 << R_SCI_B_CCR3_BY_HL_MOD_SHIFT) /* Manchester */ +# define R_SCI_B_CCR3_BY_HL_MOD_SIMPLE_LIN (6 << R_SCI_B_CCR3_BY_HL_MOD_SHIFT) /* Simple-LIN */ +# define R_SCI_B_CCR3_BY_HL_MOD_PROHIBIT (7 << R_SCI_B_CCR3_BY_HL_MOD_SHIFT) /* Prohibit */ +#define R_SCI_B_CCR3_BY_HL_MP (1 << 3) /* 08: Multi-Processor mode */ +#define R_SCI_B_CCR3_BY_HL_FM (1 << 4) /* 10: FIFO Mode Select */ +#define R_SCI_B_CCR3_BY_HL_DEN (1 << 5) /* 20: Driver control Enable */ + +/* Common Control Register 3 (8-bits) ***************************************/ + +#define R_SCI_B_CCR3_BY_HH_CKE_SHIFT (0) +#define R_SCI_B_CCR3_BY_HH_CKE_MASK (0x3) +# define R_SCI_B_CCR3_BY_HH_CKE_V00 (0 << R_SCI_B_CCR3_BY_HH_CKE_SHIFT) /* On-chip baud rate generator / On-chip baud rate generator The SCKn pin functions as I/O port. / Output disabled (The SCKn pin is available for use as an I/O port */ +# define R_SCI_B_CCR3_BY_HH_CKE_V01 (1 << R_SCI_B_CCR3_BY_HH_CKE_SHIFT) /* On-chip baud rate generator */ +# define R_SCI_B_CCR3_BY_HH_CKE_CLOCK_OUTPUT (1 << R_SCI_B_CCR3_BY_HH_CKE_SHIFT) /* Clock output */ +# define R_SCI_B_CCR3_BY_HH_CKE_OUTPUT_FIXED_LOW (0 << R_SCI_B_CCR3_BY_HH_CKE_SHIFT) /* Output fixed low */ +# define R_SCI_B_CCR3_BY_HH_CKE_OUTPUT_FIXED_HIGH (2 << R_SCI_B_CCR3_BY_HH_CKE_SHIFT) /* Output fixed high */ +#define R_SCI_B_CCR3_BY_HH_ACS0 (1 << 2) /* 04: Asynchronous Mode Clock Source Select */ +#define R_SCI_B_CCR3_BY_HH_GM (1 << 4) /* 10: GSM Mode */ +#define R_SCI_B_CCR3_BY_HH_BLK (1 << 5) /* 20: Block transfer mode */ + +/* Common Control Register 4 (32-bits) **************************************/ + +#define R_SCI_B_CCR4_CMPD_SHIFT (0) +#define R_SCI_B_CCR4_CMPD_MASK (0x1ff) +#define R_SCI_B_CCR4_ASEN (1 << 16) /* 10000: Adjustment enable bit for sampling timing */ +#define R_SCI_B_CCR4_ATEN (1 << 17) /* 20000: Adjustment enable bit for transmit waveform */ +#define R_SCI_B_CCR4_AST_SHIFT (24) +#define R_SCI_B_CCR4_AST_MASK (0x7) +# define R_SCI_B_CCR4_AST_V000 (0 << R_SCI_B_CCR4_AST_SHIFT) /* No adjustment (The sampling at default timing) */ +#define R_SCI_B_CCR4_AJD (1 << 27) /* 8000000: Adjustment Direction for sampling timing */ +#define R_SCI_B_CCR4_ATT_SHIFT (28) +#define R_SCI_B_CCR4_ATT_MASK (0x7) +# define R_SCI_B_CCR4_ATT_NO_ADJUSTMENT (0 << R_SCI_B_CCR4_ATT_SHIFT) /* No adjustment */ +#define R_SCI_B_CCR4_AET (1 << 31) /* 80000000: Adjustment Duty control level select */ + +/* Common Control Register 4 (16-bits) **************************************/ + +#define R_SCI_B_CCR4_HA_L_CMPD_SHIFT (0) +#define R_SCI_B_CCR4_HA_L_CMPD_MASK (0x1ff) + +/* Common Control Register 4 (8-bits) ***************************************/ + +#define R_SCI_B_CCR4_BY_LL_CMPD_SHIFT (0) +#define R_SCI_B_CCR4_BY_LL_CMPD_MASK (0xff) + +/* Common Control Register 4 (8-bits) ***************************************/ + +#define R_SCI_B_CCR4_BY_LH_CMPD (1 << 0) /* 01: Compare Match Data */ + +/* Common Control Register 4 (16-bits) **************************************/ + +#define R_SCI_B_CCR4_HA_H_ASEN (1 << 0) /* 01: Adjustment enable bit for sampling timing */ +#define R_SCI_B_CCR4_HA_H_ATEN (1 << 1) /* 02: Adjustment enable bit for transmit waveform */ +#define R_SCI_B_CCR4_HA_H_AST_SHIFT (8) +#define R_SCI_B_CCR4_HA_H_AST_MASK (0x7) +# define R_SCI_B_CCR4_HA_H_AST_V000 (0 << R_SCI_B_CCR4_HA_H_AST_SHIFT) /* No adjustment (The sampling at default timing) */ +#define R_SCI_B_CCR4_HA_H_AJD (1 << 11) /* 800: Adjustment Direction for sampling timing */ +#define R_SCI_B_CCR4_HA_H_ATT_SHIFT (12) +#define R_SCI_B_CCR4_HA_H_ATT_MASK (0x7) +# define R_SCI_B_CCR4_HA_H_ATT_NO_ADJUSTMENT (0 << R_SCI_B_CCR4_HA_H_ATT_SHIFT) /* No adjustment */ +#define R_SCI_B_CCR4_HA_H_AET (1 << 15) /* 8000: Adjustment Duty control level select */ + +/* Common Control Register 4 (8-bits) ***************************************/ + +#define R_SCI_B_CCR4_BY_HL_ASEN (1 << 0) /* 01: Adjustment enable bit for sampling timing */ +#define R_SCI_B_CCR4_BY_HL_ATEN (1 << 1) /* 02: Adjustment enable bit for transmit waveform */ + +/* Common Control Register 4 (8-bits) ***************************************/ + +#define R_SCI_B_CCR4_BY_HH_AST_SHIFT (0) +#define R_SCI_B_CCR4_BY_HH_AST_MASK (0x7) +# define R_SCI_B_CCR4_BY_HH_AST_V000 (0 << R_SCI_B_CCR4_BY_HH_AST_SHIFT) /* No adjustment (The sampling at default timing) */ +#define R_SCI_B_CCR4_BY_HH_AJD (1 << 3) /* 08: Adjustment Direction for sampling timing */ +#define R_SCI_B_CCR4_BY_HH_ATT_SHIFT (4) +#define R_SCI_B_CCR4_BY_HH_ATT_MASK (0x7) +# define R_SCI_B_CCR4_BY_HH_ATT_NO_ADJUSTMENT (0 << R_SCI_B_CCR4_BY_HH_ATT_SHIFT) /* No adjustment */ +#define R_SCI_B_CCR4_BY_HH_AET (1 << 7) /* 80: Adjustment Duty control level select */ + +/* Communication Enable Status Register (8-bits) ****************************/ + +#define R_SCI_B_CESR_RIST (1 << 0) /* 01: Internal status of RE signal */ +#define R_SCI_B_CESR_TIST (1 << 4) /* 10: Internal status of TE signal */ + +/* HBS valid mode Control Register (8-bits) *********************************/ + +#define R_SCI_B_HCR_HDEN (1 << 0) /* 01: HDC valid mode Enable */ +#define R_SCI_B_HCR_HDOC (1 << 2) /* 04: HDC valid mode Output Control */ +#define R_SCI_B_HCR_HDST (1 << 3) /* 08: HDC valid mode STart bit */ +#define R_SCI_B_HCR_HDIC (1 << 4) /* 10: HDC valid mode start bit Initialize Control */ + +/* Simple-I2C Control Register (32-bits) ************************************/ + +#define R_SCI_B_ICR_IICDL_SHIFT (0) +#define R_SCI_B_ICR_IICDL_MASK (0x1f) +# define R_SCI_B_ICR_IICDL_NO_OUTPUT_DELAY (0 << R_SCI_B_ICR_IICDL_SHIFT) /* No output delay */ +#define R_SCI_B_ICR_IICINTM (1 << 8) /* 100: I2C Interrupt Mode Select */ +#define R_SCI_B_ICR_IICCSC (1 << 9) /* 200: Clock Synchronization */ +#define R_SCI_B_ICR_IICACKT (1 << 13) /* 2000: ACK Transmission Data */ +#define R_SCI_B_ICR_IICSTAREQ (1 << 16) /* 10000: Start Condition Generation */ +#define R_SCI_B_ICR_IICRSTAREQ (1 << 17) /* 20000: Restart Condition Generation */ +#define R_SCI_B_ICR_IICSTPREQ (1 << 18) /* 40000: Stop Condition Generation */ +#define R_SCI_B_ICR_IICSDAS_SHIFT (20) +#define R_SCI_B_ICR_IICSDAS_MASK (0x3) +# define R_SCI_B_ICR_IICSDAS_SERIAL_DATA_OUTPUT (0 << R_SCI_B_ICR_IICSDAS_SHIFT) /* Serial data output */ +# define R_SCI_B_ICR_IICSDAS_V01 (1 << R_SCI_B_ICR_IICSDAS_SHIFT) /* Generate a start, restart, or stop condition. */ +# define R_SCI_B_ICR_IICSDAS_V10 (2 << R_SCI_B_ICR_IICSDAS_SHIFT) /* Output the low level on the SSDAn pin. */ +# define R_SCI_B_ICR_IICSDAS_V11 (3 << R_SCI_B_ICR_IICSDAS_SHIFT) /* Place the SSDAn pin in the high-impedance state. */ +#define R_SCI_B_ICR_IICSCLS_SHIFT (22) +#define R_SCI_B_ICR_IICSCLS_MASK (0x3) +# define R_SCI_B_ICR_IICSCLS_SERIAL_CLOCK_OUTPUT (0 << R_SCI_B_ICR_IICSCLS_SHIFT) /* Serial clock output */ +# define R_SCI_B_ICR_IICSCLS_V01 (1 << R_SCI_B_ICR_IICSCLS_SHIFT) /* Generate a start, restart, or stop condition. */ +# define R_SCI_B_ICR_IICSCLS_V10 (2 << R_SCI_B_ICR_IICSCLS_SHIFT) /* Output the low level on the SSCLn pin. */ +# define R_SCI_B_ICR_IICSCLS_V11 (3 << R_SCI_B_ICR_IICSCLS_SHIFT) /* Place the SSCLn pin in the high-impedance state. */ + +/* Simple-I2C Control Register (16-bits) ************************************/ + +#define R_SCI_B_ICR_HA_L_IICDL_SHIFT (0) +#define R_SCI_B_ICR_HA_L_IICDL_MASK (0x1f) +# define R_SCI_B_ICR_HA_L_IICDL_NO_OUTPUT_DELAY (0 << R_SCI_B_ICR_HA_L_IICDL_SHIFT) /* No output delay */ +#define R_SCI_B_ICR_HA_L_IICINTM (1 << 8) /* 100: I2C Interrupt Mode Select */ +#define R_SCI_B_ICR_HA_L_IICCSC (1 << 9) /* 200: Clock Synchronization */ +#define R_SCI_B_ICR_HA_L_IICACKT (1 << 13) /* 2000: ACK Transmission Data */ + +/* Simple-I2C Control Register (8-bits) *************************************/ + +#define R_SCI_B_ICR_BY_LL_IICDL_SHIFT (0) +#define R_SCI_B_ICR_BY_LL_IICDL_MASK (0x1f) +# define R_SCI_B_ICR_BY_LL_IICDL_NO_OUTPUT_DELAY (0 << R_SCI_B_ICR_BY_LL_IICDL_SHIFT) /* No output delay */ + +/* Simple-I2C Control Register (8-bits) *************************************/ + +#define R_SCI_B_ICR_BY_LH_IICINTM (1 << 0) /* 01: I2C Interrupt Mode Select */ +#define R_SCI_B_ICR_BY_LH_IICCSC (1 << 1) /* 02: Clock Synchronization */ +#define R_SCI_B_ICR_BY_LH_IICACKT (1 << 5) /* 20: ACK Transmission Data */ + +/* Simple-I2C Control Register (16-bits) ************************************/ + +#define R_SCI_B_ICR_HA_H_IICSTAREQ (1 << 0) /* 01: Start Condition Generation */ +#define R_SCI_B_ICR_HA_H_IICRSTAREQ (1 << 1) /* 02: Restart Condition Generation */ +#define R_SCI_B_ICR_HA_H_IICSTPREQ (1 << 2) /* 04: Stop Condition Generation */ +#define R_SCI_B_ICR_HA_H_IICSDAS_SHIFT (4) +#define R_SCI_B_ICR_HA_H_IICSDAS_MASK (0x3) +# define R_SCI_B_ICR_HA_H_IICSDAS_SERIAL_DATA_OUTPUT (0 << R_SCI_B_ICR_HA_H_IICSDAS_SHIFT) /* Serial data output */ +# define R_SCI_B_ICR_HA_H_IICSDAS_V01 (1 << R_SCI_B_ICR_HA_H_IICSDAS_SHIFT) /* Generate a start, restart, or stop condition. */ +# define R_SCI_B_ICR_HA_H_IICSDAS_V10 (2 << R_SCI_B_ICR_HA_H_IICSDAS_SHIFT) /* Output the low level on the SSDAn pin. */ +# define R_SCI_B_ICR_HA_H_IICSDAS_V11 (3 << R_SCI_B_ICR_HA_H_IICSDAS_SHIFT) /* Place the SSDAn pin in the high-impedance state. */ +#define R_SCI_B_ICR_HA_H_IICSCLS_SHIFT (6) +#define R_SCI_B_ICR_HA_H_IICSCLS_MASK (0x3) +# define R_SCI_B_ICR_HA_H_IICSCLS_SERIAL_CLOCK_OUTPUT (0 << R_SCI_B_ICR_HA_H_IICSCLS_SHIFT) /* Serial clock output */ +# define R_SCI_B_ICR_HA_H_IICSCLS_V01 (1 << R_SCI_B_ICR_HA_H_IICSCLS_SHIFT) /* Generate a start, restart, or stop condition. */ +# define R_SCI_B_ICR_HA_H_IICSCLS_V10 (2 << R_SCI_B_ICR_HA_H_IICSCLS_SHIFT) /* Output the low level on the SSCLn pin. */ +# define R_SCI_B_ICR_HA_H_IICSCLS_V11 (3 << R_SCI_B_ICR_HA_H_IICSCLS_SHIFT) /* Place the SSCLn pin in the high-impedance state. */ + +/* Simple-I2C Control Register (8-bits) *************************************/ + +#define R_SCI_B_ICR_BY_HL_IICSTAREQ (1 << 0) /* 01: Start Condition Generation */ +#define R_SCI_B_ICR_BY_HL_IICRSTAREQ (1 << 1) /* 02: Restart Condition Generation */ +#define R_SCI_B_ICR_BY_HL_IICSTPREQ (1 << 2) /* 04: Stop Condition Generation */ +#define R_SCI_B_ICR_BY_HL_IICSDAS_SHIFT (4) +#define R_SCI_B_ICR_BY_HL_IICSDAS_MASK (0x3) +# define R_SCI_B_ICR_BY_HL_IICSDAS_SERIAL_DATA_OUTPUT (0 << R_SCI_B_ICR_BY_HL_IICSDAS_SHIFT) /* Serial data output */ +# define R_SCI_B_ICR_BY_HL_IICSDAS_V01 (1 << R_SCI_B_ICR_BY_HL_IICSDAS_SHIFT) /* Generate a start, restart, or stop condition. */ +# define R_SCI_B_ICR_BY_HL_IICSDAS_V10 (2 << R_SCI_B_ICR_BY_HL_IICSDAS_SHIFT) /* Output the low level on the SSDAn pin. */ +# define R_SCI_B_ICR_BY_HL_IICSDAS_V11 (3 << R_SCI_B_ICR_BY_HL_IICSDAS_SHIFT) /* Place the SSDAn pin in the high-impedance state. */ +#define R_SCI_B_ICR_BY_HL_IICSCLS_SHIFT (6) +#define R_SCI_B_ICR_BY_HL_IICSCLS_MASK (0x3) +# define R_SCI_B_ICR_BY_HL_IICSCLS_SERIAL_CLOCK_OUTPUT (0 << R_SCI_B_ICR_BY_HL_IICSCLS_SHIFT) /* Serial clock output */ +# define R_SCI_B_ICR_BY_HL_IICSCLS_V01 (1 << R_SCI_B_ICR_BY_HL_IICSCLS_SHIFT) /* Generate a start, restart, or stop condition. */ +# define R_SCI_B_ICR_BY_HL_IICSCLS_V10 (2 << R_SCI_B_ICR_BY_HL_IICSCLS_SHIFT) /* Output the low level on the SSCLn pin. */ +# define R_SCI_B_ICR_BY_HL_IICSCLS_V11 (3 << R_SCI_B_ICR_BY_HL_IICSCLS_SHIFT) /* Place the SSCLn pin in the high-impedance state. */ + +/* FIFO Control Register (32-bits) ******************************************/ + +#define R_SCI_B_FCR_DRES (1 << 0) /* 01: Receive data ready error select bit */ +#define R_SCI_B_FCR_TTRG_SHIFT (8) +#define R_SCI_B_FCR_TTRG_MASK (0x1f) +#define R_SCI_B_FCR_TFRST (1 << 15) /* 8000: Transmit FIFO Data Register Reset */ +#define R_SCI_B_FCR_RTRG_SHIFT (16) +#define R_SCI_B_FCR_RTRG_MASK (0x1f) +#define R_SCI_B_FCR_RFRST (1 << 23) /* 800000: Receive FIFO Data Register Reset */ +#define R_SCI_B_FCR_RSTRG_SHIFT (24) +#define R_SCI_B_FCR_RSTRG_MASK (0x1f) + +/* FIFO Control Register (16-bits) ******************************************/ + +#define R_SCI_B_FCR_HA_L_DRES (1 << 0) /* 01: Receive data ready error select bit */ +#define R_SCI_B_FCR_HA_L_TTRG_SHIFT (8) +#define R_SCI_B_FCR_HA_L_TTRG_MASK (0x1f) +#define R_SCI_B_FCR_HA_L_TFRST (1 << 15) /* 8000: Transmit FIFO Data Register Reset */ + +/* FIFO Control Register (8-bits) *******************************************/ + +#define R_SCI_B_FCR_BY_LL_DRES (1 << 0) /* 01: Receive data ready error select bit */ + +/* FIFO Control Register (8-bits) *******************************************/ + +#define R_SCI_B_FCR_BY_LH_TTRG_SHIFT (0) +#define R_SCI_B_FCR_BY_LH_TTRG_MASK (0x1f) +#define R_SCI_B_FCR_BY_LH_TFRST (1 << 7) /* 80: Transmit FIFO Data Register Reset */ + +/* FIFO Control Register (16-bits) ******************************************/ + +#define R_SCI_B_FCR_HA_H_RTRG_SHIFT (0) +#define R_SCI_B_FCR_HA_H_RTRG_MASK (0x1f) +#define R_SCI_B_FCR_HA_H_RFRST (1 << 7) /* 80: Receive FIFO Data Register Reset */ +#define R_SCI_B_FCR_HA_H_RSTRG_SHIFT (8) +#define R_SCI_B_FCR_HA_H_RSTRG_MASK (0x1f) + +/* FIFO Control Register (8-bits) *******************************************/ + +#define R_SCI_B_FCR_BY_HL_RTRG_SHIFT (0) +#define R_SCI_B_FCR_BY_HL_RTRG_MASK (0x1f) +#define R_SCI_B_FCR_BY_HL_RFRST (1 << 7) /* 80: Receive FIFO Data Register Reset */ + +/* FIFO Control Register (8-bits) *******************************************/ + +#define R_SCI_B_FCR_BY_HH_RSTRG_SHIFT (0) +#define R_SCI_B_FCR_BY_HH_RSTRG_MASK (0x1f) + +/* Manchester Control Register (32-bits) ************************************/ + +#define R_SCI_B_MCR_RMPOL (1 << 0) /* 01: Receive Manchester polarity */ +#define R_SCI_B_MCR_TMPOL (1 << 1) /* 02: Transmission Manchester polarity */ +#define R_SCI_B_MCR_ERTEN (1 << 2) /* 04: Manchester edge retiming enable */ +#define R_SCI_B_MCR_SYNVAL (1 << 4) /* 10: Sync type of Manchester code start bit is set. */ +#define R_SCI_B_MCR_SYNSEL (1 << 5) /* 20: Sync select */ +#define R_SCI_B_MCR_SBSEL (1 << 6) /* 40: Start bit select */ +#define R_SCI_B_MCR_TPLEN_SHIFT (8) +#define R_SCI_B_MCR_TPLEN_MASK (0xf) +# define R_SCI_B_MCR_TPLEN_V0 (0 << R_SCI_B_MCR_TPLEN_SHIFT) /* Transmit preface generation disabled. */ +#define R_SCI_B_MCR_TPPAT_SHIFT (12) +#define R_SCI_B_MCR_TPPAT_MASK (0x3) +# define R_SCI_B_MCR_TPPAT_ALL_ZERO (0 << R_SCI_B_MCR_TPPAT_SHIFT) /* ALL ZERO */ +# define R_SCI_B_MCR_TPPAT_ZERO_ONE (1 << R_SCI_B_MCR_TPPAT_SHIFT) /* ZERO ONE */ +#define R_SCI_B_MCR_RPLEN_SHIFT (16) +#define R_SCI_B_MCR_RPLEN_MASK (0xf) +# define R_SCI_B_MCR_RPLEN_V0 (0 << R_SCI_B_MCR_RPLEN_SHIFT) /* Receive preface generation disabled. */ +#define R_SCI_B_MCR_RPPAT_SHIFT (20) +#define R_SCI_B_MCR_RPPAT_MASK (0x3) +# define R_SCI_B_MCR_RPPAT_ALL_ZERO (0 << R_SCI_B_MCR_RPPAT_SHIFT) /* ALL ZERO */ +# define R_SCI_B_MCR_RPPAT_ZERO_ONE (1 << R_SCI_B_MCR_RPPAT_SHIFT) /* ZERO ONE */ +# define R_SCI_B_MCR_RPPAT_ONE_ZERO (2 << R_SCI_B_MCR_RPPAT_SHIFT) /* ONE ZERO */ +# define R_SCI_B_MCR_RPPAT_ALL_ONE (3 << R_SCI_B_MCR_RPPAT_SHIFT) /* ALL ONE */ +#define R_SCI_B_MCR_PFEREN (1 << 24) /* 1000000: Preface Error enable */ +#define R_SCI_B_MCR_SYEREN (1 << 25) /* 2000000: Sync Error enable */ +#define R_SCI_B_MCR_SBEREN (1 << 26) /* 4000000: Start bit error enable */ + +/* Manchester Control Register (16-bits) ************************************/ + +#define R_SCI_B_MCR_HA_L_RMPOL (1 << 0) /* 01: Receive Manchester polarity */ +#define R_SCI_B_MCR_HA_L_TMPOL (1 << 1) /* 02: Transmission Manchester polarity */ +#define R_SCI_B_MCR_HA_L_ERTEN (1 << 2) /* 04: Manchester edge retiming enable */ +#define R_SCI_B_MCR_HA_L_SYNVAL (1 << 4) /* 10: Sync type of Manchester code start bit is set. */ +#define R_SCI_B_MCR_HA_L_SYNSEL (1 << 5) /* 20: Sync select */ +#define R_SCI_B_MCR_HA_L_SBSEL (1 << 6) /* 40: Start bit select */ +#define R_SCI_B_MCR_HA_L_TPLEN_SHIFT (8) +#define R_SCI_B_MCR_HA_L_TPLEN_MASK (0xf) +# define R_SCI_B_MCR_HA_L_TPLEN_V0 (0 << R_SCI_B_MCR_HA_L_TPLEN_SHIFT) /* Transmit preface generation disabled. */ +#define R_SCI_B_MCR_HA_L_TPPAT_SHIFT (12) +#define R_SCI_B_MCR_HA_L_TPPAT_MASK (0x3) +# define R_SCI_B_MCR_HA_L_TPPAT_ALL_ZERO (0 << R_SCI_B_MCR_HA_L_TPPAT_SHIFT) /* ALL ZERO */ +# define R_SCI_B_MCR_HA_L_TPPAT_ZERO_ONE (1 << R_SCI_B_MCR_HA_L_TPPAT_SHIFT) /* ZERO ONE */ + +/* Manchester Control Register (8-bits) *************************************/ + +#define R_SCI_B_MCR_BY_LL_RMPOL (1 << 0) /* 01: Receive Manchester polarity */ +#define R_SCI_B_MCR_BY_LL_TMPOL (1 << 1) /* 02: Transmission Manchester polarity */ +#define R_SCI_B_MCR_BY_LL_ERTEN (1 << 2) /* 04: Manchester edge retiming enable */ +#define R_SCI_B_MCR_BY_LL_SYNVAL (1 << 4) /* 10: Sync type of Manchester code start bit is set. */ +#define R_SCI_B_MCR_BY_LL_SYNSEL (1 << 5) /* 20: Sync select */ +#define R_SCI_B_MCR_BY_LL_SBSEL (1 << 6) /* 40: Start bit select */ + +/* Manchester Control Register (8-bits) *************************************/ + +#define R_SCI_B_MCR_BY_LH_TPLEN_SHIFT (0) +#define R_SCI_B_MCR_BY_LH_TPLEN_MASK (0xf) +# define R_SCI_B_MCR_BY_LH_TPLEN_V0 (0 << R_SCI_B_MCR_BY_LH_TPLEN_SHIFT) /* Transmit preface generation disabled. */ +#define R_SCI_B_MCR_BY_LH_TPPAT_SHIFT (4) +#define R_SCI_B_MCR_BY_LH_TPPAT_MASK (0x3) +# define R_SCI_B_MCR_BY_LH_TPPAT_ALL_ZERO (0 << R_SCI_B_MCR_BY_LH_TPPAT_SHIFT) /* ALL ZERO */ +# define R_SCI_B_MCR_BY_LH_TPPAT_ZERO_ONE (1 << R_SCI_B_MCR_BY_LH_TPPAT_SHIFT) /* ZERO ONE */ + +/* Manchester Control Register (16-bits) ************************************/ + +#define R_SCI_B_MCR_HA_H_RPLEN_SHIFT (0) +#define R_SCI_B_MCR_HA_H_RPLEN_MASK (0xf) +# define R_SCI_B_MCR_HA_H_RPLEN_V0 (0 << R_SCI_B_MCR_HA_H_RPLEN_SHIFT) /* Receive preface generation disabled. */ +#define R_SCI_B_MCR_HA_H_RPPAT_SHIFT (4) +#define R_SCI_B_MCR_HA_H_RPPAT_MASK (0x3) +# define R_SCI_B_MCR_HA_H_RPPAT_ALL_ZERO (0 << R_SCI_B_MCR_HA_H_RPPAT_SHIFT) /* ALL ZERO */ +# define R_SCI_B_MCR_HA_H_RPPAT_ZERO_ONE (1 << R_SCI_B_MCR_HA_H_RPPAT_SHIFT) /* ZERO ONE */ +# define R_SCI_B_MCR_HA_H_RPPAT_ONE_ZERO (2 << R_SCI_B_MCR_HA_H_RPPAT_SHIFT) /* ONE ZERO */ +# define R_SCI_B_MCR_HA_H_RPPAT_ALL_ONE (3 << R_SCI_B_MCR_HA_H_RPPAT_SHIFT) /* ALL ONE */ +#define R_SCI_B_MCR_HA_H_PFEREN (1 << 8) /* 100: Preface Error enable */ +#define R_SCI_B_MCR_HA_H_SYEREN (1 << 9) /* 200: Sync Error enable */ +#define R_SCI_B_MCR_HA_H_SBEREN (1 << 10) /* 400: Start bit error enable */ + +/* Manchester Control Register (8-bits) *************************************/ + +#define R_SCI_B_MCR_BY_HL_RPLEN_SHIFT (0) +#define R_SCI_B_MCR_BY_HL_RPLEN_MASK (0xf) +# define R_SCI_B_MCR_BY_HL_RPLEN_V0 (0 << R_SCI_B_MCR_BY_HL_RPLEN_SHIFT) /* Receive preface generation disabled. */ +#define R_SCI_B_MCR_BY_HL_RPPAT_SHIFT (4) +#define R_SCI_B_MCR_BY_HL_RPPAT_MASK (0x3) +# define R_SCI_B_MCR_BY_HL_RPPAT_ALL_ZERO (0 << R_SCI_B_MCR_BY_HL_RPPAT_SHIFT) /* ALL ZERO */ +# define R_SCI_B_MCR_BY_HL_RPPAT_ZERO_ONE (1 << R_SCI_B_MCR_BY_HL_RPPAT_SHIFT) /* ZERO ONE */ +# define R_SCI_B_MCR_BY_HL_RPPAT_ONE_ZERO (2 << R_SCI_B_MCR_BY_HL_RPPAT_SHIFT) /* ONE ZERO */ +# define R_SCI_B_MCR_BY_HL_RPPAT_ALL_ONE (3 << R_SCI_B_MCR_BY_HL_RPPAT_SHIFT) /* ALL ONE */ + +/* Manchester Control Register (8-bits) *************************************/ + +#define R_SCI_B_MCR_BY_HH_PFEREN (1 << 0) /* 01: Preface Error enable */ +#define R_SCI_B_MCR_BY_HH_SYEREN (1 << 1) /* 02: Sync Error enable */ +#define R_SCI_B_MCR_BY_HH_SBEREN (1 << 2) /* 04: Start bit error enable */ + +/* Driver Control Register (32-bits) ****************************************/ + +#define R_SCI_B_DCR_DEPOL (1 << 0) /* 01: Driver Enable POLarity select */ +#define R_SCI_B_DCR_DEAST_SHIFT (8) +#define R_SCI_B_DCR_DEAST_MASK (0x1f) +#define R_SCI_B_DCR_DENGT_SHIFT (16) +#define R_SCI_B_DCR_DENGT_MASK (0x1f) + +/* Driver Control Register (16-bits) ****************************************/ + +#define R_SCI_B_DCR_HA_L_DEPOL (1 << 0) /* 01: Driver Enable POLarity select */ +#define R_SCI_B_DCR_HA_L_DEAST_SHIFT (8) +#define R_SCI_B_DCR_HA_L_DEAST_MASK (0x1f) + +/* Driver Control Register (8-bits) *****************************************/ + +#define R_SCI_B_DCR_BY_LL_DEPOL (1 << 0) /* 01: Driver Enable POLarity select */ + +/* Driver Control Register (8-bits) *****************************************/ + +#define R_SCI_B_DCR_BY_LH_DEAST_SHIFT (0) +#define R_SCI_B_DCR_BY_LH_DEAST_MASK (0x1f) + +/* Driver Control Register (16-bits) ****************************************/ + +#define R_SCI_B_DCR_HA_H_DENGT_SHIFT (0) +#define R_SCI_B_DCR_HA_H_DENGT_MASK (0x1f) + +/* Driver Control Register (8-bits) *****************************************/ + +#define R_SCI_B_DCR_BY_HL_DENGT_SHIFT (0) +#define R_SCI_B_DCR_BY_HL_DENGT_MASK (0x1f) + +/* Simple-LIN(SCIX) Control Register 0 (32-bits) ****************************/ + +#define R_SCI_B_XCR0_TCSS_SHIFT (0) +#define R_SCI_B_XCR0_TCSS_MASK (0x3) +# define R_SCI_B_XCR0_TCSS_TCLK (0 << R_SCI_B_XCR0_TCSS_SHIFT) /* TCLK */ +# define R_SCI_B_XCR0_TCSS_TCLK_4 (1 << R_SCI_B_XCR0_TCSS_SHIFT) /* TCLK/4 */ +# define R_SCI_B_XCR0_TCSS_TCLK_16 (2 << R_SCI_B_XCR0_TCSS_SHIFT) /* TCLK/16 */ +# define R_SCI_B_XCR0_TCSS_TCLK_64 (3 << R_SCI_B_XCR0_TCSS_SHIFT) /* TCLK/64 */ +#define R_SCI_B_XCR0_BFE (1 << 8) /* 100: Break field presence/absence select */ +#define R_SCI_B_XCR0_CF0RE (1 << 9) /* 200: Control field 0 presence/absence select */ +#define R_SCI_B_XCR0_CF1DS_SHIFT (10) +#define R_SCI_B_XCR0_CF1DS_MASK (0x3) +# define R_SCI_B_XCR0_CF1DS_V00 (0 << R_SCI_B_XCR0_CF1DS_SHIFT) /* XCR1.PCF1D[7:0] is compare data */ +# define R_SCI_B_XCR0_CF1DS_V01 (1 << R_SCI_B_XCR0_CF1DS_SHIFT) /* XCR1.SCF1D[7:0] is compare data */ +# define R_SCI_B_XCR0_CF1DS_V10 (2 << R_SCI_B_XCR0_CF1DS_SHIFT) /* XCR1.PCF1D[7:0] and XCR1.SCF1D[7:0] are compare data */ +# define R_SCI_B_XCR0_CF1DS_PROHIBIT (3 << R_SCI_B_XCR0_CF1DS_SHIFT) /* Prohibit */ +#define R_SCI_B_XCR0_PIBE (1 << 12) /* 1000: Priority Interrupt Bit Enable */ +#define R_SCI_B_XCR0_PIBS_SHIFT (13) +#define R_SCI_B_XCR0_PIBS_MASK (0x7) +# define R_SCI_B_XCR0_PIBS_CONTROL_FIELD_1_BIT_0 (0 << R_SCI_B_XCR0_PIBS_SHIFT) /* Control Field 1, bit 0. */ +# define R_SCI_B_XCR0_PIBS_CONTROL_FIELD_1_BIT_1 (1 << R_SCI_B_XCR0_PIBS_SHIFT) /* Control Field 1, bit 1. */ +# define R_SCI_B_XCR0_PIBS_CONTROL_FIELD_1_BIT_2 (2 << R_SCI_B_XCR0_PIBS_SHIFT) /* Control Field 1, bit 2. */ +# define R_SCI_B_XCR0_PIBS_CONTROL_FIELD_1_BIT_3 (3 << R_SCI_B_XCR0_PIBS_SHIFT) /* Control Field 1, bit 3. */ +# define R_SCI_B_XCR0_PIBS_CONTROL_FIELD_1_BIT_4 (4 << R_SCI_B_XCR0_PIBS_SHIFT) /* Control Field 1, bit 4. */ +# define R_SCI_B_XCR0_PIBS_CONTROL_FIELD_1_BIT_5 (5 << R_SCI_B_XCR0_PIBS_SHIFT) /* Control Field 1, bit 5. */ +# define R_SCI_B_XCR0_PIBS_CONTROL_FIELD_1_BIT_6 (6 << R_SCI_B_XCR0_PIBS_SHIFT) /* Control Field 1, bit 6. */ +# define R_SCI_B_XCR0_PIBS_CONTROL_FIELD_1_BIT_7 (7 << R_SCI_B_XCR0_PIBS_SHIFT) /* Control Field 1, bit 7. */ +#define R_SCI_B_XCR0_BFOIE (1 << 16) /* 10000: Break Filed Output end Interrupt Enable */ +#define R_SCI_B_XCR0_BCDIE (1 << 17) /* 20000: Bus Collision Detect Interrupt Enable */ +#define R_SCI_B_XCR0_BFDIE (1 << 20) /* 100000: Break Filed Detection Interrupt Enable */ +#define R_SCI_B_XCR0_COFIE (1 << 21) /* 200000: Counter Over Flow Interrupt Enable */ +#define R_SCI_B_XCR0_AEDIE (1 << 22) /* 400000: Active Edge Detection Interrupt Enable */ +#define R_SCI_B_XCR0_BCCS_SHIFT (24) +#define R_SCI_B_XCR0_BCCS_MASK (0x3) +# define R_SCI_B_XCR0_BCCS_RSCI_BASE_CLOCK (0 << R_SCI_B_XCR0_BCCS_SHIFT) /* RSCI base clock */ +# define R_SCI_B_XCR0_BCCS_RSCI_BASE_CLOCK_2 (1 << R_SCI_B_XCR0_BCCS_SHIFT) /* RSCI base clock/2 */ +# define R_SCI_B_XCR0_BCCS_RSCI_BASE_CLOCK_4 (2 << R_SCI_B_XCR0_BCCS_SHIFT) /* RSCI base clock/4 */ +# define R_SCI_B_XCR0_BCCS_PROHIBIT (3 << R_SCI_B_XCR0_BCCS_SHIFT) /* Prohibit */ + +/* Simple-LIN(SCIX) Control Register 0 (16-bits) ****************************/ + +#define R_SCI_B_XCR0_HA_L_TCSS_SHIFT (0) +#define R_SCI_B_XCR0_HA_L_TCSS_MASK (0x3) +# define R_SCI_B_XCR0_HA_L_TCSS_TCLK (0 << R_SCI_B_XCR0_HA_L_TCSS_SHIFT) /* TCLK */ +# define R_SCI_B_XCR0_HA_L_TCSS_TCLK_4 (1 << R_SCI_B_XCR0_HA_L_TCSS_SHIFT) /* TCLK/4 */ +# define R_SCI_B_XCR0_HA_L_TCSS_TCLK_16 (2 << R_SCI_B_XCR0_HA_L_TCSS_SHIFT) /* TCLK/16 */ +# define R_SCI_B_XCR0_HA_L_TCSS_TCLK_64 (3 << R_SCI_B_XCR0_HA_L_TCSS_SHIFT) /* TCLK/64 */ +#define R_SCI_B_XCR0_HA_L_BFE (1 << 8) /* 100: Break field presence/absence select */ +#define R_SCI_B_XCR0_HA_L_CF0RE (1 << 9) /* 200: Control field 0 presence/absence select */ +#define R_SCI_B_XCR0_HA_L_CF1DS_SHIFT (10) +#define R_SCI_B_XCR0_HA_L_CF1DS_MASK (0x3) +# define R_SCI_B_XCR0_HA_L_CF1DS_V00 (0 << R_SCI_B_XCR0_HA_L_CF1DS_SHIFT) /* XCR1.PCF1D[7:0] is compare data */ +# define R_SCI_B_XCR0_HA_L_CF1DS_V01 (1 << R_SCI_B_XCR0_HA_L_CF1DS_SHIFT) /* XCR1.SCF1D[7:0] is compare data */ +# define R_SCI_B_XCR0_HA_L_CF1DS_V10 (2 << R_SCI_B_XCR0_HA_L_CF1DS_SHIFT) /* XCR1.PCF1D[7:0] and XCR1.SCF1D[7:0] are compare data */ +# define R_SCI_B_XCR0_HA_L_CF1DS_PROHIBIT (3 << R_SCI_B_XCR0_HA_L_CF1DS_SHIFT) /* Prohibit */ +#define R_SCI_B_XCR0_HA_L_PIBE (1 << 12) /* 1000: Priority Interrupt Bit Enable */ +#define R_SCI_B_XCR0_HA_L_PIBS_SHIFT (13) +#define R_SCI_B_XCR0_HA_L_PIBS_MASK (0x7) +# define R_SCI_B_XCR0_HA_L_PIBS_CONTROL_FIELD_1_BIT_0 (0 << R_SCI_B_XCR0_HA_L_PIBS_SHIFT) /* Control Field 1, bit 0. */ +# define R_SCI_B_XCR0_HA_L_PIBS_CONTROL_FIELD_1_BIT_1 (1 << R_SCI_B_XCR0_HA_L_PIBS_SHIFT) /* Control Field 1, bit 1. */ +# define R_SCI_B_XCR0_HA_L_PIBS_CONTROL_FIELD_1_BIT_2 (2 << R_SCI_B_XCR0_HA_L_PIBS_SHIFT) /* Control Field 1, bit 2. */ +# define R_SCI_B_XCR0_HA_L_PIBS_CONTROL_FIELD_1_BIT_3 (3 << R_SCI_B_XCR0_HA_L_PIBS_SHIFT) /* Control Field 1, bit 3. */ +# define R_SCI_B_XCR0_HA_L_PIBS_CONTROL_FIELD_1_BIT_4 (4 << R_SCI_B_XCR0_HA_L_PIBS_SHIFT) /* Control Field 1, bit 4. */ +# define R_SCI_B_XCR0_HA_L_PIBS_CONTROL_FIELD_1_BIT_5 (5 << R_SCI_B_XCR0_HA_L_PIBS_SHIFT) /* Control Field 1, bit 5. */ +# define R_SCI_B_XCR0_HA_L_PIBS_CONTROL_FIELD_1_BIT_6 (6 << R_SCI_B_XCR0_HA_L_PIBS_SHIFT) /* Control Field 1, bit 6. */ +# define R_SCI_B_XCR0_HA_L_PIBS_CONTROL_FIELD_1_BIT_7 (7 << R_SCI_B_XCR0_HA_L_PIBS_SHIFT) /* Control Field 1, bit 7. */ + +/* Simple-LIN(SCIX) Control Register 0 (8-bits) *****************************/ + +#define R_SCI_B_XCR0_BY_LL_TCSS_SHIFT (0) +#define R_SCI_B_XCR0_BY_LL_TCSS_MASK (0x3) +# define R_SCI_B_XCR0_BY_LL_TCSS_TCLK (0 << R_SCI_B_XCR0_BY_LL_TCSS_SHIFT) /* TCLK */ +# define R_SCI_B_XCR0_BY_LL_TCSS_TCLK_4 (1 << R_SCI_B_XCR0_BY_LL_TCSS_SHIFT) /* TCLK/4 */ +# define R_SCI_B_XCR0_BY_LL_TCSS_TCLK_16 (2 << R_SCI_B_XCR0_BY_LL_TCSS_SHIFT) /* TCLK/16 */ +# define R_SCI_B_XCR0_BY_LL_TCSS_TCLK_64 (3 << R_SCI_B_XCR0_BY_LL_TCSS_SHIFT) /* TCLK/64 */ + +/* Simple-LIN(SCIX) Control Register 0 (8-bits) *****************************/ + +#define R_SCI_B_XCR0_BY_LH_BFE (1 << 0) /* 01: Break field presence/absence select */ +#define R_SCI_B_XCR0_BY_LH_CF0RE (1 << 1) /* 02: Control field 0 presence/absence select */ +#define R_SCI_B_XCR0_BY_LH_CF1DS_SHIFT (2) +#define R_SCI_B_XCR0_BY_LH_CF1DS_MASK (0x3) +# define R_SCI_B_XCR0_BY_LH_CF1DS_V00 (0 << R_SCI_B_XCR0_BY_LH_CF1DS_SHIFT) /* XCR1.PCF1D[7:0] is compare data */ +# define R_SCI_B_XCR0_BY_LH_CF1DS_V01 (1 << R_SCI_B_XCR0_BY_LH_CF1DS_SHIFT) /* XCR1.SCF1D[7:0] is compare data */ +# define R_SCI_B_XCR0_BY_LH_CF1DS_V10 (2 << R_SCI_B_XCR0_BY_LH_CF1DS_SHIFT) /* XCR1.PCF1D[7:0] and XCR1.SCF1D[7:0] are compare data */ +# define R_SCI_B_XCR0_BY_LH_CF1DS_PROHIBIT (3 << R_SCI_B_XCR0_BY_LH_CF1DS_SHIFT) /* Prohibit */ +#define R_SCI_B_XCR0_BY_LH_PIBE (1 << 4) /* 10: Priority Interrupt Bit Enable */ +#define R_SCI_B_XCR0_BY_LH_PIBS_SHIFT (5) +#define R_SCI_B_XCR0_BY_LH_PIBS_MASK (0x7) +# define R_SCI_B_XCR0_BY_LH_PIBS_CONTROL_FIELD_1_BIT_0 (0 << R_SCI_B_XCR0_BY_LH_PIBS_SHIFT) /* Control Field 1, bit 0. */ +# define R_SCI_B_XCR0_BY_LH_PIBS_CONTROL_FIELD_1_BIT_1 (1 << R_SCI_B_XCR0_BY_LH_PIBS_SHIFT) /* Control Field 1, bit 1. */ +# define R_SCI_B_XCR0_BY_LH_PIBS_CONTROL_FIELD_1_BIT_2 (2 << R_SCI_B_XCR0_BY_LH_PIBS_SHIFT) /* Control Field 1, bit 2. */ +# define R_SCI_B_XCR0_BY_LH_PIBS_CONTROL_FIELD_1_BIT_3 (3 << R_SCI_B_XCR0_BY_LH_PIBS_SHIFT) /* Control Field 1, bit 3. */ +# define R_SCI_B_XCR0_BY_LH_PIBS_CONTROL_FIELD_1_BIT_4 (4 << R_SCI_B_XCR0_BY_LH_PIBS_SHIFT) /* Control Field 1, bit 4. */ +# define R_SCI_B_XCR0_BY_LH_PIBS_CONTROL_FIELD_1_BIT_5 (5 << R_SCI_B_XCR0_BY_LH_PIBS_SHIFT) /* Control Field 1, bit 5. */ +# define R_SCI_B_XCR0_BY_LH_PIBS_CONTROL_FIELD_1_BIT_6 (6 << R_SCI_B_XCR0_BY_LH_PIBS_SHIFT) /* Control Field 1, bit 6. */ +# define R_SCI_B_XCR0_BY_LH_PIBS_CONTROL_FIELD_1_BIT_7 (7 << R_SCI_B_XCR0_BY_LH_PIBS_SHIFT) /* Control Field 1, bit 7. */ + +/* Simple-LIN(SCIX) Control Register 0 (16-bits) ****************************/ + +#define R_SCI_B_XCR0_HA_H_BFOIE (1 << 0) /* 01: Break Filed Output end Interrupt Enable */ +#define R_SCI_B_XCR0_HA_H_BCDIE (1 << 1) /* 02: Bus Collision Detect Interrupt Enable */ +#define R_SCI_B_XCR0_HA_H_BFDIE (1 << 4) /* 10: Break Filed Detection Interrupt Enable */ +#define R_SCI_B_XCR0_HA_H_COFIE (1 << 5) /* 20: Counter Over Flow Interrupt Enable */ +#define R_SCI_B_XCR0_HA_H_AEDIE (1 << 6) /* 40: Active Edge Detection Interrupt Enable */ +#define R_SCI_B_XCR0_HA_H_BCCS_SHIFT (8) +#define R_SCI_B_XCR0_HA_H_BCCS_MASK (0x3) +# define R_SCI_B_XCR0_HA_H_BCCS_RSCI_BASE_CLOCK (0 << R_SCI_B_XCR0_HA_H_BCCS_SHIFT) /* RSCI base clock */ +# define R_SCI_B_XCR0_HA_H_BCCS_RSCI_BASE_CLOCK_2 (1 << R_SCI_B_XCR0_HA_H_BCCS_SHIFT) /* RSCI base clock/2 */ +# define R_SCI_B_XCR0_HA_H_BCCS_RSCI_BASE_CLOCK_4 (2 << R_SCI_B_XCR0_HA_H_BCCS_SHIFT) /* RSCI base clock/4 */ +# define R_SCI_B_XCR0_HA_H_BCCS_PROHIBIT (3 << R_SCI_B_XCR0_HA_H_BCCS_SHIFT) /* Prohibit */ + +/* Simple-LIN(SCIX) Control Register 0 (8-bits) *****************************/ + +#define R_SCI_B_XCR0_BY_HL_BFOIE (1 << 0) /* 01: Break Filed Output end Interrupt Enable */ +#define R_SCI_B_XCR0_BY_HL_BCDIE (1 << 1) /* 02: Bus Collision Detect Interrupt Enable */ +#define R_SCI_B_XCR0_BY_HL_BFDIE (1 << 4) /* 10: Break Filed Detection Interrupt Enable */ +#define R_SCI_B_XCR0_BY_HL_COFIE (1 << 5) /* 20: Counter Over Flow Interrupt Enable */ +#define R_SCI_B_XCR0_BY_HL_AEDIE (1 << 6) /* 40: Active Edge Detection Interrupt Enable */ + +/* Simple-LIN(SCIX) Control Register 0 (8-bits) *****************************/ + +#define R_SCI_B_XCR0_BY_HH_BCCS_SHIFT (0) +#define R_SCI_B_XCR0_BY_HH_BCCS_MASK (0x3) +# define R_SCI_B_XCR0_BY_HH_BCCS_RSCI_BASE_CLOCK (0 << R_SCI_B_XCR0_BY_HH_BCCS_SHIFT) /* RSCI base clock */ +# define R_SCI_B_XCR0_BY_HH_BCCS_RSCI_BASE_CLOCK_2 (1 << R_SCI_B_XCR0_BY_HH_BCCS_SHIFT) /* RSCI base clock/2 */ +# define R_SCI_B_XCR0_BY_HH_BCCS_RSCI_BASE_CLOCK_4 (2 << R_SCI_B_XCR0_BY_HH_BCCS_SHIFT) /* RSCI base clock/4 */ +# define R_SCI_B_XCR0_BY_HH_BCCS_PROHIBIT (3 << R_SCI_B_XCR0_BY_HH_BCCS_SHIFT) /* Prohibit */ + +/* Simple-LIN(SCIX) Control Register 1 (32-bits) ****************************/ + +#define R_SCI_B_XCR1_TCST (1 << 0) /* 01: break field Timer Count Start trigger */ +#define R_SCI_B_XCR1_SDST (1 << 4) /* 10: Start frame Detection Start trigger */ +#define R_SCI_B_XCR1_BMEN (1 << 5) /* 20: Bit rate Measurement function Enable */ +#define R_SCI_B_XCR1_PCF1D_SHIFT (8) +#define R_SCI_B_XCR1_PCF1D_MASK (0xff) +#define R_SCI_B_XCR1_SCF1D_SHIFT (16) +#define R_SCI_B_XCR1_SCF1D_MASK (0xff) +#define R_SCI_B_XCR1_CF1CE_SHIFT (24) +#define R_SCI_B_XCR1_CF1CE_MASK (0xff) +# define R_SCI_B_XCR1_CF1CE_V0 (0 << R_SCI_B_XCR1_CF1CE_SHIFT) /* Bit N of control Field 1 is not for comparison */ +# define R_SCI_B_XCR1_CF1CE_V1 (1 << R_SCI_B_XCR1_CF1CE_SHIFT) /* Bit N of control Field 1 is for comparison */ + +/* Simple-LIN(SCIX) Control Register 1 (16-bits) ****************************/ + +#define R_SCI_B_XCR1_HA_L_TCST (1 << 0) /* 01: break field Timer Count Start trigger */ +#define R_SCI_B_XCR1_HA_L_SDST (1 << 4) /* 10: Start frame Detection Start trigger */ +#define R_SCI_B_XCR1_HA_L_BMEN (1 << 5) /* 20: Bit rate Measurement function Enable */ +#define R_SCI_B_XCR1_HA_L_PCF1D_SHIFT (8) +#define R_SCI_B_XCR1_HA_L_PCF1D_MASK (0xff) + +/* Simple-LIN(SCIX) Control Register 1 (8-bits) *****************************/ + +#define R_SCI_B_XCR1_BY_LL_TCST (1 << 0) /* 01: break field Timer Count Start trigger */ +#define R_SCI_B_XCR1_BY_LL_SDST (1 << 4) /* 10: Start frame Detection Start trigger */ +#define R_SCI_B_XCR1_BY_LL_BMEN (1 << 5) /* 20: Bit rate Measurement function Enable */ + +/* Simple-LIN(SCIX) Control Register 1 (8-bits) *****************************/ + +#define R_SCI_B_XCR1_BY_LH_PCF1D_SHIFT (0) +#define R_SCI_B_XCR1_BY_LH_PCF1D_MASK (0xff) + +/* Simple-LIN(SCIX) Control Register 1 (16-bits) ****************************/ + +#define R_SCI_B_XCR1_HA_H_SCF1D_SHIFT (0) +#define R_SCI_B_XCR1_HA_H_SCF1D_MASK (0xff) +#define R_SCI_B_XCR1_HA_H_CF1CE_SHIFT (8) +#define R_SCI_B_XCR1_HA_H_CF1CE_MASK (0xff) +# define R_SCI_B_XCR1_HA_H_CF1CE_V0 (0 << R_SCI_B_XCR1_HA_H_CF1CE_SHIFT) /* Bit N of control Field 1 is not for comparison */ +# define R_SCI_B_XCR1_HA_H_CF1CE_V1 (1 << R_SCI_B_XCR1_HA_H_CF1CE_SHIFT) /* Bit N of control Field 1 is for comparison */ + +/* Simple-LIN(SCIX) Control Register 1 (8-bits) *****************************/ + +#define R_SCI_B_XCR1_BY_HL_SCF1D_SHIFT (0) +#define R_SCI_B_XCR1_BY_HL_SCF1D_MASK (0xff) + +/* Simple-LIN(SCIX) Control Register 1 (8-bits) *****************************/ + +#define R_SCI_B_XCR1_BY_HH_CF1CE_SHIFT (0) +#define R_SCI_B_XCR1_BY_HH_CF1CE_MASK (0xff) +# define R_SCI_B_XCR1_BY_HH_CF1CE_V0 (0 << R_SCI_B_XCR1_BY_HH_CF1CE_SHIFT) /* Bit N of control Field 1 is not for comparison */ +# define R_SCI_B_XCR1_BY_HH_CF1CE_V1 (1 << R_SCI_B_XCR1_BY_HH_CF1CE_SHIFT) /* Bit N of control Field 1 is for comparison */ + +/* Simple-LIN(SCIX) Control Register 2 (32-bits) ****************************/ + +#define R_SCI_B_XCR2_CF0D_SHIFT (0) +#define R_SCI_B_XCR2_CF0D_MASK (0xff) +#define R_SCI_B_XCR2_CF0CE_SHIFT (8) +#define R_SCI_B_XCR2_CF0CE_MASK (0xff) +# define R_SCI_B_XCR2_CF0CE_V0 (0 << R_SCI_B_XCR2_CF0CE_SHIFT) /* Bit N of control Field 0 is not for comparison */ +# define R_SCI_B_XCR2_CF0CE_V1 (1 << R_SCI_B_XCR2_CF0CE_SHIFT) /* Bit N of control Field 0 is for comparison */ +#define R_SCI_B_XCR2_BFLW_SHIFT (16) +#define R_SCI_B_XCR2_BFLW_MASK (0xffff) + +/* Simple-LIN(SCIX) Control Register 2 (16-bits) ****************************/ + +#define R_SCI_B_XCR2_HA_L_CF0D_SHIFT (0) +#define R_SCI_B_XCR2_HA_L_CF0D_MASK (0xff) +#define R_SCI_B_XCR2_HA_L_CF0CE_SHIFT (8) +#define R_SCI_B_XCR2_HA_L_CF0CE_MASK (0xff) +# define R_SCI_B_XCR2_HA_L_CF0CE_V0 (0 << R_SCI_B_XCR2_HA_L_CF0CE_SHIFT) /* Bit N of control Field 0 is not for comparison */ +# define R_SCI_B_XCR2_HA_L_CF0CE_V1 (1 << R_SCI_B_XCR2_HA_L_CF0CE_SHIFT) /* Bit N of control Field 0 is for comparison */ + +/* Simple-LIN(SCIX) Control Register 2 (8-bits) *****************************/ + +#define R_SCI_B_XCR2_BY_LL_CF0D_SHIFT (0) +#define R_SCI_B_XCR2_BY_LL_CF0D_MASK (0xff) + +/* Simple-LIN(SCIX) Control Register 2 (8-bits) *****************************/ + +#define R_SCI_B_XCR2_BY_LH_CF0CE_SHIFT (0) +#define R_SCI_B_XCR2_BY_LH_CF0CE_MASK (0xff) +# define R_SCI_B_XCR2_BY_LH_CF0CE_V0 (0 << R_SCI_B_XCR2_BY_LH_CF0CE_SHIFT) /* Bit N of control Field 0 is not for comparison */ +# define R_SCI_B_XCR2_BY_LH_CF0CE_V1 (1 << R_SCI_B_XCR2_BY_LH_CF0CE_SHIFT) /* Bit N of control Field 0 is for comparison */ + +/* Simple-LIN(SCIX) Control Register 2 (16-bits) ****************************/ + +#define R_SCI_B_XCR2_HA_H_BFLW_SHIFT (0) +#define R_SCI_B_XCR2_HA_H_BFLW_MASK (0xffff) + +/* Simple-LIN(SCIX) Control Register 2 (8-bits) *****************************/ + +#define R_SCI_B_XCR2_BY_HL_BFLW_SHIFT (0) +#define R_SCI_B_XCR2_BY_HL_BFLW_MASK (0xff) + +/* Simple-LIN(SCIX) Control Register 2 (8-bits) *****************************/ + +#define R_SCI_B_XCR2_BY_HH_BFLW_SHIFT (0) +#define R_SCI_B_XCR2_BY_HH_BFLW_MASK (0xff) + +/* Common Status Register (32-bits) *****************************************/ + +#define R_SCI_B_CSR_ERS (1 << 4) /* 10: Error Signal Status Flag */ +#define R_SCI_B_CSR_RxDMON (1 << 15) /* 8000: Serial input data monitor bit */ +#define R_SCI_B_CSR_DCMF (1 << 16) /* 10000: Data Compare Match Flag */ +#define R_SCI_B_CSR_DPER (1 << 17) /* 20000: Data Compare Match Parity Error Flag */ +#define R_SCI_B_CSR_DFER (1 << 18) /* 40000: Data Compare Match Framing Error Flag */ +#define R_SCI_B_CSR_ORER (1 << 24) /* 1000000: Overrun Error Flag */ +#define R_SCI_B_CSR_MFF (1 << 26) /* 4000000: Mode Fault Flag */ +#define R_SCI_B_CSR_PER (1 << 27) /* 8000000: Parity Error Flag */ +#define R_SCI_B_CSR_FER (1 << 28) /* 10000000: Framing Error Flag */ +#define R_SCI_B_CSR_TDRE (1 << 29) /* 20000000: Transmit Data Empty Flag */ +#define R_SCI_B_CSR_TEND (1 << 30) /* 40000000: Transmit End Flag */ +#define R_SCI_B_CSR_RDRF (1 << 31) /* 80000000: Receive Data Full Flag */ + +/* Simple-I2C Status Register (32-bits) *************************************/ + +#define R_SCI_B_ISR_IICACKR (1 << 0) /* 01: ACK Reception Data Flag */ +#define R_SCI_B_ISR_IICBBS (1 << 2) /* 04: Bus busy flag. */ +#define R_SCI_B_ISR_IICSTIF (1 << 3) /* 08: Issuing of Start, Restart, or Stop Condition Completed Flag */ +#define R_SCI_B_ISR_IICSDAI (1 << 4) /* 10: SDA input monitor bit. */ +#define R_SCI_B_ISR_IICSCLI (1 << 5) /* 20: SCL input monitor bit */ + +/* FIFO Receive Status Register (32-bits) ***********************************/ + +#define R_SCI_B_FRSR_DR (1 << 0) /* 01: Receive Data Ready flag */ +#define R_SCI_B_FRSR_BRK (1 << 1) /* 02: Break detection signal flag */ +#define R_SCI_B_FRSR_R_SHIFT (8) +#define R_SCI_B_FRSR_R_MASK (0x3f) +#define R_SCI_B_FRSR_PNUM_SHIFT (16) +#define R_SCI_B_FRSR_PNUM_MASK (0x3f) +#define R_SCI_B_FRSR_FNUM_SHIFT (24) +#define R_SCI_B_FRSR_FNUM_MASK (0x3f) + +/* FIFO Transmit Status Register (32-bits) **********************************/ + +#define R_SCI_B_FTSR_T_SHIFT (0) +#define R_SCI_B_FTSR_T_MASK (0x3f) + +/* Manchester Status Register (32-bits) *************************************/ + +#define R_SCI_B_MSR_PFER (1 << 0) /* 01: Preface Error Register */ +#define R_SCI_B_MSR_SYER (1 << 1) /* 02: Sync Error Register */ +#define R_SCI_B_MSR_SBER (1 << 2) /* 04: Start bit Error Register */ +#define R_SCI_B_MSR_MER (1 << 4) /* 10: Manchester error flag */ +#define R_SCI_B_MSR_RSYNC (1 << 6) /* 40: Receive sync data bit. */ + +/* Simple-LIN(SCIX) Status Register 0 (32-bits) *****************************/ + +#define R_SCI_B_XSR0_SFSF (1 << 0) /* 01: Start Frame Status Flag */ +#define R_SCI_B_XSR0_RXDSF (1 << 1) /* 02: RXD input Status Flag */ +#define R_SCI_B_XSR0_BFOF (1 << 8) /* 100: Break Field Output end Flag */ +#define R_SCI_B_XSR0_BCDF (1 << 9) /* 200: Bus Collision Detection Flag */ +#define R_SCI_B_XSR0_BFDF (1 << 10) /* 400: Break Field Detection Flag */ +#define R_SCI_B_XSR0_CF0MF (1 << 11) /* 800: Control Field 0 Match Flag */ +#define R_SCI_B_XSR0_CF1MF (1 << 12) /* 1000: Control Field 1 Match Flag */ +#define R_SCI_B_XSR0_PIBDF (1 << 13) /* 2000: Priority Interrupt Bit Detection Flag */ +#define R_SCI_B_XSR0_COF (1 << 14) /* 4000: Counter Over flow Flag */ +#define R_SCI_B_XSR0_AEDF (1 << 15) /* 8000: Active Edge Detection Flag */ +#define R_SCI_B_XSR0_CF0RD_SHIFT (16) +#define R_SCI_B_XSR0_CF0RD_MASK (0xff) +#define R_SCI_B_XSR0_CF1RD_SHIFT (24) +#define R_SCI_B_XSR0_CF1RD_MASK (0xff) + +/* Simple-LIN(SCIX) Status Register 1 (32-bits) *****************************/ + +#define R_SCI_B_XSR1_TCNT_SHIFT (0) +#define R_SCI_B_XSR1_TCNT_MASK (0xffff) + +/* Common Flag Clear Register (32-bits) *************************************/ + +#define R_SCI_B_CFCLR_ERSC (1 << 4) /* 10: ERS Clear bit */ +#define R_SCI_B_CFCLR_DCMFC (1 << 16) /* 10000: DCMF Clear bit */ +#define R_SCI_B_CFCLR_DPERC (1 << 17) /* 20000: DPER Clear bit */ +#define R_SCI_B_CFCLR_DFERC (1 << 18) /* 40000: DFER Clear bit */ +#define R_SCI_B_CFCLR_ORERC (1 << 24) /* 1000000: ORER Clear bit */ +#define R_SCI_B_CFCLR_MFFC (1 << 26) /* 4000000: MFF Clear bit */ +#define R_SCI_B_CFCLR_PERC (1 << 27) /* 8000000: PER Clear bit */ +#define R_SCI_B_CFCLR_FERC (1 << 28) /* 10000000: FER Clear bit */ +#define R_SCI_B_CFCLR_TDREC (1 << 29) /* 20000000: TDRE Clear bit */ +#define R_SCI_B_CFCLR_RDRFC (1 << 31) /* 80000000: RDRF Clear bit */ + +/* Common Flag Clear Register (16-bits) *************************************/ + +#define R_SCI_B_CFCLR_HA_L_ERSC (1 << 4) /* 10: ERS Clear bit */ + +/* Common Flag Clear Register (8-bits) **************************************/ + +#define R_SCI_B_CFCLR_BY_LL_ERSC (1 << 4) /* 10: ERS Clear bit */ + +/* Common Flag Clear Register (16-bits) *************************************/ + +#define R_SCI_B_CFCLR_HA_H_DCMFC (1 << 0) /* 01: DCMF Clear bit */ +#define R_SCI_B_CFCLR_HA_H_DPERC (1 << 1) /* 02: DPER Clear bit */ +#define R_SCI_B_CFCLR_HA_H_DFERC (1 << 2) /* 04: DFER Clear bit */ +#define R_SCI_B_CFCLR_HA_H_ORERC (1 << 8) /* 100: ORER Clear bit */ +#define R_SCI_B_CFCLR_HA_H_MFFC (1 << 10) /* 400: MFF Clear bit */ +#define R_SCI_B_CFCLR_HA_H_PERC (1 << 11) /* 800: PER Clear bit */ +#define R_SCI_B_CFCLR_HA_H_FERC (1 << 12) /* 1000: FER Clear bit */ +#define R_SCI_B_CFCLR_HA_H_TDREC (1 << 13) /* 2000: TDRE Clear bit */ +#define R_SCI_B_CFCLR_HA_H_RDRFC (1 << 15) /* 8000: RDRF Clear bit */ + +/* Common Flag Clear Register (8-bits) **************************************/ + +#define R_SCI_B_CFCLR_BY_HL_DCMFC (1 << 0) /* 01: DCMF Clear bit */ +#define R_SCI_B_CFCLR_BY_HL_DPERC (1 << 1) /* 02: DPER Clear bit */ +#define R_SCI_B_CFCLR_BY_HL_DFERC (1 << 2) /* 04: DFER Clear bit */ + +/* Common Flag Clear Register (8-bits) **************************************/ + +#define R_SCI_B_CFCLR_BY_HH_ORERC (1 << 0) /* 01: ORER Clear bit */ +#define R_SCI_B_CFCLR_BY_HH_MFFC (1 << 2) /* 04: MFF Clear bit */ +#define R_SCI_B_CFCLR_BY_HH_PERC (1 << 3) /* 08: PER Clear bit */ +#define R_SCI_B_CFCLR_BY_HH_FERC (1 << 4) /* 10: FER Clear bit */ +#define R_SCI_B_CFCLR_BY_HH_TDREC (1 << 5) /* 20: TDRE Clear bit */ +#define R_SCI_B_CFCLR_BY_HH_RDRFC (1 << 7) /* 80: RDRF Clear bit */ + +/* Simple-I2C Flag Clear Register (32-bits) *********************************/ + +#define R_SCI_B_ICFCLR_IICBBSC (1 << 2) /* 04: IICBBS Clear bit */ +#define R_SCI_B_ICFCLR_IICSTIFC (1 << 3) /* 08: IICSTIF Clear bit */ + +/* Simple-I2C Flag Clear Register (16-bits) *********************************/ + +#define R_SCI_B_ICFCLR_HA_L_IICBBSC (1 << 2) /* 04: IICBBSC Clear bit */ +#define R_SCI_B_ICFCLR_HA_L_IICSTIFC (1 << 3) /* 08: IICSTIF Clear bit */ + +/* Simple-I2C Flag Clear Register (8-bits) **********************************/ + +#define R_SCI_B_ICFCLR_BY_LL_IICBBSC (1 << 2) /* 04: IICBBSC Clear bit */ +#define R_SCI_B_ICFCLR_BY_LL_IICSTIFC (1 << 3) /* 08: IICSTIF Clear bit */ + +/* FIFO Flag Clear Register (32-bits) ***************************************/ + +#define R_SCI_B_FFCLR_DRC (1 << 0) /* 01: DR Clear bit */ +#define R_SCI_B_FFCLR_BRKC (1 << 1) /* 02: BRK Clear bit */ + +/* FIFO Flag Clear Register (16-bits) ***************************************/ + +#define R_SCI_B_FFCLR_HA_L_DRC (1 << 0) /* 01: DR Clear bit */ +#define R_SCI_B_FFCLR_HA_L_BRKC (1 << 1) /* 02: BRK Clear bit */ + +/* FIFO Flag Clear Register (8-bits) ****************************************/ + +#define R_SCI_B_FFCLR_BY_LL_DRC (1 << 0) /* 01: DR Clear bit */ +#define R_SCI_B_FFCLR_BY_LL_BRKC (1 << 1) /* 02: BRK Clear bit */ + +/* Manchester Flag Clear Register (32-bits) *********************************/ + +#define R_SCI_B_MFCLR_PFERC (1 << 0) /* 01: PFER Clear bit */ +#define R_SCI_B_MFCLR_SYERC (1 << 1) /* 02: SYER Clear bit */ +#define R_SCI_B_MFCLR_SBERC (1 << 2) /* 04: SBER Clear bit */ +#define R_SCI_B_MFCLR_MERC (1 << 4) /* 10: MER Clear bit */ + +/* Manchester Flag Clear Register (16-bits) *********************************/ + +#define R_SCI_B_MFCLR_HA_L_PFERC (1 << 0) /* 01: PFER Clear bit */ +#define R_SCI_B_MFCLR_HA_L_SYERC (1 << 1) /* 02: SYER Clear bit */ +#define R_SCI_B_MFCLR_HA_L_SBERC (1 << 2) /* 04: SBER Clear bit */ +#define R_SCI_B_MFCLR_HA_L_MERC (1 << 4) /* 10: MER Clear bit */ + +/* Manchester Flag Clear Register (8-bits) **********************************/ + +#define R_SCI_B_MFCLR_BY_LL_PFERC (1 << 0) /* 01: PFER Clear bit */ +#define R_SCI_B_MFCLR_BY_LL_SYERC (1 << 1) /* 02: SYER Clear bit */ +#define R_SCI_B_MFCLR_BY_LL_SBERC (1 << 2) /* 04: SBER Clear bit */ +#define R_SCI_B_MFCLR_BY_LL_MERC (1 << 4) /* 10: MER Clear bit */ + +/* Simpe-LIN(SCIX) Flag Clear Register (32-bits) ****************************/ + +#define R_SCI_B_XFCLR_BFOC (1 << 8) /* 100: BFO Clear bit */ +#define R_SCI_B_XFCLR_BCDC (1 << 9) /* 200: BCD Clear bit */ +#define R_SCI_B_XFCLR_BFDC (1 << 10) /* 400: BFD Clear bit */ +#define R_SCI_B_XFCLR_CF0MC (1 << 11) /* 800: CF0M Clear bit */ +#define R_SCI_B_XFCLR_CF1MC (1 << 12) /* 1000: CF1M Clear bit */ +#define R_SCI_B_XFCLR_PIBDC (1 << 13) /* 2000: PIBD Clear bit */ +#define R_SCI_B_XFCLR_COFC (1 << 14) /* 4000: COF Clear bit */ +#define R_SCI_B_XFCLR_AEDC (1 << 15) /* 8000: AED Clear bit */ + +/* Simpe-LIN(SCIX) Flag Clear Register (16-bits) ****************************/ + +#define R_SCI_B_XFCLR_HA_L_BFOC (1 << 8) /* 100: BFO Clear bit */ +#define R_SCI_B_XFCLR_HA_L_BCDC (1 << 9) /* 200: BCD Clear bit */ +#define R_SCI_B_XFCLR_HA_L_BFDC (1 << 10) /* 400: BFD Clear bit */ +#define R_SCI_B_XFCLR_HA_L_CF0MC (1 << 11) /* 800: CF0M Clear bit */ +#define R_SCI_B_XFCLR_HA_L_CF1MC (1 << 12) /* 1000: CF1M Clear bit */ +#define R_SCI_B_XFCLR_HA_L_PIBDC (1 << 13) /* 2000: PIBD Clear bit */ +#define R_SCI_B_XFCLR_HA_L_COFC (1 << 14) /* 4000: COF Clear bit */ +#define R_SCI_B_XFCLR_HA_L_AEDC (1 << 15) /* 8000: AED Clear bit */ + +/* Simpe-LIN(SCIX) Flag Clear Register (8-bits) *****************************/ + +#define R_SCI_B_XFCLR_BY_LH_BFOC (1 << 0) /* 01: BFO Clear bit */ +#define R_SCI_B_XFCLR_BY_LH_BCDC (1 << 1) /* 02: BCD Clear bit */ +#define R_SCI_B_XFCLR_BY_LH_BFDC (1 << 2) /* 04: BFD Clear bit */ +#define R_SCI_B_XFCLR_BY_LH_CF0MC (1 << 3) /* 08: CF0M Clear bit */ +#define R_SCI_B_XFCLR_BY_LH_CF1MC (1 << 4) /* 10: CF1M Clear bit */ +#define R_SCI_B_XFCLR_BY_LH_PIBDC (1 << 5) /* 20: PIBD Clear bit */ +#define R_SCI_B_XFCLR_BY_LH_COFC (1 << 6) /* 40: COF Clear bit */ +#define R_SCI_B_XFCLR_BY_LH_AEDC (1 << 7) /* 80: AED Clear bit */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_SCI_H */ diff --git a/arch/arm/src/ra8m1/hardware/ra8m1_system.h b/arch/arm/src/ra8m1/hardware/ra8m1_system.h new file mode 100644 index 00000000000..b91e5317a02 --- /dev/null +++ b/arch/arm/src/ra8m1/hardware/ra8m1_system.h @@ -0,0 +1,1635 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/hardware/ra8m1_system.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_SYSTEM_H +#define __ARCH_ARM_SRC_RA8M1_HARDWARE_RA8M1_SYSTEM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/ra8m1_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define R_SYSTEM_SBYCR_OFFSET 0x000c /* Standby Control Register (8-bits) */ +#define R_SYSTEM_SSCR2_OFFSET 0x000e /* Software Standby Control Register 2 (8-bits) */ +#define R_SYSTEM_FLSCR_OFFSET 0x0010 /* Flash Standby Control Register (8-bits) */ +#define R_SYSTEM_SCKDIVCR_OFFSET 0x0020 /* System Clock Division Control Register (32-bits) */ +#define R_SYSTEM_SCKDIVCR2_OFFSET 0x0024 /* System Clock Division Control Register 2 (8-bits) */ +#define R_SYSTEM_SCKSCR_OFFSET 0x0026 /* System Clock Source Control Register (8-bits) */ +#define R_SYSTEM_PLLCCR_OFFSET 0x0028 /* PLL Clock Control Register (16-bits) */ +#define R_SYSTEM_PLLCR_OFFSET 0x002a /* PLL Control Register (8-bits) */ +#define R_SYSTEM_BCKCR_OFFSET 0x0030 /* External Bus Clock Control Register (8-bits) */ +#define R_SYSTEM_MOSCCR_OFFSET 0x0032 /* Main Clock Oscillator Control Register (8-bits) */ +#define R_SYSTEM_HOCOCR_OFFSET 0x0036 /* High-Speed On-Chip Oscillator Control Register (8-bits) */ +#define R_SYSTEM_MOCOCR_OFFSET 0x0038 /* Middle-Speed On-Chip Oscillator Control Register (8-bits) */ +#define R_SYSTEM_FLLCR1_OFFSET 0x0039 /* FLL Control Register 1 (8-bits) */ +#define R_SYSTEM_FLLCR2_OFFSET 0x003a /* FLL Control Register 2 (16-bits) */ +#define R_SYSTEM_OSCSF_OFFSET 0x003c /* Oscillation Stabilization Flag Register (8-bits) */ +#define R_SYSTEM_CKOCR_OFFSET 0x003e /* Clock Out Control Register (8-bits) */ +#define R_SYSTEM_TRCKCR_OFFSET 0x003f /* Trace Clock Control Register (8-bits) */ +#define R_SYSTEM_OSTDCR_OFFSET 0x0040 /* Oscillation Stop Detection Control Register (8-bits) */ +#define R_SYSTEM_OSTDSR_OFFSET 0x0041 /* Oscillation Stop Detection Status Register (8-bits) */ +#define R_SYSTEM_OSCMONR_OFFSET 0x0043 /* Oscillator Monitor Register (8-bits) */ +#define R_SYSTEM_PLL2CCR_OFFSET 0x0048 /* PLL2 Clock Control Register (16-bits) */ +#define R_SYSTEM_PLL2CR_OFFSET 0x004a /* PLL2 Control Register (8-bits) */ +#define R_SYSTEM_PLLCCR2_OFFSET 0x004c /* PLL Clock Control Register 2 (16-bits) */ +#define R_SYSTEM_PLL2CCR2_OFFSET 0x004e /* PLL2 Clock Control Register 2 (16-bits) */ +#define R_SYSTEM_EBCKOCR_OFFSET 0x0052 /* External Bus Clock Output Control Register (8-bits) */ +#define R_SYSTEM_SDCKOCR_OFFSET 0x0053 /* SDRAM Clock Output Control Register (8-bits) */ +#define R_SYSTEM_SCICKDIVCR_OFFSET 0x0054 /* SCI clock Division control register (8-bits) */ +#define R_SYSTEM_SCICKCR_OFFSET 0x0055 /* SCI clock control register (8-bits) */ +#define R_SYSTEM_SPICKDIVCR_OFFSET 0x0056 /* SPI clock Division control register (8-bits) */ +#define R_SYSTEM_SPICKCR_OFFSET 0x0057 /* SPI clock control register (8-bits) */ +#define R_SYSTEM_ADCCKDIVCR_OFFSET 0x005a /* ADC clock Division control register (8-bits) */ +#define R_SYSTEM_ADCCKCR_OFFSET 0x005b /* ADC clock control register (8-bits) */ +#define R_SYSTEM_GPTCKDIVCR_OFFSET 0x005c /* GPT clock Division control register (8-bits) */ +#define R_SYSTEM_GPTCKCR_OFFSET 0x005d /* GPT clock control register (8-bits) */ +#define R_SYSTEM_LCDCKDIVCR_OFFSET 0x005e /* LCD clock Division control register (8-bits) */ +#define R_SYSTEM_LCDCKCR_OFFSET 0x005f /* LCD clock control register (8-bits) */ +#define R_SYSTEM_MOCOUTCR_OFFSET 0x0061 /* MOCO User Trimming Control Register (8-bits) */ +#define R_SYSTEM_HOCOUTCR_OFFSET 0x0062 /* HOCO User Trimming Control Register (8-bits) */ +#define R_SYSTEM_USBCKDIVCR_OFFSET 0x006c /* USB clock Division control register (8-bits) */ +#define R_SYSTEM_OCTACKDIVCR_OFFSET 0x006d /* Octal-SPI clock Division control register (8-bits) */ +#define R_SYSTEM_CANFDCKDIVCR_OFFSET 0x006e /* CANFD Core clock Division control register (8-bits) */ +#define R_SYSTEM_USB60CKDIVCR_OFFSET 0x006f /* USB60 clock Division control register (8-bits) */ +#define R_SYSTEM_I3CCKDIVCR_OFFSET 0x0070 /* I3C clock Division control register (8-bits) */ +#define R_SYSTEM_USBCKCR_OFFSET 0x0074 /* USB clock control register (8-bits) */ +#define R_SYSTEM_OCTACKCR_OFFSET 0x0075 /* Octal-SPI clock control register (8-bits) */ +#define R_SYSTEM_CANFDCKCR_OFFSET 0x0076 /* CANFD Core clock control register (8-bits) */ +#define R_SYSTEM_USB60CKCR_OFFSET 0x0077 /* USB60 clock control register (8-bits) */ +#define R_SYSTEM_I3CCKCR_OFFSET 0x0078 /* I3C clock control register (8-bits) */ +#define R_SYSTEM_MOSCSCR_OFFSET 0x007c /* Main Clock Oscillator Standby Control Register (8-bits) */ +#define R_SYSTEM_HOCOSCR_OFFSET 0x007d /* High-Speed On-Chip Oscillator Standby Control Register (8-bits) */ +#define R_SYSTEM_OPCCR_OFFSET 0x00a0 /* Operating Power Control Register (8-bits) */ +#define R_SYSTEM_MOSCWTCR_OFFSET 0x00a2 /* Main Clock Oscillator Wait Control Register (8-bits) */ +#define R_SYSTEM_RSTSR1_OFFSET 0x00c0 /* Reset Status Register 1 (32-bits) */ +#define R_SYSTEM_SYRACCR_OFFSET 0x00cc /* System Register Access Control Register (8-bits) */ +#define R_SYSTEM_PVDCR1_OFFSET 0x00e0 /* Voltage Monitor %s Circuit Control Register 1 (8-bits) */ +#define R_SYSTEM_PVDSR_OFFSET 0x00e1 /* Voltage Monitor %s Circuit Status Register (8-bits) */ +#define R_SYSTEM_CRVSYSCR_OFFSET 0x00f0 /* Clock Recovery System Control Register (8-bits) */ +#define R_SYSTEM_PDCTRGD_OFFSET 0x0110 /* Graphics Power Domain Control Register (8-bits) */ +#define R_SYSTEM_PDRAMSCR0_OFFSET 0x0140 /* SRAM power domain Standby Control Register 0 (16-bits) */ +#define R_SYSTEM_PDRAMSCR1_OFFSET 0x0142 /* SRAM power domain Standby Control Register 1 (8-bits) */ +#define R_SYSTEM_VBRSABAR_OFFSET 0x03b0 /* VBATT Backup Register Security Attribute Boundary Address Register (16-bits) */ +#define R_SYSTEM_VBRPABARS_OFFSET 0x03b4 /* VBATT Backup Register Privilege Attribute Boundary Address Register for Secure Region (16-bits) */ +#define R_SYSTEM_VBRPABARNS_OFFSET 0x03b8 /* VBATT Backup Register Privilege Attribute Boundary Address Register for Non-secure Region (16-bits) */ +#define R_SYSTEM_CGFSAR_OFFSET 0x03c0 /* Clock Generation Function Security Attribute Register (32-bits) */ +#define R_SYSTEM_RSTSAR_OFFSET 0x03c4 /* Reset Security Attribution Register (32-bits) */ +#define R_SYSTEM_LPMSAR_OFFSET 0x03c8 /* Low Power Mode Security Attribution Register (32-bits) */ +#define R_SYSTEM_PVDSAR_OFFSET 0x03cc /* Programmable Voltage Detection Security Attribution Register (32-bits) */ +#define R_SYSTEM_BBFSAR_OFFSET 0x03d0 /* Battery Backup Function Security Attribute Register (32-bits) */ +#define R_SYSTEM_PGCSAR_OFFSET 0x03d8 /* Power Gating Control Security Attribution Register (32-bits) */ +#define R_SYSTEM_DPFSAR_OFFSET 0x03e0 /* Deep Standby Interrupt Factor Security Attribution Register (32-bits) */ +#define R_SYSTEM_RSCSAR_OFFSET 0x03e4 /* RAM Standby Control Security Attribution Register (32-bits) */ +#define R_SYSTEM_PRCR_S_OFFSET 0x03fa /* Protect Register for Secure Register (16-bits) */ +#define R_SYSTEM_PRCR_NS_OFFSET 0x03fe /* Protect Register for Non-secure Register (16-bits) */ +#define R_SYSTEM_LOCOCR_OFFSET 0x0400 /* Low-Speed On-Chip Oscillator Control Register (8-bits) */ +#define R_SYSTEM_LOCOUTCR_OFFSET 0x0402 /* LOCO User Trimming Control Register (8-bits) */ +#define R_SYSTEM_DPSBYCR_OFFSET 0x0a00 /* Deep Standby Control Register (8-bits) */ +#define R_SYSTEM_DPSWCR_OFFSET 0x0a04 /* Deep Standby Wait Control Register (8-bits) */ +#define R_SYSTEM_DPSIER0_OFFSET 0x0a08 /* Deep Standby Interrupt Enable Register 0 (8-bits) */ +#define R_SYSTEM_DPSIER1_OFFSET 0x0a0c /* Deep Standby Interrupt Enable Register 1 (8-bits) */ +#define R_SYSTEM_DPSIER2_OFFSET 0x0a10 /* Deep Standby Interrupt Enable Register 2 (8-bits) */ +#define R_SYSTEM_DPSIER3_OFFSET 0x0a14 /* Deep Standby Interrupt Enable Register 3 (8-bits) */ +#define R_SYSTEM_DPSIFR0_OFFSET 0x0a18 /* Deep Standby Interrupt Flag Register 0 (8-bits) */ +#define R_SYSTEM_DPSIFR1_OFFSET 0x0a1c /* Deep Standby Interrupt Flag Register 1 (8-bits) */ +#define R_SYSTEM_DPSIFR2_OFFSET 0x0a20 /* Deep Standby Interrupt Flag Register 2 (8-bits) */ +#define R_SYSTEM_DPSIFR3_OFFSET 0x0a24 /* Deep Standby Interrupt Flag Register 3 (8-bits) */ +#define R_SYSTEM_DPSIEGR0_OFFSET 0x0a28 /* Deep Standby Interrupt Edge Register 0 (8-bits) */ +#define R_SYSTEM_DPSIEGR1_OFFSET 0x0a2c /* Deep Standby Interrupt Edge Register 1 (8-bits) */ +#define R_SYSTEM_DPSIEGR2_OFFSET 0x0a30 /* Deep Standby Interrupt Edge Register 2 (8-bits) */ +#define R_SYSTEM_SYOCDCR_OFFSET 0x0a38 /* System Control OCD Control Register (8-bits) */ +#define R_SYSTEM_RSTSR0_OFFSET 0x0a40 /* Reset Status Register 0 (8-bits) */ +#define R_SYSTEM_RSTSR2_OFFSET 0x0a44 /* Reset Status Register 2 (8-bits) */ +#define R_SYSTEM_RSTSR3_OFFSET 0x0a48 /* Reset Status Register 3 (8-bits) */ +#define R_SYSTEM_MOMCR_OFFSET 0x0a50 /* Main Clock Oscillator Mode Oscillation Control Register (8-bits) */ +#define R_SYSTEM_FWEPROR_OFFSET 0x0a54 /* Flash Write Erase Protect Register (8-bits) */ +#define R_SYSTEM_PVD1CMPCR_OFFSET 0x0a58 /* Voltage Monitor 1 Comparator Control Register (8-bits) */ +#define R_SYSTEM_PVD2CMPCR_OFFSET 0x0a5c /* Voltage Monitor 2 Comparator Control Register (8-bits) */ +#define R_SYSTEM_PVDCR0_OFFSET 0x0a70 /* Voltage Monitor %s Circuit Control Register 0 (8-bits) */ +#define R_SYSTEM_VBATTMNSELR_OFFSET 0x0a84 /* Battery Backup Voltage Monitor Function Select Register (8-bits) */ +#define R_SYSTEM_VBTBPCR1_OFFSET 0x0a88 /* VBATT Battery Power Supply Control Register 1 (8-bits) */ +#define R_SYSTEM_LPSCR_OFFSET 0x0a90 /* Low Power State Control Register (8-bits) */ +#define R_SYSTEM_SSCR1_OFFSET 0x0a98 /* Software Standby Control Register 1 (8-bits) */ +#define R_SYSTEM_LVOCR_OFFSET 0x0ab0 /* Low Power State Control Register (8-bits) */ +#define R_SYSTEM_SYRSTMSK0_OFFSET 0x0ad0 /* System Reset Mask Control Register0 (8-bits) */ +#define R_SYSTEM_SYRSTMSK1_OFFSET 0x0ad4 /* System Reset Mask Control Register1 (8-bits) */ +#define R_SYSTEM_SYRSTMSK2_OFFSET 0x0ad8 /* System Reset Mask Control Register2 (8-bits) */ +#define R_SYSTEM_PLL1LDOCR_OFFSET 0x0b04 /* PLL1-LDO Control Register (8-bits) */ +#define R_SYSTEM_PLL2LDOCR_OFFSET 0x0b08 /* PLL2-LDO Control Register (8-bits) */ +#define R_SYSTEM_HOCOLDOCR_OFFSET 0x0b0c /* HOCO-LDO Control Register (8-bits) */ +#define R_SYSTEM_MOMCR2_OFFSET 0x0b10 /* Main Clock Oscillator Mode Control Register 2 (8-bits) */ +#define R_SYSTEM_SOSCCR_OFFSET 0x0c00 /* Sub-clock oscillator control register (8-bits) */ +#define R_SYSTEM_SOMCR_OFFSET 0x0c01 /* Sub Clock Oscillator Mode Control Register (8-bits) */ +#define R_SYSTEM_VBTBER_OFFSET 0x0c40 /* VBATT Backup Enable Register (8-bits) */ +#define R_SYSTEM_VBTBPCR2_OFFSET 0x0c45 /* VBATT Battery Power Supply Control Register 2 (8-bits) */ +#define R_SYSTEM_VBTBPSR_OFFSET 0x0c46 /* VBATT Battery Power Supply Status Register (8-bits) */ +#define R_SYSTEM_VBTADSR_OFFSET 0x0c48 /* VBATT Tamper detection Status Register (8-bits) */ +#define R_SYSTEM_VBTADCR1_OFFSET 0x0c49 /* VBATT Tamper detection Control Register 1 (8-bits) */ +#define R_SYSTEM_VBTADCR2_OFFSET 0x0c4a /* VBATT Tamper detection Control Register 2 (8-bits) */ +#define R_SYSTEM_VBTICTLR_OFFSET 0x0c4c /* VBATT Input Control Register (8-bits) */ +#define R_SYSTEM_VBTICTLR2_OFFSET 0x0c4d /* VBATT Input Control Register 2 (8-bits) */ +#define R_SYSTEM_VBTIMONR_OFFSET 0x0c4e /* VBATT Input Monitor Register (8-bits) */ +#define R_SYSTEM_VBTBKR_OFFSET 0x0d00 /* VBATT Backup Register %s (8-bits) */ + +/* Register Addresses *******************************************************/ + +/* SYSTEM Registers */ + +#define R_SYSTEM_SBYCR (R_SYSTEM_BASE + R_SYSTEM_SBYCR_OFFSET) +#define R_SYSTEM_SSCR2 (R_SYSTEM_BASE + R_SYSTEM_SSCR2_OFFSET) +#define R_SYSTEM_FLSCR (R_SYSTEM_BASE + R_SYSTEM_FLSCR_OFFSET) +#define R_SYSTEM_SCKDIVCR (R_SYSTEM_BASE + R_SYSTEM_SCKDIVCR_OFFSET) +#define R_SYSTEM_SCKDIVCR2 (R_SYSTEM_BASE + R_SYSTEM_SCKDIVCR2_OFFSET) +#define R_SYSTEM_SCKSCR (R_SYSTEM_BASE + R_SYSTEM_SCKSCR_OFFSET) +#define R_SYSTEM_PLLCCR (R_SYSTEM_BASE + R_SYSTEM_PLLCCR_OFFSET) +#define R_SYSTEM_PLLCR (R_SYSTEM_BASE + R_SYSTEM_PLLCR_OFFSET) +#define R_SYSTEM_BCKCR (R_SYSTEM_BASE + R_SYSTEM_BCKCR_OFFSET) +#define R_SYSTEM_MOSCCR (R_SYSTEM_BASE + R_SYSTEM_MOSCCR_OFFSET) +#define R_SYSTEM_HOCOCR (R_SYSTEM_BASE + R_SYSTEM_HOCOCR_OFFSET) +#define R_SYSTEM_MOCOCR (R_SYSTEM_BASE + R_SYSTEM_MOCOCR_OFFSET) +#define R_SYSTEM_FLLCR1 (R_SYSTEM_BASE + R_SYSTEM_FLLCR1_OFFSET) +#define R_SYSTEM_FLLCR2 (R_SYSTEM_BASE + R_SYSTEM_FLLCR2_OFFSET) +#define R_SYSTEM_OSCSF (R_SYSTEM_BASE + R_SYSTEM_OSCSF_OFFSET) +#define R_SYSTEM_CKOCR (R_SYSTEM_BASE + R_SYSTEM_CKOCR_OFFSET) +#define R_SYSTEM_TRCKCR (R_SYSTEM_BASE + R_SYSTEM_TRCKCR_OFFSET) +#define R_SYSTEM_OSTDCR (R_SYSTEM_BASE + R_SYSTEM_OSTDCR_OFFSET) +#define R_SYSTEM_OSTDSR (R_SYSTEM_BASE + R_SYSTEM_OSTDSR_OFFSET) +#define R_SYSTEM_OSCMONR (R_SYSTEM_BASE + R_SYSTEM_OSCMONR_OFFSET) +#define R_SYSTEM_PLL2CCR (R_SYSTEM_BASE + R_SYSTEM_PLL2CCR_OFFSET) +#define R_SYSTEM_PLL2CR (R_SYSTEM_BASE + R_SYSTEM_PLL2CR_OFFSET) +#define R_SYSTEM_PLLCCR2 (R_SYSTEM_BASE + R_SYSTEM_PLLCCR2_OFFSET) +#define R_SYSTEM_PLL2CCR2 (R_SYSTEM_BASE + R_SYSTEM_PLL2CCR2_OFFSET) +#define R_SYSTEM_EBCKOCR (R_SYSTEM_BASE + R_SYSTEM_EBCKOCR_OFFSET) +#define R_SYSTEM_SDCKOCR (R_SYSTEM_BASE + R_SYSTEM_SDCKOCR_OFFSET) +#define R_SYSTEM_SCICKDIVCR (R_SYSTEM_BASE + R_SYSTEM_SCICKDIVCR_OFFSET) +#define R_SYSTEM_SCICKCR (R_SYSTEM_BASE + R_SYSTEM_SCICKCR_OFFSET) +#define R_SYSTEM_SPICKDIVCR (R_SYSTEM_BASE + R_SYSTEM_SPICKDIVCR_OFFSET) +#define R_SYSTEM_SPICKCR (R_SYSTEM_BASE + R_SYSTEM_SPICKCR_OFFSET) +#define R_SYSTEM_ADCCKDIVCR (R_SYSTEM_BASE + R_SYSTEM_ADCCKDIVCR_OFFSET) +#define R_SYSTEM_ADCCKCR (R_SYSTEM_BASE + R_SYSTEM_ADCCKCR_OFFSET) +#define R_SYSTEM_GPTCKDIVCR (R_SYSTEM_BASE + R_SYSTEM_GPTCKDIVCR_OFFSET) +#define R_SYSTEM_GPTCKCR (R_SYSTEM_BASE + R_SYSTEM_GPTCKCR_OFFSET) +#define R_SYSTEM_LCDCKDIVCR (R_SYSTEM_BASE + R_SYSTEM_LCDCKDIVCR_OFFSET) +#define R_SYSTEM_LCDCKCR (R_SYSTEM_BASE + R_SYSTEM_LCDCKCR_OFFSET) +#define R_SYSTEM_MOCOUTCR (R_SYSTEM_BASE + R_SYSTEM_MOCOUTCR_OFFSET) +#define R_SYSTEM_HOCOUTCR (R_SYSTEM_BASE + R_SYSTEM_HOCOUTCR_OFFSET) +#define R_SYSTEM_USBCKDIVCR (R_SYSTEM_BASE + R_SYSTEM_USBCKDIVCR_OFFSET) +#define R_SYSTEM_OCTACKDIVCR (R_SYSTEM_BASE + R_SYSTEM_OCTACKDIVCR_OFFSET) +#define R_SYSTEM_CANFDCKDIVCR (R_SYSTEM_BASE + R_SYSTEM_CANFDCKDIVCR_OFFSET) +#define R_SYSTEM_USB60CKDIVCR (R_SYSTEM_BASE + R_SYSTEM_USB60CKDIVCR_OFFSET) +#define R_SYSTEM_I3CCKDIVCR (R_SYSTEM_BASE + R_SYSTEM_I3CCKDIVCR_OFFSET) +#define R_SYSTEM_USBCKCR (R_SYSTEM_BASE + R_SYSTEM_USBCKCR_OFFSET) +#define R_SYSTEM_OCTACKCR (R_SYSTEM_BASE + R_SYSTEM_OCTACKCR_OFFSET) +#define R_SYSTEM_CANFDCKCR (R_SYSTEM_BASE + R_SYSTEM_CANFDCKCR_OFFSET) +#define R_SYSTEM_USB60CKCR (R_SYSTEM_BASE + R_SYSTEM_USB60CKCR_OFFSET) +#define R_SYSTEM_I3CCKCR (R_SYSTEM_BASE + R_SYSTEM_I3CCKCR_OFFSET) +#define R_SYSTEM_MOSCSCR (R_SYSTEM_BASE + R_SYSTEM_MOSCSCR_OFFSET) +#define R_SYSTEM_HOCOSCR (R_SYSTEM_BASE + R_SYSTEM_HOCOSCR_OFFSET) +#define R_SYSTEM_OPCCR (R_SYSTEM_BASE + R_SYSTEM_OPCCR_OFFSET) +#define R_SYSTEM_MOSCWTCR (R_SYSTEM_BASE + R_SYSTEM_MOSCWTCR_OFFSET) +#define R_SYSTEM_RSTSR1 (R_SYSTEM_BASE + R_SYSTEM_RSTSR1_OFFSET) +#define R_SYSTEM_SYRACCR (R_SYSTEM_BASE + R_SYSTEM_SYRACCR_OFFSET) +#define R_SYSTEM_PVDCR1(p) (R_SYSTEM_BASE + R_SYSTEM_PVDCR1_OFFSET + (p)*0x0002) +#define R_SYSTEM_PVDSR(p) (R_SYSTEM_BASE + R_SYSTEM_PVDSR_OFFSET + (p)*0x0002) +#define R_SYSTEM_CRVSYSCR (R_SYSTEM_BASE + R_SYSTEM_CRVSYSCR_OFFSET) +#define R_SYSTEM_PDCTRGD (R_SYSTEM_BASE + R_SYSTEM_PDCTRGD_OFFSET) +#define R_SYSTEM_PDRAMSCR0 (R_SYSTEM_BASE + R_SYSTEM_PDRAMSCR0_OFFSET) +#define R_SYSTEM_PDRAMSCR1 (R_SYSTEM_BASE + R_SYSTEM_PDRAMSCR1_OFFSET) +#define R_SYSTEM_VBRSABAR (R_SYSTEM_BASE + R_SYSTEM_VBRSABAR_OFFSET) +#define R_SYSTEM_VBRPABARS (R_SYSTEM_BASE + R_SYSTEM_VBRPABARS_OFFSET) +#define R_SYSTEM_VBRPABARNS (R_SYSTEM_BASE + R_SYSTEM_VBRPABARNS_OFFSET) +#define R_SYSTEM_CGFSAR (R_SYSTEM_BASE + R_SYSTEM_CGFSAR_OFFSET) +#define R_SYSTEM_RSTSAR (R_SYSTEM_BASE + R_SYSTEM_RSTSAR_OFFSET) +#define R_SYSTEM_LPMSAR (R_SYSTEM_BASE + R_SYSTEM_LPMSAR_OFFSET) +#define R_SYSTEM_PVDSAR (R_SYSTEM_BASE + R_SYSTEM_PVDSAR_OFFSET) +#define R_SYSTEM_BBFSAR (R_SYSTEM_BASE + R_SYSTEM_BBFSAR_OFFSET) +#define R_SYSTEM_PGCSAR (R_SYSTEM_BASE + R_SYSTEM_PGCSAR_OFFSET) +#define R_SYSTEM_DPFSAR (R_SYSTEM_BASE + R_SYSTEM_DPFSAR_OFFSET) +#define R_SYSTEM_RSCSAR (R_SYSTEM_BASE + R_SYSTEM_RSCSAR_OFFSET) +#define R_SYSTEM_PRCR_S (R_SYSTEM_BASE + R_SYSTEM_PRCR_S_OFFSET) +#define R_SYSTEM_PRCR_NS (R_SYSTEM_BASE + R_SYSTEM_PRCR_NS_OFFSET) +#define R_SYSTEM_LOCOCR (R_SYSTEM_BASE + R_SYSTEM_LOCOCR_OFFSET) +#define R_SYSTEM_LOCOUTCR (R_SYSTEM_BASE + R_SYSTEM_LOCOUTCR_OFFSET) +#define R_SYSTEM_DPSBYCR (R_SYSTEM_BASE + R_SYSTEM_DPSBYCR_OFFSET) +#define R_SYSTEM_DPSWCR (R_SYSTEM_BASE + R_SYSTEM_DPSWCR_OFFSET) +#define R_SYSTEM_DPSIER0 (R_SYSTEM_BASE + R_SYSTEM_DPSIER0_OFFSET) +#define R_SYSTEM_DPSIER1 (R_SYSTEM_BASE + R_SYSTEM_DPSIER1_OFFSET) +#define R_SYSTEM_DPSIER2 (R_SYSTEM_BASE + R_SYSTEM_DPSIER2_OFFSET) +#define R_SYSTEM_DPSIER3 (R_SYSTEM_BASE + R_SYSTEM_DPSIER3_OFFSET) +#define R_SYSTEM_DPSIFR0 (R_SYSTEM_BASE + R_SYSTEM_DPSIFR0_OFFSET) +#define R_SYSTEM_DPSIFR1 (R_SYSTEM_BASE + R_SYSTEM_DPSIFR1_OFFSET) +#define R_SYSTEM_DPSIFR2 (R_SYSTEM_BASE + R_SYSTEM_DPSIFR2_OFFSET) +#define R_SYSTEM_DPSIFR3 (R_SYSTEM_BASE + R_SYSTEM_DPSIFR3_OFFSET) +#define R_SYSTEM_DPSIEGR0 (R_SYSTEM_BASE + R_SYSTEM_DPSIEGR0_OFFSET) +#define R_SYSTEM_DPSIEGR1 (R_SYSTEM_BASE + R_SYSTEM_DPSIEGR1_OFFSET) +#define R_SYSTEM_DPSIEGR2 (R_SYSTEM_BASE + R_SYSTEM_DPSIEGR2_OFFSET) +#define R_SYSTEM_SYOCDCR (R_SYSTEM_BASE + R_SYSTEM_SYOCDCR_OFFSET) +#define R_SYSTEM_RSTSR0 (R_SYSTEM_BASE + R_SYSTEM_RSTSR0_OFFSET) +#define R_SYSTEM_RSTSR2 (R_SYSTEM_BASE + R_SYSTEM_RSTSR2_OFFSET) +#define R_SYSTEM_RSTSR3 (R_SYSTEM_BASE + R_SYSTEM_RSTSR3_OFFSET) +#define R_SYSTEM_MOMCR (R_SYSTEM_BASE + R_SYSTEM_MOMCR_OFFSET) +#define R_SYSTEM_FWEPROR (R_SYSTEM_BASE + R_SYSTEM_FWEPROR_OFFSET) +#define R_SYSTEM_PVD1CMPCR (R_SYSTEM_BASE + R_SYSTEM_PVD1CMPCR_OFFSET) +#define R_SYSTEM_PVD2CMPCR (R_SYSTEM_BASE + R_SYSTEM_PVD2CMPCR_OFFSET) +#define R_SYSTEM_PVDCR0(p) (R_SYSTEM_BASE + R_SYSTEM_PVDCR0_OFFSET + (p)*0x0004) +#define R_SYSTEM_VBATTMNSELR (R_SYSTEM_BASE + R_SYSTEM_VBATTMNSELR_OFFSET) +#define R_SYSTEM_VBTBPCR1 (R_SYSTEM_BASE + R_SYSTEM_VBTBPCR1_OFFSET) +#define R_SYSTEM_LPSCR (R_SYSTEM_BASE + R_SYSTEM_LPSCR_OFFSET) +#define R_SYSTEM_SSCR1 (R_SYSTEM_BASE + R_SYSTEM_SSCR1_OFFSET) +#define R_SYSTEM_LVOCR (R_SYSTEM_BASE + R_SYSTEM_LVOCR_OFFSET) +#define R_SYSTEM_SYRSTMSK0 (R_SYSTEM_BASE + R_SYSTEM_SYRSTMSK0_OFFSET) +#define R_SYSTEM_SYRSTMSK1 (R_SYSTEM_BASE + R_SYSTEM_SYRSTMSK1_OFFSET) +#define R_SYSTEM_SYRSTMSK2 (R_SYSTEM_BASE + R_SYSTEM_SYRSTMSK2_OFFSET) +#define R_SYSTEM_PLL1LDOCR (R_SYSTEM_BASE + R_SYSTEM_PLL1LDOCR_OFFSET) +#define R_SYSTEM_PLL2LDOCR (R_SYSTEM_BASE + R_SYSTEM_PLL2LDOCR_OFFSET) +#define R_SYSTEM_HOCOLDOCR (R_SYSTEM_BASE + R_SYSTEM_HOCOLDOCR_OFFSET) +#define R_SYSTEM_MOMCR2 (R_SYSTEM_BASE + R_SYSTEM_MOMCR2_OFFSET) +#define R_SYSTEM_SOSCCR (R_SYSTEM_BASE + R_SYSTEM_SOSCCR_OFFSET) +#define R_SYSTEM_SOMCR (R_SYSTEM_BASE + R_SYSTEM_SOMCR_OFFSET) +#define R_SYSTEM_VBTBER (R_SYSTEM_BASE + R_SYSTEM_VBTBER_OFFSET) +#define R_SYSTEM_VBTBPCR2 (R_SYSTEM_BASE + R_SYSTEM_VBTBPCR2_OFFSET) +#define R_SYSTEM_VBTBPSR (R_SYSTEM_BASE + R_SYSTEM_VBTBPSR_OFFSET) +#define R_SYSTEM_VBTADSR (R_SYSTEM_BASE + R_SYSTEM_VBTADSR_OFFSET) +#define R_SYSTEM_VBTADCR1 (R_SYSTEM_BASE + R_SYSTEM_VBTADCR1_OFFSET) +#define R_SYSTEM_VBTADCR2 (R_SYSTEM_BASE + R_SYSTEM_VBTADCR2_OFFSET) +#define R_SYSTEM_VBTICTLR (R_SYSTEM_BASE + R_SYSTEM_VBTICTLR_OFFSET) +#define R_SYSTEM_VBTICTLR2 (R_SYSTEM_BASE + R_SYSTEM_VBTICTLR2_OFFSET) +#define R_SYSTEM_VBTIMONR (R_SYSTEM_BASE + R_SYSTEM_VBTIMONR_OFFSET) +#define R_SYSTEM_VBTBKR(p) (R_SYSTEM_BASE + R_SYSTEM_VBTBKR_OFFSET + (p)*0x0001) + +/* Register Bitfield Definitions ********************************************/ + +/* Standby Control Register (8-bits) ****************************************/ + +#define R_SYSTEM_SBYCR_OPE (1 << 6) /* 40: Output Port Enable */ + +/* Software Standby Control Register 2 (8-bits) *****************************/ + +#define R_SYSTEM_SSCR2_SS1RSF (1 << 0) /* 01: Software Standby 1 regulator status flag */ + +/* Flash Standby Control Register (8-bits) **********************************/ + +#define R_SYSTEM_FLSCR_FLSWCF (1 << 0) /* 01: Flash Stabilization wait completion flag */ + +/* System Clock Division Control Register (32-bits) *************************/ + +#define R_SYSTEM_SCKDIVCR_PCKD_SHIFT (0) +#define R_SYSTEM_SCKDIVCR_PCKD_MASK (0xf) +# define R_SYSTEM_SCKDIVCR_PCKD_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SCKDIVCR_PCKD_DIV_2 (1 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* /2 */ +# define R_SYSTEM_SCKDIVCR_PCKD_DIV_4 (2 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* /4 */ +# define R_SYSTEM_SCKDIVCR_PCKD_DIV_8 (3 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* /8 */ +# define R_SYSTEM_SCKDIVCR_PCKD_DIV_16 (4 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* /16 */ +# define R_SYSTEM_SCKDIVCR_PCKD_DIV_32 (5 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* /32 */ +# define R_SYSTEM_SCKDIVCR_PCKD_DIV_64 (6 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* /64 */ +# define R_SYSTEM_SCKDIVCR_PCKD_DIV_3 (8 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* /3 */ +# define R_SYSTEM_SCKDIVCR_PCKD_DIV_6 (9 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* /6 */ +# define R_SYSTEM_SCKDIVCR_PCKD_DIV_12 (10 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* /12 */ +#define R_SYSTEM_SCKDIVCR_PCKC_SHIFT (4) +#define R_SYSTEM_SCKDIVCR_PCKC_MASK (0xf) +# define R_SYSTEM_SCKDIVCR_PCKC_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SCKDIVCR_PCKC_DIV_2 (1 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* /2 */ +# define R_SYSTEM_SCKDIVCR_PCKC_DIV_4 (2 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* /4 */ +# define R_SYSTEM_SCKDIVCR_PCKC_DIV_8 (3 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* /8 */ +# define R_SYSTEM_SCKDIVCR_PCKC_DIV_16 (4 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* /16 */ +# define R_SYSTEM_SCKDIVCR_PCKC_DIV_32 (5 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* /32 */ +# define R_SYSTEM_SCKDIVCR_PCKC_DIV_64 (6 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* /64 */ +# define R_SYSTEM_SCKDIVCR_PCKC_DIV_3 (8 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* /3 */ +# define R_SYSTEM_SCKDIVCR_PCKC_DIV_6 (9 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* /6 */ +# define R_SYSTEM_SCKDIVCR_PCKC_DIV_12 (10 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* /12 */ +#define R_SYSTEM_SCKDIVCR_PCKB_SHIFT (8) +#define R_SYSTEM_SCKDIVCR_PCKB_MASK (0xf) +# define R_SYSTEM_SCKDIVCR_PCKB_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SCKDIVCR_PCKB_DIV_2 (1 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* /2 */ +# define R_SYSTEM_SCKDIVCR_PCKB_DIV_4 (2 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* /4 */ +# define R_SYSTEM_SCKDIVCR_PCKB_DIV_8 (3 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* /8 */ +# define R_SYSTEM_SCKDIVCR_PCKB_DIV_16 (4 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* /16 */ +# define R_SYSTEM_SCKDIVCR_PCKB_DIV_32 (5 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* /32 */ +# define R_SYSTEM_SCKDIVCR_PCKB_DIV_64 (6 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* /64 */ +# define R_SYSTEM_SCKDIVCR_PCKB_DIV_3 (8 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* /3 */ +# define R_SYSTEM_SCKDIVCR_PCKB_DIV_6 (9 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* /6 */ +# define R_SYSTEM_SCKDIVCR_PCKB_DIV_12 (10 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* /12 */ +#define R_SYSTEM_SCKDIVCR_PCKA_SHIFT (12) +#define R_SYSTEM_SCKDIVCR_PCKA_MASK (0xf) +# define R_SYSTEM_SCKDIVCR_PCKA_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SCKDIVCR_PCKA_DIV_2 (1 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* /2 */ +# define R_SYSTEM_SCKDIVCR_PCKA_DIV_4 (2 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* /4 */ +# define R_SYSTEM_SCKDIVCR_PCKA_DIV_8 (3 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* /8 */ +# define R_SYSTEM_SCKDIVCR_PCKA_DIV_16 (4 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* /16 */ +# define R_SYSTEM_SCKDIVCR_PCKA_DIV_32 (5 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* /32 */ +# define R_SYSTEM_SCKDIVCR_PCKA_DIV_64 (6 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* /64 */ +# define R_SYSTEM_SCKDIVCR_PCKA_DIV_3 (8 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* /3 */ +# define R_SYSTEM_SCKDIVCR_PCKA_DIV_6 (9 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* /6 */ +# define R_SYSTEM_SCKDIVCR_PCKA_DIV_12 (10 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* /12 */ +#define R_SYSTEM_SCKDIVCR_BCK_SHIFT (16) +#define R_SYSTEM_SCKDIVCR_BCK_MASK (0xf) +# define R_SYSTEM_SCKDIVCR_BCK_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SCKDIVCR_BCK_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SCKDIVCR_BCK_DIV_2 (1 << R_SYSTEM_SCKDIVCR_BCK_SHIFT) /* /2 */ +# define R_SYSTEM_SCKDIVCR_BCK_DIV_4 (2 << R_SYSTEM_SCKDIVCR_BCK_SHIFT) /* /4 */ +# define R_SYSTEM_SCKDIVCR_BCK_DIV_8 (3 << R_SYSTEM_SCKDIVCR_BCK_SHIFT) /* /8 */ +# define R_SYSTEM_SCKDIVCR_BCK_DIV_16 (4 << R_SYSTEM_SCKDIVCR_BCK_SHIFT) /* /16 */ +# define R_SYSTEM_SCKDIVCR_BCK_DIV_32 (5 << R_SYSTEM_SCKDIVCR_BCK_SHIFT) /* /32 */ +# define R_SYSTEM_SCKDIVCR_BCK_DIV_64 (6 << R_SYSTEM_SCKDIVCR_BCK_SHIFT) /* /64 */ +# define R_SYSTEM_SCKDIVCR_BCK_DIV_3 (8 << R_SYSTEM_SCKDIVCR_BCK_SHIFT) /* /3 */ +# define R_SYSTEM_SCKDIVCR_BCK_DIV_6 (9 << R_SYSTEM_SCKDIVCR_BCK_SHIFT) /* /6 */ +# define R_SYSTEM_SCKDIVCR_BCK_DIV_12 (10 << R_SYSTEM_SCKDIVCR_BCK_SHIFT) /* /12 */ +#define R_SYSTEM_SCKDIVCR_PCKE_SHIFT (20) +#define R_SYSTEM_SCKDIVCR_PCKE_MASK (0xf) +# define R_SYSTEM_SCKDIVCR_PCKE_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SCKDIVCR_PCKE_DIV_2 (1 << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) /* /2 */ +# define R_SYSTEM_SCKDIVCR_PCKE_DIV_4 (2 << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) /* /4 */ +# define R_SYSTEM_SCKDIVCR_PCKE_DIV_8 (3 << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) /* /8 */ +# define R_SYSTEM_SCKDIVCR_PCKE_DIV_16 (4 << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) /* /16 */ +# define R_SYSTEM_SCKDIVCR_PCKE_DIV_32 (5 << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) /* /32 */ +# define R_SYSTEM_SCKDIVCR_PCKE_DIV_64 (6 << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) /* /64 */ +# define R_SYSTEM_SCKDIVCR_PCKE_DIV_3 (8 << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) /* /3 */ +# define R_SYSTEM_SCKDIVCR_PCKE_DIV_6 (9 << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) /* /6 */ +# define R_SYSTEM_SCKDIVCR_PCKE_DIV_12 (10 << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) /* /12 */ +#define R_SYSTEM_SCKDIVCR_ICK_SHIFT (24) +#define R_SYSTEM_SCKDIVCR_ICK_MASK (0xf) +# define R_SYSTEM_SCKDIVCR_ICK_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SCKDIVCR_ICK_DIV_2 (1 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* /2 */ +# define R_SYSTEM_SCKDIVCR_ICK_DIV_4 (2 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* /4 */ +# define R_SYSTEM_SCKDIVCR_ICK_DIV_8 (3 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* /8 */ +# define R_SYSTEM_SCKDIVCR_ICK_DIV_16 (4 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* /16 */ +# define R_SYSTEM_SCKDIVCR_ICK_DIV_32 (5 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* /32 */ +# define R_SYSTEM_SCKDIVCR_ICK_DIV_64 (6 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* /64 */ +# define R_SYSTEM_SCKDIVCR_ICK_DIV_3 (8 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* /3 */ +# define R_SYSTEM_SCKDIVCR_ICK_DIV_6 (9 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* /6 */ +# define R_SYSTEM_SCKDIVCR_ICK_DIV_12 (10 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* /12 */ +#define R_SYSTEM_SCKDIVCR_FCK_SHIFT (28) +#define R_SYSTEM_SCKDIVCR_FCK_MASK (0xf) +# define R_SYSTEM_SCKDIVCR_FCK_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SCKDIVCR_FCK_DIV_2 (1 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* /2 */ +# define R_SYSTEM_SCKDIVCR_FCK_DIV_4 (2 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* /4 */ +# define R_SYSTEM_SCKDIVCR_FCK_DIV_8 (3 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* /8 */ +# define R_SYSTEM_SCKDIVCR_FCK_DIV_16 (4 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* /16 */ +# define R_SYSTEM_SCKDIVCR_FCK_DIV_32 (5 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* /32 */ +# define R_SYSTEM_SCKDIVCR_FCK_DIV_64 (6 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* /64 */ +# define R_SYSTEM_SCKDIVCR_FCK_DIV_3 (8 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* /3 */ +# define R_SYSTEM_SCKDIVCR_FCK_DIV_6 (9 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* /6 */ +# define R_SYSTEM_SCKDIVCR_FCK_DIV_12 (10 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* /12 */ + +/* System Clock Division Control Register 2 (8-bits) ************************/ + +#define R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT (0) +#define R_SYSTEM_SCKDIVCR2_CPUCK_MASK (0xf) +# define R_SYSTEM_SCKDIVCR2_CPUCK_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SCKDIVCR2_CPUCK_DIV_2 (1 << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) /* /2 */ +# define R_SYSTEM_SCKDIVCR2_CPUCK_DIV_4 (2 << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) /* /4 */ +# define R_SYSTEM_SCKDIVCR2_CPUCK_DIV_8 (3 << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) /* /8 */ +# define R_SYSTEM_SCKDIVCR2_CPUCK_DIV_16 (4 << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) /* /16 */ +# define R_SYSTEM_SCKDIVCR2_CPUCK_DIV_32 (5 << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) /* /32 */ +# define R_SYSTEM_SCKDIVCR2_CPUCK_DIV_64 (6 << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) /* /64 */ +# define R_SYSTEM_SCKDIVCR2_CPUCK_DIV_3 (8 << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) /* /3 */ +# define R_SYSTEM_SCKDIVCR2_CPUCK_DIV_6 (9 << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) /* /6 */ +# define R_SYSTEM_SCKDIVCR2_CPUCK_DIV_12 (10 << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) /* /12 */ + +/* System Clock Source Control Register (8-bits) ****************************/ + +#define R_SYSTEM_SCKSCR_CKSEL_SHIFT (0) +#define R_SYSTEM_SCKSCR_CKSEL_MASK (0x7) +# define R_SYSTEM_SCKSCR_CKSEL_HOCO (0 << R_SYSTEM_SCKSCR_CKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_SCKSCR_CKSEL_MOCO (1 << R_SYSTEM_SCKSCR_CKSEL_SHIFT) /* MOCO */ +# define R_SYSTEM_SCKSCR_CKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_SCKSCR_CKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_SCKSCR_CKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_SCKSCR_CKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_SCKSCR_CKSEL_PLL (5 << R_SYSTEM_SCKSCR_CKSEL_SHIFT) /* PLL */ + +/* PLL Clock Control Register (16-bits) *************************************/ + +#define R_SYSTEM_PLLCCR_PLIDIV_SHIFT (0) +#define R_SYSTEM_PLLCCR_PLIDIV_MASK (0x3) +# define R_SYSTEM_PLLCCR_PLIDIV_DIV_1 (0 << R_SYSTEM_PLLCCR_PLIDIV_SHIFT) /* /1 */ +# define R_SYSTEM_PLLCCR_PLIDIV_DIV_2 (1 << R_SYSTEM_PLLCCR_PLIDIV_SHIFT) /* /2 */ +# define R_SYSTEM_PLLCCR_PLIDIV_DIV_3 (2 << R_SYSTEM_PLLCCR_PLIDIV_SHIFT) /* /3 */ +# define R_SYSTEM_PLLCCR_PLIDIV_SETTING_PROHIBITED (3 << R_SYSTEM_PLLCCR_PLIDIV_SHIFT) /* Setting prohibited */ +#define R_SYSTEM_PLLCCR_PLSRCSEL (1 << 4) /* 10: PLL1 Clock Source Select */ +#define R_SYSTEM_PLLCCR_PLLMULNF_SHIFT (6) +#define R_SYSTEM_PLLCCR_PLLMULNF_MASK (0x3) +# define R_SYSTEM_PLLCCR_PLLMULNF_V0_00_VALUE_AFTER_RESET (0 << R_SYSTEM_PLLCCR_PLLMULNF_SHIFT) /* 0.00 (Value after reset) */ +# define R_SYSTEM_PLLCCR_PLLMULNF_V0_33_1_3 (1 << R_SYSTEM_PLLCCR_PLLMULNF_SHIFT) /* 0.33 (1/3) */ +# define R_SYSTEM_PLLCCR_PLLMULNF_V0_66_2_3 (2 << R_SYSTEM_PLLCCR_PLLMULNF_SHIFT) /* 0.66 (2/3) */ +# define R_SYSTEM_PLLCCR_PLLMULNF_V0_50_1_2 (3 << R_SYSTEM_PLLCCR_PLLMULNF_SHIFT) /* 0.50 (1/2) */ +#define R_SYSTEM_PLLCCR_PLLMUL_SHIFT (8) +#define R_SYSTEM_PLLCCR_PLLMUL_MASK (0xff) +# define R_SYSTEM_PLLCCR_PLLMUL_V26_VALUE_AFTER_RESET (25 << R_SYSTEM_PLLCCR_PLLMUL_SHIFT) /* ×26 (Value after reset) */ +# define R_SYSTEM_PLLCCR_PLLMUL_V27 (26 << R_SYSTEM_PLLCCR_PLLMUL_SHIFT) /* ×27 */ +# define R_SYSTEM_PLLCCR_PLLMUL_V28 (27 << R_SYSTEM_PLLCCR_PLLMUL_SHIFT) /* ×28 */ +# define R_SYSTEM_PLLCCR_PLLMUL_V89 (88 << R_SYSTEM_PLLCCR_PLLMUL_SHIFT) /* ×89 */ +# define R_SYSTEM_PLLCCR_PLLMUL_V90 (89 << R_SYSTEM_PLLCCR_PLLMUL_SHIFT) /* ×90 */ +# define R_SYSTEM_PLLCCR_PLLMUL_V91 (90 << R_SYSTEM_PLLCCR_PLLMUL_SHIFT) /* ×91 */ +# define R_SYSTEM_PLLCCR_PLLMUL_V179 (178 << R_SYSTEM_PLLCCR_PLLMUL_SHIFT) /* ×179 */ +# define R_SYSTEM_PLLCCR_PLLMUL_V180 (179 << R_SYSTEM_PLLCCR_PLLMUL_SHIFT) /* ×180 */ + +/* PLL Control Register (8-bits) ********************************************/ + +#define R_SYSTEM_PLLCR_PLLSTP (1 << 0) /* 01: PLL1 Stop Control */ + +/* External Bus Clock Control Register (8-bits) *****************************/ + +#define R_SYSTEM_BCKCR_BCLKDIV (1 << 0) /* 01: BCLK Pin Output Select */ + +/* Main Clock Oscillator Control Register (8-bits) **************************/ + +#define R_SYSTEM_MOSCCR_MOSTP (1 << 0) /* 01: Main Clock Oscillator Stop */ + +/* High-Speed On-Chip Oscillator Control Register (8-bits) ******************/ + +#define R_SYSTEM_HOCOCR_HCSTP (1 << 0) /* 01: HOCO Stop */ + +/* Middle-Speed On-Chip Oscillator Control Register (8-bits) ****************/ + +#define R_SYSTEM_MOCOCR_MCSTP (1 << 0) /* 01: MOCO Stop */ + +/* FLL Control Register 1 (8-bits) ******************************************/ + +#define R_SYSTEM_FLLCR1_FLLEN (1 << 0) /* 01: FLL Enable */ + +/* FLL Control Register 2 (16-bits) *****************************************/ + +#define R_SYSTEM_FLLCR2_FLLCNTL_SHIFT (0) +#define R_SYSTEM_FLLCR2_FLLCNTL_MASK (0x7ff) + +/* Oscillation Stabilization Flag Register (8-bits) *************************/ + +#define R_SYSTEM_OSCSF_HOCOSF (1 << 0) /* 01: HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1. */ +#define R_SYSTEM_OSCSF_MOSCSF (1 << 3) /* 08: Main Clock Oscillation Stabilization Flag */ +#define R_SYSTEM_OSCSF_PLLSF (1 << 5) /* 20: PLL1 Clock Oscillation Stabilization Flag */ +#define R_SYSTEM_OSCSF_PLL2SF (1 << 6) /* 40: PLL2 Clock Oscillation Stabilization Flag */ + +/* Clock Out Control Register (8-bits) **************************************/ + +#define R_SYSTEM_CKOCR_CKODIV_SHIFT (4) +#define R_SYSTEM_CKOCR_CKODIV_MASK (0x7) +# define R_SYSTEM_CKOCR_CKODIV_DIV_1 (0 << R_SYSTEM_CKOCR_CKODIV_SHIFT) /* /1 */ +# define R_SYSTEM_CKOCR_CKODIV_DIV_2 (1 << R_SYSTEM_CKOCR_CKODIV_SHIFT) /* /2 */ +# define R_SYSTEM_CKOCR_CKODIV_DIV_4 (2 << R_SYSTEM_CKOCR_CKODIV_SHIFT) /* /4 */ +# define R_SYSTEM_CKOCR_CKODIV_DIV_8 (3 << R_SYSTEM_CKOCR_CKODIV_SHIFT) /* /8 */ +# define R_SYSTEM_CKOCR_CKODIV_DIV_16 (4 << R_SYSTEM_CKOCR_CKODIV_SHIFT) /* /16 */ +# define R_SYSTEM_CKOCR_CKODIV_DIV_32 (5 << R_SYSTEM_CKOCR_CKODIV_SHIFT) /* /32 */ +# define R_SYSTEM_CKOCR_CKODIV_DIV_64 (6 << R_SYSTEM_CKOCR_CKODIV_SHIFT) /* /64 */ +# define R_SYSTEM_CKOCR_CKODIV_DIV_128 (7 << R_SYSTEM_CKOCR_CKODIV_SHIFT) /* /128 */ +#define R_SYSTEM_CKOCR_CKOEN (1 << 7) /* 80: Clock out enable */ + +/* Trace Clock Control Register (8-bits) ************************************/ + +#define R_SYSTEM_TRCKCR_TRCK_SHIFT (0) +#define R_SYSTEM_TRCKCR_TRCK_MASK (0xf) +#define R_SYSTEM_TRCKCR_TRCKSEL (1 << 4) /* 10: Trace Clock source select */ +#define R_SYSTEM_TRCKCR_TRCKEN (1 << 7) /* 80: Trace Clock operating Enable */ + +/* Oscillation Stop Detection Control Register (8-bits) *********************/ + +#define R_SYSTEM_OSTDCR_OSTDIE (1 << 0) /* 01: Oscillation Stop Detection Interrupt Enable */ +#define R_SYSTEM_OSTDCR_OSTDE (1 << 7) /* 80: Oscillation Stop Detection Function Enable */ + +/* Oscillation Stop Detection Status Register (8-bits) **********************/ + +#define R_SYSTEM_OSTDSR_OSTDF (1 << 0) /* 01: Oscillation Stop Detection Flag */ + +/* Oscillator Monitor Register (8-bits) *************************************/ + +#define R_SYSTEM_OSCMONR_MOCOMON (1 << 1) /* 02: MOCO operation monitor */ +#define R_SYSTEM_OSCMONR_LOCOMON (1 << 2) /* 04: LOCO operation monitor */ + +/* PLL2 Clock Control Register (16-bits) ************************************/ + +#define R_SYSTEM_PLL2CCR_PL2IDIV_SHIFT (0) +#define R_SYSTEM_PLL2CCR_PL2IDIV_MASK (0x3) +# define R_SYSTEM_PLL2CCR_PL2IDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_PLL2CCR_PL2IDIV_SHIFT) /* /1 (Value after reset) */ +# define R_SYSTEM_PLL2CCR_PL2IDIV_DIV_2 (1 << R_SYSTEM_PLL2CCR_PL2IDIV_SHIFT) /* /2 */ +# define R_SYSTEM_PLL2CCR_PL2IDIV_DIV_3 (2 << R_SYSTEM_PLL2CCR_PL2IDIV_SHIFT) /* /3 */ +# define R_SYSTEM_PLL2CCR_PL2IDIV_DIV_4 (3 << R_SYSTEM_PLL2CCR_PL2IDIV_SHIFT) /* /4 */ +#define R_SYSTEM_PLL2CCR_PL2SRCSEL (1 << 4) /* 10: PLL Clock Source Select */ +#define R_SYSTEM_PLL2CCR_PLL2MULNF_SHIFT (6) +#define R_SYSTEM_PLL2CCR_PLL2MULNF_MASK (0x3) +# define R_SYSTEM_PLL2CCR_PLL2MULNF_V0_00_VALUE_AFTER_RESET (0 << R_SYSTEM_PLL2CCR_PLL2MULNF_SHIFT) /* 0.00 (Value after reset) */ +# define R_SYSTEM_PLL2CCR_PLL2MULNF_V0_33_1_3 (1 << R_SYSTEM_PLL2CCR_PLL2MULNF_SHIFT) /* 0.33 (1/3) */ +# define R_SYSTEM_PLL2CCR_PLL2MULNF_V0_66_2_3 (2 << R_SYSTEM_PLL2CCR_PLL2MULNF_SHIFT) /* 0.66 (2/3) */ +# define R_SYSTEM_PLL2CCR_PLL2MULNF_V0_50_1_2 (3 << R_SYSTEM_PLL2CCR_PLL2MULNF_SHIFT) /* 0.50 (1/2) */ +#define R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT (8) +#define R_SYSTEM_PLL2CCR_PLL2MUL_MASK (0xff) +# define R_SYSTEM_PLL2CCR_PLL2MUL_V26_VALUE_AFTER_RESET (25 << R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT) /* ×26 (Value after reset) */ +# define R_SYSTEM_PLL2CCR_PLL2MUL_V27 (26 << R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT) /* ×27 */ +# define R_SYSTEM_PLL2CCR_PLL2MUL_V28 (27 << R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT) /* ×28 */ +# define R_SYSTEM_PLL2CCR_PLL2MUL_V89 (88 << R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT) /* ×89 */ +# define R_SYSTEM_PLL2CCR_PLL2MUL_V90 (89 << R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT) /* ×90 */ +# define R_SYSTEM_PLL2CCR_PLL2MUL_V91 (90 << R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT) /* ×91 */ +# define R_SYSTEM_PLL2CCR_PLL2MUL_V179 (178 << R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT) /* ×179 */ +# define R_SYSTEM_PLL2CCR_PLL2MUL_V180 (179 << R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT) /* ×180 */ + +/* PLL2 Control Register (8-bits) *******************************************/ + +#define R_SYSTEM_PLL2CR_PLL2STP (1 << 0) /* 01: PLL2 Stop Control */ + +/* PLL Clock Control Register 2 (16-bits) ***********************************/ + +#define R_SYSTEM_PLLCCR2_PLODIVP_SHIFT (0) +#define R_SYSTEM_PLLCCR2_PLODIVP_MASK (0xf) +# define R_SYSTEM_PLLCCR2_PLODIVP_V1 (0 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* ×1 */ +# define R_SYSTEM_PLLCCR2_PLODIVP_V1_2 (1 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* ×1 / 2 */ +# define R_SYSTEM_PLLCCR2_PLODIVP_PROHIBITED_2 (2 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVP_V1_4 (3 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* ×1 / 4 */ +# define R_SYSTEM_PLLCCR2_PLODIVP_PROHIBITED_4 (4 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVP_V0101 (5 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* ×1 / 6 (Value after reset) */ +# define R_SYSTEM_PLLCCR2_PLODIVP_PROHIBITED_6 (6 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVP_V1_8 (7 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* ×1 / 8 */ +# define R_SYSTEM_PLLCCR2_PLODIVP_PROHIBITED_8 (8 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVP_PROHIBITED_9 (9 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVP_PROHIBITED_10 (10 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVP_PROHIBITED_11 (11 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVP_PROHIBITED_12 (12 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVP_PROHIBITED_13 (13 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVP_PROHIBITED_14 (14 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVP_V1_16 (15 << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) /* ×1 / 16 */ +#define R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT (4) +#define R_SYSTEM_PLLCCR2_PLODIVQ_MASK (0xf) +# define R_SYSTEM_PLLCCR2_PLODIVQ_PROHIBITED_0 (0 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_V1_2 (1 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* ×1 / 2 */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_V1_3 (2 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* ×1 / 3 */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_V1_4 (3 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* ×1 / 4 */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_V1_5 (4 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* ×1 / 5 */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_V0101 (5 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* ×1 / 6 (Value after reset) */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_PROHIBITED_6 (6 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_V1_8 (7 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* ×1 / 8 */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_V1_9 (8 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* ×1 / 9 */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_PROHIBITED_9 (9 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_PROHIBITED_10 (10 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_PROHIBITED_11 (11 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_PROHIBITED_12 (12 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_PROHIBITED_13 (13 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_PROHIBITED_14 (14 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVQ_PROHIBITED_15 (15 << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) /* prohibited */ +#define R_SYSTEM_PLLCCR2_PLODIVR_SHIFT (8) +#define R_SYSTEM_PLLCCR2_PLODIVR_MASK (0xf) +# define R_SYSTEM_PLLCCR2_PLODIVR_PROHIBITED_0 (0 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVR_V1_2 (1 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* ×1 / 2 */ +# define R_SYSTEM_PLLCCR2_PLODIVR_V1_3 (2 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* ×1 / 3 */ +# define R_SYSTEM_PLLCCR2_PLODIVR_V1_4 (3 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* ×1 / 4 */ +# define R_SYSTEM_PLLCCR2_PLODIVR_V1_5 (4 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* ×1 / 5 */ +# define R_SYSTEM_PLLCCR2_PLODIVR_V0101 (5 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* ×1 / 6 (Value after reset) */ +# define R_SYSTEM_PLLCCR2_PLODIVR_PROHIBITED_6 (6 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVR_V1_8 (7 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* ×1 / 8 */ +# define R_SYSTEM_PLLCCR2_PLODIVR_V1_9 (8 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* ×1 / 9 */ +# define R_SYSTEM_PLLCCR2_PLODIVR_PROHIBITED_9 (9 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVR_PROHIBITED_10 (10 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVR_PROHIBITED_11 (11 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVR_PROHIBITED_12 (12 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVR_PROHIBITED_13 (13 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVR_PROHIBITED_14 (14 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLLCCR2_PLODIVR_PROHIBITED_15 (15 << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT) /* prohibited */ + +/* PLL2 Clock Control Register 2 (16-bits) **********************************/ + +#define R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT (0) +#define R_SYSTEM_PLL2CCR2_PL2ODIVP_MASK (0xf) +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_V1 (0 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* ×1 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_V1_2 (1 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* ×1 / 2 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_PROHIBITED_2 (2 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_V1_4 (3 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* ×1 / 4 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_PROHIBITED_4 (4 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_V0101 (5 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* ×1 / 6 (Value after reset) */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_PROHIBITED_6 (6 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_V1_8 (7 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* ×1 / 8 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_PROHIBITED_8 (8 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_PROHIBITED_9 (9 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_PROHIBITED_10 (10 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_PROHIBITED_11 (11 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_PROHIBITED_12 (12 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_PROHIBITED_13 (13 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_PROHIBITED_14 (14 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVP_V1_16 (15 << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) /* ×1 / 16 */ +#define R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT (4) +#define R_SYSTEM_PLL2CCR2_PL2ODIVQ_MASK (0xf) +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_PROHIBITED_0 (0 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_V1_2 (1 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* ×1 / 2 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_V1_3 (2 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* ×1 / 3 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_V1_4 (3 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* ×1 / 4 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_V1_5 (4 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* ×1 / 5 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_V0101 (5 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* ×1 / 6 (Value after reset) */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_PROHIBITED_6 (6 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_V1_8 (7 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* ×1 / 8 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_V1_9 (8 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* ×1 / 9 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_PROHIBITED_9 (9 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_PROHIBITED_10 (10 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_PROHIBITED_11 (11 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_PROHIBITED_12 (12 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_PROHIBITED_13 (13 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_PROHIBITED_14 (14 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVQ_PROHIBITED_15 (15 << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) /* prohibited */ +#define R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT (8) +#define R_SYSTEM_PLL2CCR2_PL2ODIVR_MASK (0xf) +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_PROHIBITED_0 (0 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_V1_2 (1 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* ×1 / 2 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_V1_3 (2 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* ×1 / 3 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_V1_4 (3 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* ×1 / 4 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_V1_5 (4 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* ×1 / 5 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_V0101 (5 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* ×1 / 6 (Value after reset) */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_PROHIBITED_6 (6 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_V1_8 (7 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* ×1 / 8 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_V1_9 (8 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* ×1 / 9 */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_PROHIBITED_9 (9 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_PROHIBITED_10 (10 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_PROHIBITED_11 (11 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_PROHIBITED_12 (12 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_PROHIBITED_13 (13 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_PROHIBITED_14 (14 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* prohibited */ +# define R_SYSTEM_PLL2CCR2_PL2ODIVR_PROHIBITED_15 (15 << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT) /* prohibited */ + +/* External Bus Clock Output Control Register (8-bits) **********************/ + +#define R_SYSTEM_EBCKOCR_EBCKOEN (1 << 0) /* 01: BCLK Pin Output Control */ + +/* SDRAM Clock Output Control Register (8-bits) *****************************/ + +#define R_SYSTEM_SDCKOCR_SDCKOEN (1 << 0) /* 01: SDCLK Pin Output Control */ + +/* SCI clock Division control register (8-bits) *****************************/ + +#define R_SYSTEM_SCICKDIVCR_CKDIV_SHIFT (0) +#define R_SYSTEM_SCICKDIVCR_CKDIV_MASK (0x7) +# define R_SYSTEM_SCICKDIVCR_CKDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SCICKDIVCR_CKDIV_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SCICKDIVCR_CKDIV_DIV_2 (1 << R_SYSTEM_SCICKDIVCR_CKDIV_SHIFT) /* /2 */ +# define R_SYSTEM_SCICKDIVCR_CKDIV_DIV_4 (2 << R_SYSTEM_SCICKDIVCR_CKDIV_SHIFT) /* /4 */ +# define R_SYSTEM_SCICKDIVCR_CKDIV_DIV_6 (3 << R_SYSTEM_SCICKDIVCR_CKDIV_SHIFT) /* /6 */ +# define R_SYSTEM_SCICKDIVCR_CKDIV_DIV_8 (4 << R_SYSTEM_SCICKDIVCR_CKDIV_SHIFT) /* /8 */ +# define R_SYSTEM_SCICKDIVCR_CKDIV_DIV_3 (5 << R_SYSTEM_SCICKDIVCR_CKDIV_SHIFT) /* /3 */ +# define R_SYSTEM_SCICKDIVCR_CKDIV_DIV_5 (6 << R_SYSTEM_SCICKDIVCR_CKDIV_SHIFT) /* /5 */ + +/* SCI clock control register (8-bits) **************************************/ + +#define R_SYSTEM_SCICKCR_CKSEL_SHIFT (0) +#define R_SYSTEM_SCICKCR_CKSEL_MASK (0xf) +# define R_SYSTEM_SCICKCR_CKSEL_HOCO (0 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_SCICKCR_CKSEL_MOCO_VALUE_AFTER_RESET (1 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* MOCO (value after reset) */ +# define R_SYSTEM_SCICKCR_CKSEL_LOCO (2 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* LOCO */ +# define R_SYSTEM_SCICKCR_CKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_SCICKCR_CKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_SCICKCR_CKSEL_PLL1P (5 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* PLL1P */ +# define R_SYSTEM_SCICKCR_CKSEL_PLL2P (6 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* PLL2P */ +# define R_SYSTEM_SCICKCR_CKSEL_PLL1Q (7 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* PLL1Q */ +# define R_SYSTEM_SCICKCR_CKSEL_PLL1R (8 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* PLL1R */ +# define R_SYSTEM_SCICKCR_CKSEL_PLL2Q (9 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* PLL2Q */ +# define R_SYSTEM_SCICKCR_CKSEL_PLL2R (10 << R_SYSTEM_SCICKCR_CKSEL_SHIFT) /* PLL2R */ +#define R_SYSTEM_SCICKCR_CKSREQ (1 << 6) /* 40: Clock Switching Request */ +#define R_SYSTEM_SCICKCR_CKSRDY (1 << 7) /* 80: Clock Switching Ready state flag */ + +/* SPI clock Division control register (8-bits) *****************************/ + +#define R_SYSTEM_SPICKDIVCR_CKDIV_SHIFT (0) +#define R_SYSTEM_SPICKDIVCR_CKDIV_MASK (0x7) +# define R_SYSTEM_SPICKDIVCR_CKDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_SPICKDIVCR_CKDIV_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_SPICKDIVCR_CKDIV_DIV_2 (1 << R_SYSTEM_SPICKDIVCR_CKDIV_SHIFT) /* /2 */ +# define R_SYSTEM_SPICKDIVCR_CKDIV_DIV_4 (2 << R_SYSTEM_SPICKDIVCR_CKDIV_SHIFT) /* /4 */ +# define R_SYSTEM_SPICKDIVCR_CKDIV_DIV_6 (3 << R_SYSTEM_SPICKDIVCR_CKDIV_SHIFT) /* /6 */ +# define R_SYSTEM_SPICKDIVCR_CKDIV_DIV_8 (4 << R_SYSTEM_SPICKDIVCR_CKDIV_SHIFT) /* /8 */ +# define R_SYSTEM_SPICKDIVCR_CKDIV_DIV_3 (5 << R_SYSTEM_SPICKDIVCR_CKDIV_SHIFT) /* /3 */ +# define R_SYSTEM_SPICKDIVCR_CKDIV_DIV_5 (6 << R_SYSTEM_SPICKDIVCR_CKDIV_SHIFT) /* /5 */ + +/* SPI clock control register (8-bits) **************************************/ + +#define R_SYSTEM_SPICKCR_CKSEL_SHIFT (0) +#define R_SYSTEM_SPICKCR_CKSEL_MASK (0xf) +# define R_SYSTEM_SPICKCR_CKSEL_HOCO (0 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_SPICKCR_CKSEL_MOCO_VALUE_AFTER_RESET (1 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* MOCO (value after reset) */ +# define R_SYSTEM_SPICKCR_CKSEL_LOCO (2 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* LOCO */ +# define R_SYSTEM_SPICKCR_CKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_SPICKCR_CKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_SPICKCR_CKSEL_PLL1P (5 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* PLL1P */ +# define R_SYSTEM_SPICKCR_CKSEL_PLL2P (6 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* PLL2P */ +# define R_SYSTEM_SPICKCR_CKSEL_PLL1Q (7 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* PLL1Q */ +# define R_SYSTEM_SPICKCR_CKSEL_PLL1R (8 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* PLL1R */ +# define R_SYSTEM_SPICKCR_CKSEL_PLL2Q (9 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* PLL2Q */ +# define R_SYSTEM_SPICKCR_CKSEL_PLL2R (10 << R_SYSTEM_SPICKCR_CKSEL_SHIFT) /* PLL2R */ +#define R_SYSTEM_SPICKCR_CKSREQ (1 << 6) /* 40: Clock Switching Request */ +#define R_SYSTEM_SPICKCR_CKSRDY (1 << 7) /* 80: Clock Switching Ready state flag */ + +/* ADC clock Division control register (8-bits) *****************************/ + +#define R_SYSTEM_ADCCKDIVCR_CKDIV_SHIFT (0) +#define R_SYSTEM_ADCCKDIVCR_CKDIV_MASK (0x7) +# define R_SYSTEM_ADCCKDIVCR_CKDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_ADCCKDIVCR_CKDIV_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_ADCCKDIVCR_CKDIV_DIV_2 (1 << R_SYSTEM_ADCCKDIVCR_CKDIV_SHIFT) /* /2 */ +# define R_SYSTEM_ADCCKDIVCR_CKDIV_DIV_4 (2 << R_SYSTEM_ADCCKDIVCR_CKDIV_SHIFT) /* /4 */ +# define R_SYSTEM_ADCCKDIVCR_CKDIV_DIV_6 (3 << R_SYSTEM_ADCCKDIVCR_CKDIV_SHIFT) /* /6 */ +# define R_SYSTEM_ADCCKDIVCR_CKDIV_DIV_8 (4 << R_SYSTEM_ADCCKDIVCR_CKDIV_SHIFT) /* /8 */ +# define R_SYSTEM_ADCCKDIVCR_CKDIV_DIV_3 (5 << R_SYSTEM_ADCCKDIVCR_CKDIV_SHIFT) /* /3 */ +# define R_SYSTEM_ADCCKDIVCR_CKDIV_DIV_5 (6 << R_SYSTEM_ADCCKDIVCR_CKDIV_SHIFT) /* /5 */ + +/* ADC clock control register (8-bits) **************************************/ + +#define R_SYSTEM_ADCCKCR_CKSEL_SHIFT (0) +#define R_SYSTEM_ADCCKCR_CKSEL_MASK (0xf) +# define R_SYSTEM_ADCCKCR_CKSEL_HOCO (0 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_ADCCKCR_CKSEL_MOCO_VALUE_AFTER_RESET (1 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* MOCO (value after reset) */ +# define R_SYSTEM_ADCCKCR_CKSEL_LOCO (2 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* LOCO */ +# define R_SYSTEM_ADCCKCR_CKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_ADCCKCR_CKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_ADCCKCR_CKSEL_PLL1P (5 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* PLL1P */ +# define R_SYSTEM_ADCCKCR_CKSEL_PLL2P (6 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* PLL2P */ +# define R_SYSTEM_ADCCKCR_CKSEL_PLL1Q (7 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* PLL1Q */ +# define R_SYSTEM_ADCCKCR_CKSEL_PLL1R (8 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* PLL1R */ +# define R_SYSTEM_ADCCKCR_CKSEL_PLL2Q (9 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* PLL2Q */ +# define R_SYSTEM_ADCCKCR_CKSEL_PLL2R (10 << R_SYSTEM_ADCCKCR_CKSEL_SHIFT) /* PLL2R */ +#define R_SYSTEM_ADCCKCR_CKSREQ (1 << 6) /* 40: Clock Switching Request */ +#define R_SYSTEM_ADCCKCR_CKSRDY (1 << 7) /* 80: Clock Switching Ready state flag */ + +/* GPT clock Division control register (8-bits) *****************************/ + +#define R_SYSTEM_GPTCKDIVCR_CKDIV_SHIFT (0) +#define R_SYSTEM_GPTCKDIVCR_CKDIV_MASK (0x7) +# define R_SYSTEM_GPTCKDIVCR_CKDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_GPTCKDIVCR_CKDIV_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_GPTCKDIVCR_CKDIV_DIV_2 (1 << R_SYSTEM_GPTCKDIVCR_CKDIV_SHIFT) /* /2 */ +# define R_SYSTEM_GPTCKDIVCR_CKDIV_DIV_4 (2 << R_SYSTEM_GPTCKDIVCR_CKDIV_SHIFT) /* /4 */ +# define R_SYSTEM_GPTCKDIVCR_CKDIV_DIV_6 (3 << R_SYSTEM_GPTCKDIVCR_CKDIV_SHIFT) /* /6 */ +# define R_SYSTEM_GPTCKDIVCR_CKDIV_DIV_8 (4 << R_SYSTEM_GPTCKDIVCR_CKDIV_SHIFT) /* /8 */ +# define R_SYSTEM_GPTCKDIVCR_CKDIV_DIV_3 (5 << R_SYSTEM_GPTCKDIVCR_CKDIV_SHIFT) /* /3 */ +# define R_SYSTEM_GPTCKDIVCR_CKDIV_DIV_5 (6 << R_SYSTEM_GPTCKDIVCR_CKDIV_SHIFT) /* /5 */ + +/* GPT clock control register (8-bits) **************************************/ + +#define R_SYSTEM_GPTCKCR_CKSEL_SHIFT (0) +#define R_SYSTEM_GPTCKCR_CKSEL_MASK (0xf) +# define R_SYSTEM_GPTCKCR_CKSEL_HOCO (0 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_GPTCKCR_CKSEL_MOCO_VALUE_AFTER_RESET (1 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* MOCO (value after reset) */ +# define R_SYSTEM_GPTCKCR_CKSEL_LOCO (2 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* LOCO */ +# define R_SYSTEM_GPTCKCR_CKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_GPTCKCR_CKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_GPTCKCR_CKSEL_PLL1P (5 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* PLL1P */ +# define R_SYSTEM_GPTCKCR_CKSEL_PLL2P (6 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* PLL2P */ +# define R_SYSTEM_GPTCKCR_CKSEL_PLL1Q (7 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* PLL1Q */ +# define R_SYSTEM_GPTCKCR_CKSEL_PLL1R (8 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* PLL1R */ +# define R_SYSTEM_GPTCKCR_CKSEL_PLL2Q (9 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* PLL2Q */ +# define R_SYSTEM_GPTCKCR_CKSEL_PLL2R (10 << R_SYSTEM_GPTCKCR_CKSEL_SHIFT) /* PLL2R */ +#define R_SYSTEM_GPTCKCR_CKSREQ (1 << 6) /* 40: Clock Switching Request */ +#define R_SYSTEM_GPTCKCR_CKSRDY (1 << 7) /* 80: Clock Switching Ready state flag */ + +/* LCD clock Division control register (8-bits) *****************************/ + +#define R_SYSTEM_LCDCKDIVCR_CKDIV_SHIFT (0) +#define R_SYSTEM_LCDCKDIVCR_CKDIV_MASK (0x7) +# define R_SYSTEM_LCDCKDIVCR_CKDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_LCDCKDIVCR_CKDIV_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_LCDCKDIVCR_CKDIV_DIV_2 (1 << R_SYSTEM_LCDCKDIVCR_CKDIV_SHIFT) /* /2 */ +# define R_SYSTEM_LCDCKDIVCR_CKDIV_DIV_4 (2 << R_SYSTEM_LCDCKDIVCR_CKDIV_SHIFT) /* /4 */ +# define R_SYSTEM_LCDCKDIVCR_CKDIV_DIV_6 (3 << R_SYSTEM_LCDCKDIVCR_CKDIV_SHIFT) /* /6 */ +# define R_SYSTEM_LCDCKDIVCR_CKDIV_DIV_8 (4 << R_SYSTEM_LCDCKDIVCR_CKDIV_SHIFT) /* /8 */ +# define R_SYSTEM_LCDCKDIVCR_CKDIV_DIV_3 (5 << R_SYSTEM_LCDCKDIVCR_CKDIV_SHIFT) /* /3 */ +# define R_SYSTEM_LCDCKDIVCR_CKDIV_DIV_5 (6 << R_SYSTEM_LCDCKDIVCR_CKDIV_SHIFT) /* /5 */ + +/* LCD clock control register (8-bits) **************************************/ + +#define R_SYSTEM_LCDCKCR_CKSEL_SHIFT (0) +#define R_SYSTEM_LCDCKCR_CKSEL_MASK (0xf) +# define R_SYSTEM_LCDCKCR_CKSEL_HOCO (0 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_LCDCKCR_CKSEL_MOCO_VALUE_AFTER_RESET (1 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* MOCO (value after reset) */ +# define R_SYSTEM_LCDCKCR_CKSEL_LOCO (2 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* LOCO */ +# define R_SYSTEM_LCDCKCR_CKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_LCDCKCR_CKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_LCDCKCR_CKSEL_PLL1P (5 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* PLL1P */ +# define R_SYSTEM_LCDCKCR_CKSEL_PLL2P (6 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* PLL2P */ +# define R_SYSTEM_LCDCKCR_CKSEL_PLL1Q (7 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* PLL1Q */ +# define R_SYSTEM_LCDCKCR_CKSEL_PLL1R (8 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* PLL1R */ +# define R_SYSTEM_LCDCKCR_CKSEL_PLL2Q (9 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* PLL2Q */ +# define R_SYSTEM_LCDCKCR_CKSEL_PLL2R (10 << R_SYSTEM_LCDCKCR_CKSEL_SHIFT) /* PLL2R */ +#define R_SYSTEM_LCDCKCR_CKSREQ (1 << 6) /* 40: Clock Switching Request */ +#define R_SYSTEM_LCDCKCR_CKSRDY (1 << 7) /* 80: Clock Switching Ready state flag */ + +/* MOCO User Trimming Control Register (8-bits) *****************************/ + +#define R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT (0) +#define R_SYSTEM_MOCOUTCR_MOCOUTRM_MASK (0xff) +# define R_SYSTEM_MOCOUTCR_MOCOUTRM_M128 (128 << R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT) /* -128 */ +# define R_SYSTEM_MOCOUTCR_MOCOUTRM_M127 (129 << R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT) /* -127 */ +# define R_SYSTEM_MOCOUTCR_MOCOUTRM_M126 (130 << R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT) /* -126 */ +# define R_SYSTEM_MOCOUTCR_MOCOUTRM_M1 (255 << R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT) /* -1 */ +# define R_SYSTEM_MOCOUTCR_MOCOUTRM_CENTER_CODE (0 << R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT) /* Center Code */ +# define R_SYSTEM_MOCOUTCR_MOCOUTRM_P1 (1 << R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT) /* +1 */ +# define R_SYSTEM_MOCOUTCR_MOCOUTRM_P125 (125 << R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT) /* +125 */ +# define R_SYSTEM_MOCOUTCR_MOCOUTRM_P126 (126 << R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT) /* +126 */ +# define R_SYSTEM_MOCOUTCR_MOCOUTRM_P127 (127 << R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT) /* +127 */ + +/* HOCO User Trimming Control Register (8-bits) *****************************/ + +#define R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT (0) +#define R_SYSTEM_HOCOUTCR_HOCOUTRM_MASK (0xff) +# define R_SYSTEM_HOCOUTCR_HOCOUTRM_M128 (128 << R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT) /* -128 */ +# define R_SYSTEM_HOCOUTCR_HOCOUTRM_M127 (129 << R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT) /* -127 */ +# define R_SYSTEM_HOCOUTCR_HOCOUTRM_M126 (130 << R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT) /* -126 */ +# define R_SYSTEM_HOCOUTCR_HOCOUTRM_M1 (255 << R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT) /* -1 */ +# define R_SYSTEM_HOCOUTCR_HOCOUTRM_CENTER_CODE (0 << R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT) /* Center Code */ +# define R_SYSTEM_HOCOUTCR_HOCOUTRM_P1 (1 << R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT) /* +1 */ +# define R_SYSTEM_HOCOUTCR_HOCOUTRM_P125 (125 << R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT) /* +125 */ +# define R_SYSTEM_HOCOUTCR_HOCOUTRM_P126 (126 << R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT) /* +126 */ +# define R_SYSTEM_HOCOUTCR_HOCOUTRM_P127 (127 << R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT) /* +127 */ + +/* USB clock Division control register (8-bits) *****************************/ + +#define R_SYSTEM_USBCKDIVCR_USBCKDIV_SHIFT (0) +#define R_SYSTEM_USBCKDIVCR_USBCKDIV_MASK (0x7) +# define R_SYSTEM_USBCKDIVCR_USBCKDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_USBCKDIVCR_USBCKDIV_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_USBCKDIVCR_USBCKDIV_DIV_2 (1 << R_SYSTEM_USBCKDIVCR_USBCKDIV_SHIFT) /* /2 */ +# define R_SYSTEM_USBCKDIVCR_USBCKDIV_DIV_4 (2 << R_SYSTEM_USBCKDIVCR_USBCKDIV_SHIFT) /* /4 */ +# define R_SYSTEM_USBCKDIVCR_USBCKDIV_DIV_6 (3 << R_SYSTEM_USBCKDIVCR_USBCKDIV_SHIFT) /* /6 */ +# define R_SYSTEM_USBCKDIVCR_USBCKDIV_DIV_8 (4 << R_SYSTEM_USBCKDIVCR_USBCKDIV_SHIFT) /* /8 */ +# define R_SYSTEM_USBCKDIVCR_USBCKDIV_DIV_3 (5 << R_SYSTEM_USBCKDIVCR_USBCKDIV_SHIFT) /* /3 */ +# define R_SYSTEM_USBCKDIVCR_USBCKDIV_DIV_5 (6 << R_SYSTEM_USBCKDIVCR_USBCKDIV_SHIFT) /* /5 */ + +/* Octal-SPI clock Division control register (8-bits) ***********************/ + +#define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_SHIFT (0) +#define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_MASK (0x7) +# define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_OCTACKDIVCR_OCTACKDIV_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_DIV_2 (1 << R_SYSTEM_OCTACKDIVCR_OCTACKDIV_SHIFT) /* /2 */ +# define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_DIV_4 (2 << R_SYSTEM_OCTACKDIVCR_OCTACKDIV_SHIFT) /* /4 */ +# define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_DIV_6 (3 << R_SYSTEM_OCTACKDIVCR_OCTACKDIV_SHIFT) /* /6 */ +# define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_DIV_8 (4 << R_SYSTEM_OCTACKDIVCR_OCTACKDIV_SHIFT) /* /8 */ +# define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_DIV_3 (5 << R_SYSTEM_OCTACKDIVCR_OCTACKDIV_SHIFT) /* /3 */ +# define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_DIV_5 (6 << R_SYSTEM_OCTACKDIVCR_OCTACKDIV_SHIFT) /* /5 */ + +/* CANFD Core clock Division control register (8-bits) **********************/ + +#define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_SHIFT (0) +#define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_MASK (0x7) +# define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_DIV_2 (1 << R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_SHIFT) /* /2 */ +# define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_DIV_4 (2 << R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_SHIFT) /* /4 */ +# define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_DIV_6 (3 << R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_SHIFT) /* /6 */ +# define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_DIV_8 (4 << R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_SHIFT) /* /8 */ +# define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_DIV_3 (5 << R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_SHIFT) /* /3 */ +# define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_DIV_5 (6 << R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_SHIFT) /* /5 */ + +/* USB60 clock Division control register (8-bits) ***************************/ + +#define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_SHIFT (0) +#define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_MASK (0x7) +# define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_USB60CKDIVCR_USB60CKDIV_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_DIV_2 (1 << R_SYSTEM_USB60CKDIVCR_USB60CKDIV_SHIFT) /* /2 */ +# define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_DIV_4 (2 << R_SYSTEM_USB60CKDIVCR_USB60CKDIV_SHIFT) /* /4 */ +# define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_DIV_6 (3 << R_SYSTEM_USB60CKDIVCR_USB60CKDIV_SHIFT) /* /6 */ +# define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_DIV_8 (4 << R_SYSTEM_USB60CKDIVCR_USB60CKDIV_SHIFT) /* /8 */ +# define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_DIV_3 (5 << R_SYSTEM_USB60CKDIVCR_USB60CKDIV_SHIFT) /* /3 */ +# define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_DIV_5 (6 << R_SYSTEM_USB60CKDIVCR_USB60CKDIV_SHIFT) /* /5 */ + +/* I3C clock Division control register (8-bits) *****************************/ + +#define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_SHIFT (0) +#define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_MASK (0x7) +# define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_V1_VALUE_AFTER_RESET (0 << R_SYSTEM_I3CCKDIVCR_I3CCKDIV_SHIFT) /* /1 (value after reset) */ +# define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_DIV_2 (1 << R_SYSTEM_I3CCKDIVCR_I3CCKDIV_SHIFT) /* /2 */ +# define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_DIV_4 (2 << R_SYSTEM_I3CCKDIVCR_I3CCKDIV_SHIFT) /* /4 */ +# define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_DIV_6 (3 << R_SYSTEM_I3CCKDIVCR_I3CCKDIV_SHIFT) /* /6 */ +# define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_DIV_8 (4 << R_SYSTEM_I3CCKDIVCR_I3CCKDIV_SHIFT) /* /8 */ +# define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_DIV_3 (5 << R_SYSTEM_I3CCKDIVCR_I3CCKDIV_SHIFT) /* /3 */ +# define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_DIV_5 (6 << R_SYSTEM_I3CCKDIVCR_I3CCKDIV_SHIFT) /* /5 */ + +/* USB clock control register (8-bits) **************************************/ + +#define R_SYSTEM_USBCKCR_USBCKSEL_SHIFT (0) +#define R_SYSTEM_USBCKCR_USBCKSEL_MASK (0xf) +# define R_SYSTEM_USBCKCR_USBCKSEL_HOCO (0 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_USBCKCR_USBCKSEL_MOCO_VALUE_AFTER_RESET (1 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* MOCO (value after reset) */ +# define R_SYSTEM_USBCKCR_USBCKSEL_LOCO (2 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* LOCO */ +# define R_SYSTEM_USBCKCR_USBCKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_USBCKCR_USBCKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_USBCKCR_USBCKSEL_PLL1P (5 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* PLL1P */ +# define R_SYSTEM_USBCKCR_USBCKSEL_PLL2P (6 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* PLL2P */ +# define R_SYSTEM_USBCKCR_USBCKSEL_PLL1Q (7 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* PLL1Q */ +# define R_SYSTEM_USBCKCR_USBCKSEL_PLL1R (8 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* PLL1R */ +# define R_SYSTEM_USBCKCR_USBCKSEL_PLL2Q (9 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* PLL2Q */ +# define R_SYSTEM_USBCKCR_USBCKSEL_PLL2R (10 << R_SYSTEM_USBCKCR_USBCKSEL_SHIFT) /* PLL2R */ +#define R_SYSTEM_USBCKCR_USBCKSREQ (1 << 6) /* 40: USB clock (USBCLK) Switching Request */ +#define R_SYSTEM_USBCKCR_USBCKSRDY (1 << 7) /* 80: USB clock (USBCLK) Switching Ready state flag */ + +/* Octal-SPI clock control register (8-bits) ********************************/ + +#define R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT (0) +#define R_SYSTEM_OCTACKCR_OCTACKSEL_MASK (0xf) +# define R_SYSTEM_OCTACKCR_OCTACKSEL_HOCO (0 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_OCTACKCR_OCTACKSEL_MOCO_VALUE_AFTER_RESET (1 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* MOCO (value after reset) */ +# define R_SYSTEM_OCTACKCR_OCTACKSEL_LOCO (2 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* LOCO */ +# define R_SYSTEM_OCTACKCR_OCTACKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_OCTACKCR_OCTACKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_OCTACKCR_OCTACKSEL_PLL1P (5 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* PLL1P */ +# define R_SYSTEM_OCTACKCR_OCTACKSEL_PLL2P (6 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* PLL2P */ +# define R_SYSTEM_OCTACKCR_OCTACKSEL_PLL1Q (7 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* PLL1Q */ +# define R_SYSTEM_OCTACKCR_OCTACKSEL_PLL1R (8 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* PLL1R */ +# define R_SYSTEM_OCTACKCR_OCTACKSEL_PLL2Q (9 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* PLL2Q */ +# define R_SYSTEM_OCTACKCR_OCTACKSEL_PLL2R (10 << R_SYSTEM_OCTACKCR_OCTACKSEL_SHIFT) /* PLL2R */ +#define R_SYSTEM_OCTACKCR_OCTACKSREQ (1 << 6) /* 40: Octal-SPI clock (OCTACLK) Switching Request */ +#define R_SYSTEM_OCTACKCR_OCTACKSRDY (1 << 7) /* 80: Octal-SPI clock (OCTACLK) Switching Ready state flag */ + +/* CANFD Core clock control register (8-bits) *******************************/ + +#define R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT (0) +#define R_SYSTEM_CANFDCKCR_CANFDCKSEL_MASK (0xf) +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_HOCO (0 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_MOCO_VALUE_AFTER_RESET (1 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* MOCO (value after reset) */ +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_LOCO (2 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* LOCO */ +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_PLL1P (5 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* PLL1P */ +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_PLL2P (6 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* PLL2P */ +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_PLL1Q (7 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* PLL1Q */ +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_PLL1R (8 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* PLL1R */ +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_PLL2Q (9 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* PLL2Q */ +# define R_SYSTEM_CANFDCKCR_CANFDCKSEL_PLL2R (10 << R_SYSTEM_CANFDCKCR_CANFDCKSEL_SHIFT) /* PLL2R */ +#define R_SYSTEM_CANFDCKCR_CANFDCKSREQ (1 << 6) /* 40: CANFD Core clock (CANFDCLK) Switching Request */ +#define R_SYSTEM_CANFDCKCR_CANFDCKSRDY (1 << 7) /* 80: CANFD Core clock (CANFDCLK) Switching Ready state flag */ + +/* USB60 clock control register (8-bits) ************************************/ + +#define R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT (0) +#define R_SYSTEM_USB60CKCR_USB60CKSEL_MASK (0xf) +# define R_SYSTEM_USB60CKCR_USB60CKSEL_HOCO (0 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_USB60CKCR_USB60CKSEL_MOCO_VALUE_AFTER_RESET (1 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* MOCO (value after reset) */ +# define R_SYSTEM_USB60CKCR_USB60CKSEL_LOCO (2 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* LOCO */ +# define R_SYSTEM_USB60CKCR_USB60CKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_USB60CKCR_USB60CKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_USB60CKCR_USB60CKSEL_PLL1P (5 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* PLL1P */ +# define R_SYSTEM_USB60CKCR_USB60CKSEL_PLL2P (6 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* PLL2P */ +# define R_SYSTEM_USB60CKCR_USB60CKSEL_PLL1Q (7 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* PLL1Q */ +# define R_SYSTEM_USB60CKCR_USB60CKSEL_PLL1R (8 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* PLL1R */ +# define R_SYSTEM_USB60CKCR_USB60CKSEL_PLL2Q (9 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* PLL2Q */ +# define R_SYSTEM_USB60CKCR_USB60CKSEL_PLL2R (10 << R_SYSTEM_USB60CKCR_USB60CKSEL_SHIFT) /* PLL2R */ +#define R_SYSTEM_USB60CKCR_USB60CKSREQ (1 << 6) /* 40: USB clock (USB60CLK) Switching Request */ +#define R_SYSTEM_USB60CKCR_USB60CKSRDY (1 << 7) /* 80: USB clock (USB60CLK) Switching Ready state flag */ + +/* I3C clock control register (8-bits) **************************************/ + +#define R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT (0) +#define R_SYSTEM_I3CCKCR_I3CCKSEL_MASK (0xf) +# define R_SYSTEM_I3CCKCR_I3CCKSEL_HOCO (0 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* HOCO */ +# define R_SYSTEM_I3CCKCR_I3CCKSEL_MOCO_VALUE_AFTER_RESET (1 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* MOCO (value after reset) */ +# define R_SYSTEM_I3CCKCR_I3CCKSEL_LOCO (2 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* LOCO */ +# define R_SYSTEM_I3CCKCR_I3CCKSEL_MAIN_CLOCK_OSCILLATOR (3 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* Main clock oscillator */ +# define R_SYSTEM_I3CCKCR_I3CCKSEL_SUB_CLOCK_OSCILLATOR (4 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* Sub-clock oscillator */ +# define R_SYSTEM_I3CCKCR_I3CCKSEL_PLL1P (5 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* PLL1P */ +# define R_SYSTEM_I3CCKCR_I3CCKSEL_PLL2P (6 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* PLL2P */ +# define R_SYSTEM_I3CCKCR_I3CCKSEL_PLL1Q (7 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* PLL1Q */ +# define R_SYSTEM_I3CCKCR_I3CCKSEL_PLL1R (8 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* PLL1R */ +# define R_SYSTEM_I3CCKCR_I3CCKSEL_PLL2Q (9 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* PLL2Q */ +# define R_SYSTEM_I3CCKCR_I3CCKSEL_PLL2R (10 << R_SYSTEM_I3CCKCR_I3CCKSEL_SHIFT) /* PLL2R */ +#define R_SYSTEM_I3CCKCR_I3CCKREQ (1 << 6) /* 40: I3C clock (I3CCLK) Switching Request */ +#define R_SYSTEM_I3CCKCR_I3CCKSRDY (1 << 7) /* 80: I3C clock (I3CCLK) Switching Ready state flag */ + +/* Main Clock Oscillator Standby Control Register (8-bits) ******************/ + +#define R_SYSTEM_MOSCSCR_MOSCSOKP (1 << 0) /* 01: Main Clock Oscillator Standby Oscillation Keep select */ + +/* High-Speed On-Chip Oscillator Standby Control Register (8-bits) **********/ + +#define R_SYSTEM_HOCOSCR_HOCOSOKP (1 << 0) /* 01: HOCO Standby Oscillation Keep select */ + +/* Operating Power Control Register (8-bits) ********************************/ + +#define R_SYSTEM_OPCCR_OPCM_SHIFT (0) +#define R_SYSTEM_OPCCR_OPCM_MASK (0x3) +# define R_SYSTEM_OPCCR_OPCM_HIGH_SPEED_MODE (0 << R_SYSTEM_OPCCR_OPCM_SHIFT) /* High-speed mode */ +# define R_SYSTEM_OPCCR_OPCM_PROHIBITED_1 (1 << R_SYSTEM_OPCCR_OPCM_SHIFT) /* Prohibited */ +# define R_SYSTEM_OPCCR_OPCM_PROHIBITED_2 (2 << R_SYSTEM_OPCCR_OPCM_SHIFT) /* Prohibited */ +# define R_SYSTEM_OPCCR_OPCM_LOW_SPEED_MODE (3 << R_SYSTEM_OPCCR_OPCM_SHIFT) /* Low-speed mode */ +#define R_SYSTEM_OPCCR_OPCMTSF (1 << 4) /* 10: Operating Power Control Mode Transition Status Flag */ + +/* Main Clock Oscillator Wait Control Register (8-bits) *********************/ + +#define R_SYSTEM_MOSCWTCR_MSTS_SHIFT (0) +#define R_SYSTEM_MOSCWTCR_MSTS_MASK (0xf) +# define R_SYSTEM_MOSCWTCR_MSTS_V0000 (0 << R_SYSTEM_MOSCWTCR_MSTS_SHIFT) /* Wait time= 11.4us (3 cycles) / 15.3us (4 cycles) */ +# define R_SYSTEM_MOSCWTCR_MSTS_V0001 (1 << R_SYSTEM_MOSCWTCR_MSTS_SHIFT) /* Wait time= 133.5us (35 cycles) / 137.3us (36 cycles) */ +# define R_SYSTEM_MOSCWTCR_MSTS_V0010 (2 << R_SYSTEM_MOSCWTCR_MSTS_SHIFT) /* Wait time= 255.6us (67 cycles) / 259.4us (68 cycles) */ +# define R_SYSTEM_MOSCWTCR_MSTS_V0011 (3 << R_SYSTEM_MOSCWTCR_MSTS_SHIFT) /* Wait time= 499.7us (131 cycles) / 503.5us (132 cycles) */ +# define R_SYSTEM_MOSCWTCR_MSTS_V0100 (4 << R_SYSTEM_MOSCWTCR_MSTS_SHIFT) /* Wait time= 988.0us (259 cycles) / 991.8us (260 cycles) */ +# define R_SYSTEM_MOSCWTCR_MSTS_V0101 (5 << R_SYSTEM_MOSCWTCR_MSTS_SHIFT) /* Wait time= 2086.6us (547 cycles) (value after reset) / 2090.5us (548 cycles) (value after reset) */ +# define R_SYSTEM_MOSCWTCR_MSTS_V0110 (6 << R_SYSTEM_MOSCWTCR_MSTS_SHIFT) /* Wait time= 4039.8us (1059 cycles) / 4043.6us (1060 cycles) */ +# define R_SYSTEM_MOSCWTCR_MSTS_V0111 (7 << R_SYSTEM_MOSCWTCR_MSTS_SHIFT) /* Wait time= 8190.2us (2147 cycles) / 8194.0us (2148 cycles) */ +# define R_SYSTEM_MOSCWTCR_MSTS_V1000 (8 << R_SYSTEM_MOSCWTCR_MSTS_SHIFT) /* Wait time= 16368.9us (4291 cycles) / 16372.7us (4292 cycles) */ +# define R_SYSTEM_MOSCWTCR_MSTS_V1001 (9 << R_SYSTEM_MOSCWTCR_MSTS_SHIFT) /* Wait time= 31139.4us (8163 cycles) / 31143.2us (8164 cycles) */ + +/* Reset Status Register 1 (32-bits) ****************************************/ + +#define R_SYSTEM_RSTSR1_IWDTRF (1 << 0) /* 01: Independent Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. */ +#define R_SYSTEM_RSTSR1_WDT0RF (1 << 1) /* 02: Watchdog Timer0 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. */ +#define R_SYSTEM_RSTSR1_SWRF (1 << 2) /* 04: Software Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. */ +#define R_SYSTEM_RSTSR1_CLU0RF (1 << 4) /* 10: CPU0 Lockup Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. */ +#define R_SYSTEM_RSTSR1_LM0RF (1 << 5) /* 20: Local memory 0 error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. */ +#define R_SYSTEM_RSTSR1_BUSRF (1 << 10) /* 400: Bus error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. */ +#define R_SYSTEM_RSTSR1_CMRF (1 << 14) /* 4000: Common memory error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. */ +#define R_SYSTEM_RSTSR1_WDT1RF (1 << 17) /* 20000: Watchdog Timer1 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. */ +#define R_SYSTEM_RSTSR1_LM1RF (1 << 21) /* 200000: Local memory 1 error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. */ +#define R_SYSTEM_RSTSR1_NWRF (1 << 22) /* 400000: Network Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. */ + +/* System Register Access Control Register (8-bits) *************************/ + +#define R_SYSTEM_SYRACCR_BUSY (1 << 0) /* 01: Access Ready monitor */ + +/* Voltage Monitor %s Circuit Control Register 1 (8-bits) *******************/ + +#define R_SYSTEM_PVDCR1_SIZE 2 +#define R_SYSTEM_PVDCR1_IDTSEL_SHIFT (0) +#define R_SYSTEM_PVDCR1_IDTSEL_MASK (0x3) +# define R_SYSTEM_PVDCR1_IDTSEL_V00 (0 << R_SYSTEM_PVDCR1_IDTSEL_SHIFT) /* Generate when VCC>=Vdet (rise) is detected */ +# define R_SYSTEM_PVDCR1_IDTSEL_V01 (1 << R_SYSTEM_PVDCR1_IDTSEL_SHIFT) /* Generate when VCC + +#include +#include +#include + +#include +#include +#include + +#include + +#include "mpu.h" +#include "arm_internal.h" +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +void up_allocate_heap(void **heap_start, size_t *heap_size) +{ + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +} diff --git a/arch/arm/src/ra8m1/ra_clockconfig.c b/arch/arm/src/ra8m1/ra_clockconfig.c new file mode 100644 index 00000000000..41133a00bc6 --- /dev/null +++ b/arch/arm/src/ra8m1/ra_clockconfig.c @@ -0,0 +1,495 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Clock generation set-up, from the BOARD_* clock options in board.h. + * + * The sequence follows RA8M1 User's Manual section 8.11 (initial system + * clock setting, oscillator and PLL settings, peripheral module-dedicated + * clock setting) and the FSP reference start-up code: + * + * 1. start the oscillators that are used (HOCO, MOSC); the MOCO is + * already running because the MCU starts from it, + * 2. start the PLLs that are used, + * 3. set the flash wait states for the final ICLK and enable the flash + * cache, + * 4. set the dividers and switch the system clock source, + * 5. configure the SCI clock. + * + * A flat (no TrustZone) image runs in the secure state, so every register + * here is the secure instance and PRCR_S protects them. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "ra_clockconfig.h" +#include "hardware/ra8m1_fcache.h" +#include "hardware/ra8m1_system.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SCKDIVCR/SCKDIVCR2 divider encoding */ + +#define RA_SCKDIV_CODE(d) \ + ((d) == 1 ? 0 : (d) == 2 ? 1 : (d) == 4 ? 2 : (d) == 8 ? 3 : \ + (d) == 16 ? 4 : (d) == 32 ? 5 : (d) == 64 ? 6 : (d) == 3 ? 8 : \ + (d) == 6 ? 9 : 10) + +#define RA_SCKDIVCR_VALUE \ + ((RA_SCKDIV_CODE(BOARD_FCLK_DIVIDER) << R_SYSTEM_SCKDIVCR_FCK_SHIFT) | \ + (RA_SCKDIV_CODE(BOARD_ICLK_DIVIDER) << R_SYSTEM_SCKDIVCR_ICK_SHIFT) | \ + (RA_SCKDIV_CODE(BOARD_PCLKE_DIVIDER) << R_SYSTEM_SCKDIVCR_PCKE_SHIFT) | \ + (RA_SCKDIV_CODE(BOARD_BCLK_DIVIDER) << R_SYSTEM_SCKDIVCR_BCK_SHIFT) | \ + (RA_SCKDIV_CODE(BOARD_PCLKA_DIVIDER) << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) | \ + (RA_SCKDIV_CODE(BOARD_PCLKB_DIVIDER) << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) | \ + (RA_SCKDIV_CODE(BOARD_PCLKC_DIVIDER) << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) | \ + (RA_SCKDIV_CODE(BOARD_PCLKD_DIVIDER) << R_SYSTEM_SCKDIVCR_PCKD_SHIFT)) + +#define RA_SCKDIVCR2_VALUE \ + (RA_SCKDIV_CODE(BOARD_CPUCLK_DIVIDER) << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) + +#define RA_SCKDIVCR2_SWITCH_VALUE \ + (RA_SCKDIV_CODE(RA_CPUCLK_SWITCH_DIVIDER) << R_SYSTEM_SCKDIVCR2_CPUCK_SHIFT) + +/* System clock source: BOARD_SYSCLK_SOURCE is already the SCKSCR.CKSEL + * value (board.h sets it to one of the R_SYSTEM_SCKSCR_CKSEL_* codes), so + * it is written to the register as-is; ra_clockconfig.h has already + * checked it is one of the four this port supports. + */ + +#define RA_SCKSCR_VALUE BOARD_SYSCLK_SOURCE + +/* MOSC: drive capability by frequency (as FSP), and the wait time. MOMCR + * bit 4 must be written as 1. MOSCWTCR.MSTS counts LOCO based cycles; + * pick the shortest setting that is at least the requested time (in + * tenths of a microsecond, from the manual's table). + */ + +#if RA_USE_MOSC +# if RA_MOSC_FREQUENCY >= 24000000 +# define RA_MOSC_MODRV0 5 +# else +# define RA_MOSC_MODRV0 3 +# endif + +# if BOARD_MOSC_EXTERNAL_CLOCK +# define RA_MOMCR_VALUE (R_SYSTEM_MOMCR_AGCEN | R_SYSTEM_MOMCR_MOSEL | \ + (RA_MOSC_MODRV0 << R_SYSTEM_MOMCR_MODRV0_SHIFT)) +# define RA_MOSCWTCR_VALUE 0 +# else +# define RA_MOMCR_VALUE (R_SYSTEM_MOMCR_AGCEN | \ + (RA_MOSC_MODRV0 << R_SYSTEM_MOMCR_MODRV0_SHIFT)) +# define RA_MOSC_WAIT_X10 (BOARD_MOSC_STABILIZATION_US * 10) +# define RA_MOSCWTCR_VALUE \ + (RA_MOSC_WAIT_X10 <= 114 ? 0 : RA_MOSC_WAIT_X10 <= 1335 ? 1 : \ + RA_MOSC_WAIT_X10 <= 2556 ? 2 : RA_MOSC_WAIT_X10 <= 4997 ? 3 : \ + RA_MOSC_WAIT_X10 <= 9880 ? 4 : RA_MOSC_WAIT_X10 <= 20866 ? 5 : \ + RA_MOSC_WAIT_X10 <= 40398 ? 6 : RA_MOSC_WAIT_X10 <= 81902 ? 7 : \ + RA_MOSC_WAIT_X10 <= 163689 ? 8 : 9) +# endif +#endif + +/* PLL1 and PLL2 settings. PLLMUL holds the multiplier minus 1. The + * fraction (PLLMULNF) and the source select bit (PLSRCSEL) are written + * from board.h as-is: BOARD_PLLn_MULTIPLIER_FRACTION and BOARD_PLLn_SOURCE + * are already the real, correctly shifted register field values (see + * board.h and ra_clockconfig.h), not raw codes needing a shift here. The + * output dividers are held as the divider minus 1. + */ + +#if RA_USE_PLL1 +# define RA_PLLCCR_VALUE \ + (((BOARD_PLL1_MULTIPLIER - 1) << R_SYSTEM_PLLCCR_PLLMUL_SHIFT) | \ + BOARD_PLL1_MULTIPLIER_FRACTION | BOARD_PLL1_SOURCE | \ + ((BOARD_PLL1_INPUT_DIVIDER - 1) << R_SYSTEM_PLLCCR_PLIDIV_SHIFT)) + +# define RA_PLLCCR2_VALUE \ + (((BOARD_PLL1_DIVIDER_P - 1) << R_SYSTEM_PLLCCR2_PLODIVP_SHIFT) | \ + ((BOARD_PLL1_DIVIDER_Q - 1) << R_SYSTEM_PLLCCR2_PLODIVQ_SHIFT) | \ + ((BOARD_PLL1_DIVIDER_R - 1) << R_SYSTEM_PLLCCR2_PLODIVR_SHIFT)) +#endif + +#if RA_USE_PLL2 +# define RA_PLL2CCR_VALUE \ + (((BOARD_PLL2_MULTIPLIER - 1) << R_SYSTEM_PLL2CCR_PLL2MUL_SHIFT) | \ + BOARD_PLL2_MULTIPLIER_FRACTION | BOARD_PLL2_SOURCE | \ + ((BOARD_PLL2_INPUT_DIVIDER - 1) << R_SYSTEM_PLL2CCR_PL2IDIV_SHIFT)) + +# define RA_PLL2CCR2_VALUE \ + (((BOARD_PLL2_DIVIDER_P - 1) << R_SYSTEM_PLL2CCR2_PL2ODIVP_SHIFT) | \ + ((BOARD_PLL2_DIVIDER_Q - 1) << R_SYSTEM_PLL2CCR2_PL2ODIVQ_SHIFT) | \ + ((BOARD_PLL2_DIVIDER_R - 1) << R_SYSTEM_PLL2CCR2_PL2ODIVR_SHIFT)) +#endif + +/* SCICLK: source select codes (SCICKCR.SCICKSEL) and divider codes + * (SCICKDIVCR.SCICKDIV, non-linear like the system clock dividers). + */ + +#if RA_USE_SCICLK +# if BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_HOCO +# define RA_SCICKSEL_VALUE 0 +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_MOSC +# define RA_SCICKSEL_VALUE 3 +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1P +# define RA_SCICKSEL_VALUE 5 +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2P +# define RA_SCICKSEL_VALUE 6 +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1Q +# define RA_SCICKSEL_VALUE 7 +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1R +# define RA_SCICKSEL_VALUE 8 +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2Q +# define RA_SCICKSEL_VALUE 9 +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2R +# define RA_SCICKSEL_VALUE 10 +# else +# define RA_SCICKSEL_VALUE 1 +# endif + +# define RA_SCICKDIV_VALUE \ + (BOARD_SCICLK_DIVIDER == 1 ? 0 : BOARD_SCICLK_DIVIDER == 2 ? 1 : \ + BOARD_SCICLK_DIVIDER == 4 ? 2 : BOARD_SCICLK_DIVIDER == 6 ? 3 : \ + BOARD_SCICLK_DIVIDER == 8 ? 4 : BOARD_SCICLK_DIVIDER == 3 ? 5 : 6) +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ra_delay_us + * + * Description: + * Busy wait for at least the given time. No timer is available this + * early, so this counts loop iterations. Each iteration takes at least + * one CPU clock cycle, so assuming one cycle per iteration can only make + * the wait longer than requested, never shorter. + * + * Input Parameters: + * us - Time to wait, in microseconds. + * cpuclk_hz - An upper bound for the CPU clock frequency during the wait. + * + ****************************************************************************/ + +#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_PLL +static void ra_delay_us(uint32_t us, uint32_t cpuclk_hz) +{ + uint32_t loops = us * (cpuclk_hz / 1000000); + + if (loops == 0) + { + loops = 1; + } + + __asm__ __volatile__ + ( + "1:\n" + "\tsubs %0, %0, #1\n" + "\tbne 1b\n" + : "+r" (loops) + : + : "cc" + ); +} +#endif + +/**************************************************************************** + * Name: ra_wait_stable + * + * Description: + * Wait until the given OSCSF flag is set, meaning that the oscillator or + * PLL is stable and can be used. + * + ****************************************************************************/ + +#if RA_USE_HOCO || RA_USE_MOSC || RA_USE_PLL1 || RA_USE_PLL2 +static void ra_wait_stable(uint8_t flag) +{ + while ((getreg8(R_SYSTEM_OSCSF) & flag) == 0) + { + } +} +#endif + +/**************************************************************************** + * Name: ra_hoco_start + ****************************************************************************/ + +#if RA_USE_HOCO +static void ra_hoco_start(void) +{ + /* The HOCO is stopped after reset unless OFS1.HOCOEN starts it. Its + * frequency register (HOCOCR2) comes out of reset holding + * OFS1.HOCOFRQ0, the same BOARD_HOCO_FREQUENCY that RA_HOCO_FREQUENCY + * comes from, so only the start is needed here. + */ + + if ((getreg8(R_SYSTEM_HOCOCR) & R_SYSTEM_HOCOCR_HCSTP) != 0) + { + putreg8(0, R_SYSTEM_HOCOCR); + } + + ra_wait_stable(R_SYSTEM_OSCSF_HOCOSF); +} +#endif + +/**************************************************************************** + * Name: ra_mosc_start + ****************************************************************************/ + +#if RA_USE_MOSC +static void ra_mosc_start(void) +{ + /* MOMCR and MOSCWTCR may only be written while the oscillator is + * stopped. After that, start it and wait for it to stabilize. + */ + + if ((getreg8(R_SYSTEM_MOSCCR) & R_SYSTEM_MOSCCR_MOSTP) != 0) + { + putreg8(RA_MOMCR_VALUE, R_SYSTEM_MOMCR); + putreg8(RA_MOSCWTCR_VALUE, R_SYSTEM_MOSCWTCR); + putreg8(0, R_SYSTEM_MOSCCR); + } + + ra_wait_stable(R_SYSTEM_OSCSF_MOSCSF); +} +#endif + +/**************************************************************************** + * Name: ra_pll1_start + ****************************************************************************/ + +#if RA_USE_PLL1 +static void ra_pll1_start(void) +{ + /* PLL1 is stopped after reset, so its settings can be written */ + + putreg16(RA_PLLCCR_VALUE, R_SYSTEM_PLLCCR); + putreg16(RA_PLLCCR2_VALUE, R_SYSTEM_PLLCCR2); + putreg8(0, R_SYSTEM_PLLCR); + + ra_wait_stable(R_SYSTEM_OSCSF_PLLSF); +} +#endif + +/**************************************************************************** + * Name: ra_pll2_start + ****************************************************************************/ + +#if RA_USE_PLL2 +static void ra_pll2_start(void) +{ + putreg16(RA_PLL2CCR_VALUE, R_SYSTEM_PLL2CCR); + putreg16(RA_PLL2CCR2_VALUE, R_SYSTEM_PLL2CCR2); + putreg8(0, R_SYSTEM_PLL2CR); + + ra_wait_stable(R_SYSTEM_OSCSF_PLL2SF); +} +#endif + +/**************************************************************************** + * Name: ra_sysclk_switch + * + * Description: + * Set the dividers and switch the system clock source, keeping the + * frequencies inside their limits at every step. + * + * The MCU starts from the MOCO with every divider at 1. All the + * configurable sources are at least as fast as the MOCO, so the dividers + * are written first: nothing can run faster than configured while the + * source changes. The dividers of ICLK and below are written before the + * CPUCLK one so that CPUCLK never drops below ICLK. + * + * Each register is read back after being written, as the manual asks + * (section 8.12.1), before the next step. + * + ****************************************************************************/ + +static void ra_sysclk_switch(void) +{ + putreg32(RA_SCKDIVCR_VALUE, R_SYSTEM_SCKDIVCR); + getreg32(R_SYSTEM_SCKDIVCR); + +#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_PLL + /* The PLL is selected with CPUCLK at or below the package limit. If the + * final CPUCLK is above it, start with a slower CPU divider, wait for the + * PLL to settle and only then lower the divider (RA8M1 User's Manual + * figure 8.13). + */ + +# if RA_CPUCLK_FREQUENCY > RA_PLL_SWITCH_MAX_CPUCLK + putreg8(RA_SCKDIVCR2_SWITCH_VALUE, R_SYSTEM_SCKDIVCR2); + getreg8(R_SYSTEM_SCKDIVCR2); + + putreg8(RA_SCKSCR_VALUE, R_SYSTEM_SCKSCR); + getreg8(R_SYSTEM_SCKSCR); + + ra_delay_us(RA_CLOCK_SETTLE_US, RA_CPUCLK_FREQUENCY); + + putreg8(RA_SCKDIVCR2_VALUE, R_SYSTEM_SCKDIVCR2); + getreg8(R_SYSTEM_SCKDIVCR2); + + ra_delay_us(RA_CLOCK_SETTLE_US, RA_CPUCLK_FREQUENCY); +# else + putreg8(RA_SCKDIVCR2_VALUE, R_SYSTEM_SCKDIVCR2); + getreg8(R_SYSTEM_SCKDIVCR2); + + putreg8(RA_SCKSCR_VALUE, R_SYSTEM_SCKSCR); + getreg8(R_SYSTEM_SCKSCR); + + ra_delay_us(RA_CLOCK_SETTLE_US, RA_CPUCLK_FREQUENCY); +# endif +#else + putreg8(RA_SCKDIVCR2_VALUE, R_SYSTEM_SCKDIVCR2); + getreg8(R_SYSTEM_SCKDIVCR2); + + putreg8(RA_SCKSCR_VALUE, R_SYSTEM_SCKSCR); + getreg8(R_SYSTEM_SCKSCR); +#endif +} + +/**************************************************************************** + * Name: ra_sciclk_set + * + * Description: + * Select the SCICLK source and divider with the switching handshake of + * the manual (section 8.2.48): request the switch, wait until SCICLK is + * stopped, write the divider and source, release the request, and wait + * until SCICLK runs again. + * + * Changing the divider from a value other than 1 needs the SCI modules + * in the module-stop state. That is the case here: they are all stopped + * after reset and this runs before any of them is started. + * + ****************************************************************************/ + +#if RA_USE_SCICLK +static void ra_sciclk_set(void) +{ + modifyreg8(R_SYSTEM_SCICKCR, 0, R_SYSTEM_SCICKCR_CKSREQ); + while ((getreg8(R_SYSTEM_SCICKCR) & R_SYSTEM_SCICKCR_CKSRDY) == 0) + { + } + + putreg8(RA_SCICKDIV_VALUE, R_SYSTEM_SCICKDIVCR); + putreg8(RA_SCICKSEL_VALUE | R_SYSTEM_SCICKCR_CKSREQ, R_SYSTEM_SCICKCR); + + putreg8(RA_SCICKSEL_VALUE, R_SYSTEM_SCICKCR); + while ((getreg8(R_SYSTEM_SCICKCR) & R_SYSTEM_SCICKCR_CKSRDY) != 0) + { + } +} +#endif + +/**************************************************************************** + * Name: ra_fcache_enable + * + * Description: + * Enable the flash cache, as the FSP reference start-up code does + * (R_BSP_FlashCacheEnable()): invalidate it and wait for the + * invalidation to finish (RA8M1 User's Manual, Flash Memory chapter, + * "Operation") before enabling it. + * + ****************************************************************************/ + +static void ra_fcache_enable(void) +{ + putreg16(R_FCACHE_FCACHEIV_FCACHEIV, R_FCACHE_FCACHEIV); + while ((getreg16(R_FCACHE_FCACHEIV) & R_FCACHE_FCACHEIV_FCACHEIV) != 0) + { + } + + putreg16(R_FCACHE_FCACHEE_FCACHEEN, R_FCACHE_FCACHEE); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ra_clockconfig + * + * Description: + * Called to initialize the RA8M1. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the BOARD_* clock options in board.h. + * + ****************************************************************************/ + +void ra_clockconfig(void) +{ + /* Unlock the clock generation (PRC0) and low power/module stop (PRC1) + * registers. + */ + + putreg16((R_SYSTEM_PRCR_S_PRKEY_V0XA5 | R_SYSTEM_PRCR_S_PRC0 | + R_SYSTEM_PRCR_S_PRC1), R_SYSTEM_PRCR_S); + + /* The MCU is in high-speed operating mode after reset, which is what + * every configuration allowed here needs, so OPCCR is left alone. + */ + + /* Start the oscillators the configuration uses before anything that + * depends on them (the PLLs). The MOCO is already running. + */ + +#if RA_USE_HOCO + ra_hoco_start(); +#endif + +#if RA_USE_MOSC + ra_mosc_start(); +#endif + +#if RA_USE_PLL1 + ra_pll1_start(); +#endif + +#if RA_USE_PLL2 + ra_pll2_start(); +#endif + + /* The flash needs its wait states for the final ICLK. Setting them + * before the clock speeds up is safe: extra wait states at a lower + * frequency only cost time. + */ + + putreg8(RA_FLASH_WAIT_STATES, R_FCACHE_FLWT); + + ra_fcache_enable(); + + ra_sysclk_switch(); + +#if RA_USE_SCICLK + ra_sciclk_set(); +#endif + + /* Lock the protected registers again */ + + putreg16(R_SYSTEM_PRCR_S_PRKEY_V0XA5, R_SYSTEM_PRCR_S); +} diff --git a/arch/arm/src/ra8m1/ra_clockconfig.h b/arch/arm/src/ra8m1/ra_clockconfig.h new file mode 100644 index 00000000000..56e6d2fe853 --- /dev/null +++ b/arch/arm/src/ra8m1/ra_clockconfig.h @@ -0,0 +1,656 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_RA_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_RA8M1_RA_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "hardware/ra8m1_system.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clock frequencies derived from the BOARD_* clock options. + * + * The clock tree is chosen by the board in (see the + * "Clocking" section of that file for every option and its valid values). + * Everything here is a compile-time constant, and every limit in the RA8M1 + * User's Manual chapter 8 (Tables 8.1 and 8.2 and their notes) is checked + * with #error, so a missing option or an invalid combination fails to build + * instead of producing a clock the MCU is not specified for. Some of the + * results are unsigned long long constants (the PLL VCO does not fit in 32 + * bits during the calculation); cast them where a plain integer is needed. + */ + +/* Options the board has to define. There is no default: a board.h that + * does not describe its clock tree does not build. + */ + +#ifndef BOARD_HOCO_FREQUENCY +# error "board.h must define BOARD_HOCO_FREQUENCY" +#endif +#ifndef BOARD_SYSCLK_SOURCE +# error "board.h must define BOARD_SYSCLK_SOURCE" +#endif +#ifndef BOARD_OFS2_DCDC +# error "board.h must define BOARD_OFS2_DCDC" +#endif +#if !defined(BOARD_CPUCLK_DIVIDER) || !defined(BOARD_ICLK_DIVIDER) || \ + !defined(BOARD_PCLKA_DIVIDER) || !defined(BOARD_PCLKB_DIVIDER) || \ + !defined(BOARD_PCLKC_DIVIDER) || !defined(BOARD_PCLKD_DIVIDER) || \ + !defined(BOARD_PCLKE_DIVIDER) || !defined(BOARD_FCLK_DIVIDER) || \ + !defined(BOARD_BCLK_DIVIDER) +# error "board.h must define BOARD_CPUCLK/ICLK/PCLKA-E/FCLK/BCLK_DIVIDER" +#endif + +/* SCICLK source selectors, for BOARD_SCICLK_SOURCE. + * + * Every other *_SOURCE option reuses the real register-field value from + * hardware/ra8m1_system.h (see board.h). SCICKCR.SCICKSEL has no such + * generated names -- the SVD gives this field no enumeratedValues -- so + * this is the one selector this port has to invent, and it is kept here, + * private to this file, rather than in board.h: board.h only references + * these names (no #include needed for that -- a macro's replacement text + * is resolved where it is used, not where it is written), and the actual + * SCICKCR.SCICKSEL codes these translate to are computed in + * ra_clockconfig.c, independently of the numbering used here. + */ + +#define RA_SCICLK_SRC_MOCO 1 +#define RA_SCICLK_SRC_HOCO 2 +#define RA_SCICLK_SRC_MOSC 3 +#define RA_SCICLK_SRC_PLL1P 4 +#define RA_SCICLK_SRC_PLL1Q 5 +#define RA_SCICLK_SRC_PLL1R 6 +#define RA_SCICLK_SRC_PLL2P 7 +#define RA_SCICLK_SRC_PLL2Q 8 +#define RA_SCICLK_SRC_PLL2R 9 + +/* Which oscillators, PLLs and dedicated clocks the configuration needs. + * Each RA_USE_* is 0 or 1. + * + * SCICLK is needed as soon as one SCI UART is enabled: the baud rate + * generator of every SCI runs from it. + */ + +#if defined(CONFIG_RA_SCI0_UART) || defined(CONFIG_RA_SCI1_UART) || \ + defined(CONFIG_RA_SCI2_UART) || defined(CONFIG_RA_SCI3_UART) || \ + defined(CONFIG_RA_SCI4_UART) || defined(CONFIG_RA_SCI9_UART) +# define RA_USE_SCICLK 1 +#else +# define RA_USE_SCICLK 0 +#endif + +#if RA_USE_SCICLK +# if !defined(BOARD_SCICLK_SOURCE) || !defined(BOARD_SCICLK_DIVIDER) +# error "board.h must define BOARD_SCICLK_SOURCE and BOARD_SCICLK_DIVIDER" +# endif +#endif + +#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_PLL || \ + (RA_USE_SCICLK && (BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1P || \ + BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1Q || \ + BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1R)) +# define RA_USE_PLL1 1 +#else +# define RA_USE_PLL1 0 +#endif + +#if RA_USE_SCICLK && (BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2P || \ + BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2Q || \ + BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2R) +# define RA_USE_PLL2 1 +#else +# define RA_USE_PLL2 0 +#endif + +#if RA_USE_PLL1 +# if !defined(BOARD_PLL1_SOURCE) || !defined(BOARD_PLL1_INPUT_DIVIDER) || \ + !defined(BOARD_PLL1_MULTIPLIER) || !defined(BOARD_PLL1_MULTIPLIER_FRACTION) || \ + !defined(BOARD_PLL1_DIVIDER_P) || !defined(BOARD_PLL1_DIVIDER_Q) || \ + !defined(BOARD_PLL1_DIVIDER_R) +# error "PLL1 is used: board.h must define all the BOARD_PLL1_* options" +# endif +#endif + +#if RA_USE_PLL2 +# if !defined(BOARD_PLL2_SOURCE) || !defined(BOARD_PLL2_INPUT_DIVIDER) || \ + !defined(BOARD_PLL2_MULTIPLIER) || !defined(BOARD_PLL2_MULTIPLIER_FRACTION) || \ + !defined(BOARD_PLL2_DIVIDER_P) || !defined(BOARD_PLL2_DIVIDER_Q) || \ + !defined(BOARD_PLL2_DIVIDER_R) +# error "PLL2 is used: board.h must define all the BOARD_PLL2_* options" +# endif +#endif + +#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_HOCO || \ + (RA_USE_SCICLK && BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_HOCO) || \ + (RA_USE_PLL1 && BOARD_PLL1_SOURCE == R_SYSTEM_PLLCCR_PLSRCSEL) || \ + (RA_USE_PLL2 && BOARD_PLL2_SOURCE == R_SYSTEM_PLL2CCR_PL2SRCSEL) +# define RA_USE_HOCO 1 +#else +# define RA_USE_HOCO 0 +#endif + +#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_MAIN_CLOCK_OSCILLATOR || \ + (RA_USE_SCICLK && BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_MOSC) || \ + (RA_USE_PLL1 && BOARD_PLL1_SOURCE == 0) || \ + (RA_USE_PLL2 && BOARD_PLL2_SOURCE == 0) +# define RA_USE_MOSC 1 +#else +# define RA_USE_MOSC 0 +#endif + +#if BOARD_SYSCLK_SOURCE != R_SYSTEM_SCKSCR_CKSEL_MOCO && \ + BOARD_SYSCLK_SOURCE != R_SYSTEM_SCKSCR_CKSEL_HOCO && \ + BOARD_SYSCLK_SOURCE != R_SYSTEM_SCKSCR_CKSEL_MAIN_CLOCK_OSCILLATOR && \ + BOARD_SYSCLK_SOURCE != R_SYSTEM_SCKSCR_CKSEL_PLL +# error "BOARD_SYSCLK_SOURCE must be R_SYSTEM_SCKSCR_CKSEL_MOCO, _HOCO, _MAIN_CLOCK_OSCILLATOR or _PLL" +#endif + +/* Oscillators */ + +#define RA_MOCO_FREQUENCY 8000000 + +/* The HOCO frequency after reset is the one programmed into OFS1 (see + * ra_option_setting.c), so BOARD_HOCO_FREQUENCY is used for both. + */ + +#if BOARD_HOCO_FREQUENCY != 16000000 && BOARD_HOCO_FREQUENCY != 18000000 && \ + BOARD_HOCO_FREQUENCY != 20000000 && BOARD_HOCO_FREQUENCY != 32000000 && \ + BOARD_HOCO_FREQUENCY != 48000000 +# error "BOARD_HOCO_FREQUENCY must be 16, 18, 20, 32 or 48 MHz" +#endif + +#define RA_HOCO_FREQUENCY BOARD_HOCO_FREQUENCY + +#if RA_USE_MOSC +# if !defined(BOARD_MOSC_FREQUENCY) || !defined(BOARD_MOSC_EXTERNAL_CLOCK) || \ + !defined(BOARD_MOSC_STABILIZATION_US) +# error "MOSC is used: board.h must define BOARD_MOSC_FREQUENCY, BOARD_MOSC_EXTERNAL_CLOCK and BOARD_MOSC_STABILIZATION_US" +# endif +# if BOARD_MOSC_FREQUENCY < 8000000 || BOARD_MOSC_FREQUENCY > 48000000 +# error "BOARD_MOSC_FREQUENCY must be 8 MHz to 48 MHz" +# endif +# if !BOARD_MOSC_EXTERNAL_CLOCK && \ + (BOARD_MOSC_STABILIZATION_US < 12 || BOARD_MOSC_STABILIZATION_US > 31139) +# error "BOARD_MOSC_STABILIZATION_US must be 12 us to 31139 us" +# endif +# define RA_MOSC_FREQUENCY BOARD_MOSC_FREQUENCY +#endif + +/* Divider validity. The dividers are the values 1, 2, 3, 4, 6, 8, 12, 16, + * 32 and 64 (SCKDIVCR/SCKDIVCR2 encode them non-linearly). + */ + +#define RA_SCKDIV_VALID(d) \ + ((d) == 1 || (d) == 2 || (d) == 3 || (d) == 4 || (d) == 6 || \ + (d) == 8 || (d) == 12 || (d) == 16 || (d) == 32 || (d) == 64) +#define RA_SCKDIV_FAMILY_A(d) \ + ((d) == 2 || (d) == 4 || (d) == 8 || (d) == 16 || (d) == 32 || (d) == 64) +#define RA_SCKDIV_FAMILY_B(d) ((d) == 3 || (d) == 6 || (d) == 12) + +#define RA_PLL_DIV_P_VALID(d) \ + ((d) == 2 || (d) == 4 || (d) == 6 || (d) == 8 || (d) == 16) +#define RA_PLL_DIV_QR_VALID(d) \ + ((d) == 2 || (d) == 3 || (d) == 4 || (d) == 5 || (d) == 6 || \ + (d) == 8 || (d) == 9) + +#define RA_SCICLK_DIV_VALID(d) \ + ((d) == 1 || (d) == 2 || (d) == 3 || (d) == 4 || (d) == 5 || \ + (d) == 6 || (d) == 8) + +/* PLL1 and PLL2 */ + +#if RA_USE_PLL1 + +# if BOARD_PLL1_SOURCE == 0 +# define RA_PLL1_SOURCE_FREQUENCY RA_MOSC_FREQUENCY +# elif BOARD_PLL1_SOURCE == R_SYSTEM_PLLCCR_PLSRCSEL +# define RA_PLL1_SOURCE_FREQUENCY RA_HOCO_FREQUENCY +# else +# error "BOARD_PLL1_SOURCE must be 0 (MOSC) or R_SYSTEM_PLLCCR_PLSRCSEL (HOCO)" +# endif + +# if BOARD_PLL1_INPUT_DIVIDER < 1 || BOARD_PLL1_INPUT_DIVIDER > 4 +# error "BOARD_PLL1_INPUT_DIVIDER must be 1 to 4" +# endif +# if BOARD_PLL1_MULTIPLIER < 53 || BOARD_PLL1_MULTIPLIER > 180 +# error "BOARD_PLL1_MULTIPLIER must be 53 to 180" +# endif + +# if BOARD_PLL1_MULTIPLIER_FRACTION == R_SYSTEM_PLLCCR_PLLMULNF_V0_33_1_3 +# define RA_PLL1_MULF6 2 /* 1/3 = 2/6 */ +# elif BOARD_PLL1_MULTIPLIER_FRACTION == R_SYSTEM_PLLCCR_PLLMULNF_V0_50_1_2 +# define RA_PLL1_MULF6 3 /* 1/2 = 3/6 */ +# elif BOARD_PLL1_MULTIPLIER_FRACTION == R_SYSTEM_PLLCCR_PLLMULNF_V0_66_2_3 +# define RA_PLL1_MULF6 4 /* 2/3 = 4/6 */ +# elif BOARD_PLL1_MULTIPLIER_FRACTION == \ + R_SYSTEM_PLLCCR_PLLMULNF_V0_00_VALUE_AFTER_RESET +# define RA_PLL1_MULF6 0 +# else +# error "BOARD_PLL1_MULTIPLIER_FRACTION must be one of the R_SYSTEM_PLLCCR_PLLMULNF_* codes" +# endif + +# define RA_PLL1_INPUT_FREQUENCY (RA_PLL1_SOURCE_FREQUENCY / BOARD_PLL1_INPUT_DIVIDER) +# define RA_PLL1_VCO_FREQUENCY \ + ((RA_PLL1_INPUT_FREQUENCY * (6ULL * BOARD_PLL1_MULTIPLIER + RA_PLL1_MULF6)) / 6ULL) +# define RA_PLL1P_FREQUENCY (RA_PLL1_VCO_FREQUENCY / BOARD_PLL1_DIVIDER_P) +# define RA_PLL1Q_FREQUENCY (RA_PLL1_VCO_FREQUENCY / BOARD_PLL1_DIVIDER_Q) +# define RA_PLL1R_FREQUENCY (RA_PLL1_VCO_FREQUENCY / BOARD_PLL1_DIVIDER_R) + +# if RA_PLL1_SOURCE_FREQUENCY < 8000000 || RA_PLL1_SOURCE_FREQUENCY > 48000000 +# error "PLL1 source clock must be 8 MHz to 48 MHz" +# endif +# if RA_PLL1_INPUT_FREQUENCY < 6000000 || RA_PLL1_INPUT_FREQUENCY > 12000000 +# error "PLL1 input frequency after the input divider must be 6 MHz to 12 MHz" +# endif +# if RA_PLL1_VCO_FREQUENCY < 640000000ULL || RA_PLL1_VCO_FREQUENCY > 1440000000ULL +# error "PLL1 VCO frequency must be 640 MHz to 1440 MHz" +# endif +# if !RA_PLL_DIV_P_VALID(BOARD_PLL1_DIVIDER_P) +# error "PLL1 output P divider must be 2, 4, 6, 8 or 16" +# endif +# if !RA_PLL_DIV_QR_VALID(BOARD_PLL1_DIVIDER_Q) || !RA_PLL_DIV_QR_VALID(BOARD_PLL1_DIVIDER_R) +# error "PLL1 output Q/R dividers must be 2, 3, 4, 5, 6, 8 or 9" +# endif +# if RA_PLL1P_FREQUENCY < 40000000 || RA_PLL1P_FREQUENCY > 480000000 +# error "PLL1P must be 40 MHz to 480 MHz" +# endif +# if RA_PLL1Q_FREQUENCY < 71000000 || RA_PLL1Q_FREQUENCY > 480000000 +# error "PLL1Q must be 71 MHz to 480 MHz" +# endif +# if RA_PLL1R_FREQUENCY < 71000000 || RA_PLL1R_FREQUENCY > 480000000 +# error "PLL1R must be 71 MHz to 480 MHz" +# endif + +#endif /* RA_USE_PLL1 */ + +#if RA_USE_PLL2 + +# if BOARD_PLL2_SOURCE == 0 +# define RA_PLL2_SOURCE_FREQUENCY RA_MOSC_FREQUENCY +# elif BOARD_PLL2_SOURCE == R_SYSTEM_PLL2CCR_PL2SRCSEL +# define RA_PLL2_SOURCE_FREQUENCY RA_HOCO_FREQUENCY +# else +# error "BOARD_PLL2_SOURCE must be 0 (MOSC) or R_SYSTEM_PLL2CCR_PL2SRCSEL (HOCO)" +# endif + +# if BOARD_PLL2_INPUT_DIVIDER < 1 || BOARD_PLL2_INPUT_DIVIDER > 4 +# error "BOARD_PLL2_INPUT_DIVIDER must be 1 to 4" +# endif +# if BOARD_PLL2_MULTIPLIER < 53 || BOARD_PLL2_MULTIPLIER > 180 +# error "BOARD_PLL2_MULTIPLIER must be 53 to 180" +# endif + +# if BOARD_PLL2_MULTIPLIER_FRACTION == R_SYSTEM_PLL2CCR_PLL2MULNF_V0_33_1_3 +# define RA_PLL2_MULF6 2 /* 1/3 = 2/6 */ +# elif BOARD_PLL2_MULTIPLIER_FRACTION == R_SYSTEM_PLL2CCR_PLL2MULNF_V0_50_1_2 +# define RA_PLL2_MULF6 3 /* 1/2 = 3/6 */ +# elif BOARD_PLL2_MULTIPLIER_FRACTION == R_SYSTEM_PLL2CCR_PLL2MULNF_V0_66_2_3 +# define RA_PLL2_MULF6 4 /* 2/3 = 4/6 */ +# elif BOARD_PLL2_MULTIPLIER_FRACTION == \ + R_SYSTEM_PLL2CCR_PLL2MULNF_V0_00_VALUE_AFTER_RESET +# define RA_PLL2_MULF6 0 +# else +# error "BOARD_PLL2_MULTIPLIER_FRACTION must be one of the R_SYSTEM_PLL2CCR_PLL2MULNF_* codes" +# endif + +# define RA_PLL2_INPUT_FREQUENCY (RA_PLL2_SOURCE_FREQUENCY / BOARD_PLL2_INPUT_DIVIDER) +# define RA_PLL2_VCO_FREQUENCY \ + ((RA_PLL2_INPUT_FREQUENCY * (6ULL * BOARD_PLL2_MULTIPLIER + RA_PLL2_MULF6)) / 6ULL) +# define RA_PLL2P_FREQUENCY (RA_PLL2_VCO_FREQUENCY / BOARD_PLL2_DIVIDER_P) +# define RA_PLL2Q_FREQUENCY (RA_PLL2_VCO_FREQUENCY / BOARD_PLL2_DIVIDER_Q) +# define RA_PLL2R_FREQUENCY (RA_PLL2_VCO_FREQUENCY / BOARD_PLL2_DIVIDER_R) + +# if RA_PLL2_SOURCE_FREQUENCY < 8000000 || RA_PLL2_SOURCE_FREQUENCY > 48000000 +# error "PLL2 source clock must be 8 MHz to 48 MHz" +# endif +# if RA_PLL2_INPUT_FREQUENCY < 6000000 || RA_PLL2_INPUT_FREQUENCY > 12000000 +# error "PLL2 input frequency after the input divider must be 6 MHz to 12 MHz" +# endif +# if RA_PLL2_VCO_FREQUENCY < 640000000ULL || RA_PLL2_VCO_FREQUENCY > 1440000000ULL +# error "PLL2 VCO frequency must be 640 MHz to 1440 MHz" +# endif +# if !RA_PLL_DIV_P_VALID(BOARD_PLL2_DIVIDER_P) +# error "PLL2 output P divider must be 2, 4, 6, 8 or 16" +# endif +# if !RA_PLL_DIV_QR_VALID(BOARD_PLL2_DIVIDER_Q) || !RA_PLL_DIV_QR_VALID(BOARD_PLL2_DIVIDER_R) +# error "PLL2 output Q/R dividers must be 2, 3, 4, 5, 6, 8 or 9" +# endif +# if RA_PLL2P_FREQUENCY < 40000000 || RA_PLL2P_FREQUENCY > 480000000 +# error "PLL2P must be 40 MHz to 480 MHz" +# endif +# if RA_PLL2Q_FREQUENCY < 71000000 || RA_PLL2Q_FREQUENCY > 480000000 +# error "PLL2Q must be 71 MHz to 480 MHz" +# endif +# if RA_PLL2R_FREQUENCY < 71000000 || RA_PLL2R_FREQUENCY > 480000000 +# error "PLL2R must be 71 MHz to 480 MHz" +# endif + +#endif /* RA_USE_PLL2 */ + +/* System clock source */ + +#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_HOCO +# define RA_SYSCLK_FREQUENCY RA_HOCO_FREQUENCY +#elif BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_MAIN_CLOCK_OSCILLATOR +# define RA_SYSCLK_FREQUENCY RA_MOSC_FREQUENCY +#elif BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_PLL +# define RA_SYSCLK_FREQUENCY RA_PLL1P_FREQUENCY +#else +# define RA_SYSCLK_FREQUENCY RA_MOCO_FREQUENCY +#endif + +/* Clocks derived from the system clock */ + +#define RA_CPUCLK_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_CPUCLK_DIVIDER) +#define RA_ICLK_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_ICLK_DIVIDER) +#define RA_PCLKA_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_PCLKA_DIVIDER) +#define RA_PCLKB_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_PCLKB_DIVIDER) +#define RA_PCLKC_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_PCLKC_DIVIDER) +#define RA_PCLKD_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_PCLKD_DIVIDER) +#define RA_PCLKE_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_PCLKE_DIVIDER) +#define RA_FCLK_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_FCLK_DIVIDER) +#define RA_BCLK_FREQUENCY (RA_SYSCLK_FREQUENCY / BOARD_BCLK_DIVIDER) + +/* SCI clock (SCICLK): the clock of the SCI baud rate generator. When no + * SCI UART is enabled it is left at its reset value, the MOCO. + */ + +#if RA_USE_SCICLK +# if BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_HOCO +# define RA_SCICLK_SOURCE_FREQUENCY RA_HOCO_FREQUENCY +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_MOSC +# define RA_SCICLK_SOURCE_FREQUENCY RA_MOSC_FREQUENCY +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1P +# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL1P_FREQUENCY +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1Q +# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL1Q_FREQUENCY +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL1R +# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL1R_FREQUENCY +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2P +# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL2P_FREQUENCY +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2Q +# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL2Q_FREQUENCY +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_PLL2R +# define RA_SCICLK_SOURCE_FREQUENCY RA_PLL2R_FREQUENCY +# elif BOARD_SCICLK_SOURCE == RA_SCICLK_SRC_MOCO +# define RA_SCICLK_SOURCE_FREQUENCY RA_MOCO_FREQUENCY +# else +# error "BOARD_SCICLK_SOURCE is not a valid clock source" +# endif +# define RA_SCICLK_FREQUENCY \ + (RA_SCICLK_SOURCE_FREQUENCY / BOARD_SCICLK_DIVIDER) +#else +# define RA_SCICLK_FREQUENCY RA_MOCO_FREQUENCY +#endif + +/* Package dependent limit for switching the system clock to the PLL. The + * switch has to happen with CPUCLK at or below this frequency (RA8M1 User's + * Manual figures 8.13-8.15); CPUCLK is then raised by dropping its divider. + * The package is the one of the selected part number (PLBG0224 = 224-pin + * BGA, PLQP0176/0144/0100 = LQFP). The "AM" package does not appear in the + * manual, so it is treated like the most restrictive one. + */ + +#if defined(CONFIG_ARCH_CHIP_R7FA8M1AFECBD) || \ + defined(CONFIG_ARCH_CHIP_R7FA8M1AHECBD) +# define RA_PLL_SWITCH_MAX_CPUCLK 240000000 +#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFC) || \ + defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFC) || \ + defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFB) || \ + defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFB) +# define RA_PLL_SWITCH_MAX_CPUCLK 200000000 +#else +# define RA_PLL_SWITCH_MAX_CPUCLK 180000000 +#endif + +/* Settling time after the system clock is switched to the PLL: 150 us with + * the DCDC converter enabled, 10 us with an external VDD. + */ + +#if BOARD_OFS2_DCDC +# define RA_CLOCK_SETTLE_US 150 +#else +# define RA_CLOCK_SETTLE_US 10 +#endif + +/* Flash wait states (FCACHE.FLWT) required for the ICLK frequency */ + +#if RA_ICLK_FREQUENCY <= 48000000 +# define RA_FLASH_WAIT_STATES 0 +#elif RA_ICLK_FREQUENCY <= 96000000 +# define RA_FLASH_WAIT_STATES 1 +#elif RA_ICLK_FREQUENCY <= 144000000 +# define RA_FLASH_WAIT_STATES 2 +#elif RA_ICLK_FREQUENCY <= 192000000 +# define RA_FLASH_WAIT_STATES 3 +#else +# define RA_FLASH_WAIT_STATES 4 +#endif + +/* Divider families: 3, 6 and 12 can not be mixed with 2, 4, 8, 16, 32, 64 */ + +#define RA_ANY_DIV_A \ + (RA_SCKDIV_FAMILY_A(BOARD_CPUCLK_DIVIDER) || \ + RA_SCKDIV_FAMILY_A(BOARD_ICLK_DIVIDER) || \ + RA_SCKDIV_FAMILY_A(BOARD_PCLKA_DIVIDER) || \ + RA_SCKDIV_FAMILY_A(BOARD_PCLKB_DIVIDER) || \ + RA_SCKDIV_FAMILY_A(BOARD_PCLKC_DIVIDER) || \ + RA_SCKDIV_FAMILY_A(BOARD_PCLKD_DIVIDER) || \ + RA_SCKDIV_FAMILY_A(BOARD_PCLKE_DIVIDER) || \ + RA_SCKDIV_FAMILY_A(BOARD_FCLK_DIVIDER) || \ + RA_SCKDIV_FAMILY_A(BOARD_BCLK_DIVIDER)) +#define RA_ANY_DIV_B \ + (RA_SCKDIV_FAMILY_B(BOARD_CPUCLK_DIVIDER) || \ + RA_SCKDIV_FAMILY_B(BOARD_ICLK_DIVIDER) || \ + RA_SCKDIV_FAMILY_B(BOARD_PCLKA_DIVIDER) || \ + RA_SCKDIV_FAMILY_B(BOARD_PCLKB_DIVIDER) || \ + RA_SCKDIV_FAMILY_B(BOARD_PCLKC_DIVIDER) || \ + RA_SCKDIV_FAMILY_B(BOARD_PCLKD_DIVIDER) || \ + RA_SCKDIV_FAMILY_B(BOARD_PCLKE_DIVIDER) || \ + RA_SCKDIV_FAMILY_B(BOARD_FCLK_DIVIDER) || \ + RA_SCKDIV_FAMILY_B(BOARD_BCLK_DIVIDER)) + +/* CPUCLK divider used while the PLL is first selected as the system clock + * when CPUCLK is above RA_PLL_SWITCH_MAX_CPUCLK: twice (or, in the 3/6/12 + * family, three times) slower than the final one. + */ + +#if RA_ANY_DIV_B +# define RA_CPUCLK_SWITCH_DIVIDER (BOARD_CPUCLK_DIVIDER * 3) +#else +# define RA_CPUCLK_SWITCH_DIVIDER (BOARD_CPUCLK_DIVIDER * 2) +#endif + +/* Checks against RA8M1 User's Manual chapter 8, Table 8.2 and its notes */ + +#if !RA_SCKDIV_VALID(BOARD_CPUCLK_DIVIDER) || \ + !RA_SCKDIV_VALID(BOARD_ICLK_DIVIDER) || \ + !RA_SCKDIV_VALID(BOARD_PCLKA_DIVIDER) || \ + !RA_SCKDIV_VALID(BOARD_PCLKB_DIVIDER) || \ + !RA_SCKDIV_VALID(BOARD_PCLKC_DIVIDER) || \ + !RA_SCKDIV_VALID(BOARD_PCLKD_DIVIDER) || \ + !RA_SCKDIV_VALID(BOARD_PCLKE_DIVIDER) || \ + !RA_SCKDIV_VALID(BOARD_FCLK_DIVIDER) || \ + !RA_SCKDIV_VALID(BOARD_BCLK_DIVIDER) +# error "System clock dividers must be 1, 2, 3, 4, 6, 8, 12, 16, 32 or 64" +#endif + +#if RA_ANY_DIV_A && RA_ANY_DIV_B +# error "Clock dividers of 3, 6 and 12 can not be mixed with 2, 4, 8, 16, 32 and 64" +#endif + +#if RA_CPUCLK_FREQUENCY > 480000000 +# error "CPUCLK must be at most 480 MHz" +#endif +#if RA_ICLK_FREQUENCY > 240000000 +# error "ICLK must be at most 240 MHz" +#endif +#if RA_PCLKA_FREQUENCY > 120000000 +# error "PCLKA must be at most 120 MHz" +#endif +#if RA_PCLKB_FREQUENCY > 60000000 +# error "PCLKB must be at most 60 MHz" +#endif +#if RA_PCLKC_FREQUENCY > 60000000 +# error "PCLKC must be at most 60 MHz" +#endif +#if RA_PCLKD_FREQUENCY > 120000000 +# error "PCLKD must be at most 120 MHz" +#endif +#if RA_PCLKE_FREQUENCY > 240000000 +# error "PCLKE must be at most 240 MHz" +#endif +#if RA_FCLK_FREQUENCY > 60000000 +# error "FCLK must be at most 60 MHz" +#endif +#if RA_BCLK_FREQUENCY > 120000000 +# error "BCLK must be at most 120 MHz" +#endif + +/* Frequency ordering and integer ratios: CPUCLK >= ICLK >= PCLKA >= PCLKB, + * ICLK >= FCLK, ICLK >= BCLK, PCLKD >= PCLKA, CPUCLK:ICLK = N:1, + * ICLK:{PCLKA, PCLKB, FCLK, BCLK} = N:1 and ICLK:{PCLKC, PCLKD, PCLKE} = + * N:1 or 1:N. + */ + +#if BOARD_ICLK_DIVIDER < BOARD_CPUCLK_DIVIDER || \ + (BOARD_ICLK_DIVIDER % BOARD_CPUCLK_DIVIDER) != 0 +# error "CPUCLK:ICLK must be an integer ratio with CPUCLK >= ICLK" +#endif +#if BOARD_PCLKA_DIVIDER < BOARD_ICLK_DIVIDER || \ + (BOARD_PCLKA_DIVIDER % BOARD_ICLK_DIVIDER) != 0 +# error "ICLK:PCLKA must be an integer ratio with ICLK >= PCLKA" +#endif +#if BOARD_PCLKB_DIVIDER < BOARD_PCLKA_DIVIDER +# error "PCLKA must be at least PCLKB" +#endif +#if BOARD_PCLKB_DIVIDER < BOARD_ICLK_DIVIDER || \ + (BOARD_PCLKB_DIVIDER % BOARD_ICLK_DIVIDER) != 0 +# error "ICLK:PCLKB must be an integer ratio with ICLK >= PCLKB" +#endif +#if BOARD_FCLK_DIVIDER < BOARD_ICLK_DIVIDER || \ + (BOARD_FCLK_DIVIDER % BOARD_ICLK_DIVIDER) != 0 +# error "ICLK:FCLK must be an integer ratio with ICLK >= FCLK" +#endif +#if BOARD_BCLK_DIVIDER < BOARD_ICLK_DIVIDER || \ + (BOARD_BCLK_DIVIDER % BOARD_ICLK_DIVIDER) != 0 +# error "ICLK:BCLK must be an integer ratio with ICLK >= BCLK" +#endif +#if BOARD_PCLKD_DIVIDER > BOARD_PCLKA_DIVIDER +# error "PCLKD must be at least PCLKA" +#endif +#if ((BOARD_PCLKC_DIVIDER % BOARD_ICLK_DIVIDER) != 0 && \ + (BOARD_ICLK_DIVIDER % BOARD_PCLKC_DIVIDER) != 0) || \ + ((BOARD_PCLKD_DIVIDER % BOARD_ICLK_DIVIDER) != 0 && \ + (BOARD_ICLK_DIVIDER % BOARD_PCLKD_DIVIDER) != 0) || \ + ((BOARD_PCLKE_DIVIDER % BOARD_ICLK_DIVIDER) != 0 && \ + (BOARD_ICLK_DIVIDER % BOARD_PCLKE_DIVIDER) != 0) +# error "ICLK:PCLKC/PCLKD/PCLKE must be an integer ratio (N:1 or 1:N)" +#endif + +/* When the HOCO feeds PLL1 the CPU clock is limited to 360 MHz */ + +#if RA_USE_PLL1 && BOARD_PLL1_SOURCE == R_SYSTEM_PLLCCR_PLSRCSEL && \ + RA_CPUCLK_FREQUENCY > 360000000 +# error "CPUCLK above 360 MHz needs the main oscillator as the PLL1 source" +#endif + +/* Switching to the PLL: CPUCLK has to be at or below the package limit at + * the moment of the switch, and raised afterwards with the divider. + */ + +#if BOARD_SYSCLK_SOURCE == R_SYSTEM_SCKSCR_CKSEL_PLL && \ + RA_CPUCLK_FREQUENCY > RA_PLL_SWITCH_MAX_CPUCLK +# if BOARD_CPUCLK_DIVIDER != 1 +# error "CPUCLK above the PLL switch limit needs a CPUCLK divider of 1" +# endif +# if (RA_SYSCLK_FREQUENCY / RA_CPUCLK_SWITCH_DIVIDER) > \ + RA_PLL_SWITCH_MAX_CPUCLK +# error "CPUCLK is more than 2x (3x) the limit for switching to the PLL" +# endif +#endif + +#if RA_USE_SCICLK +# if !RA_SCICLK_DIV_VALID(BOARD_SCICLK_DIVIDER) +# error "SCICLK divider must be 1, 2, 3, 4, 5, 6 or 8" +# endif +# if RA_SCICLK_FREQUENCY > 120000000 +# error "SCICLK must be at most 120 MHz" +# endif +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: ra_clockconfig + * + * Description: + * Called to initialize the RA8M1. This does whatever setup is needed to + * put the SoC in a usable state. This includes starting the oscillators + * and PLLs, selecting the system clock source, setting the clock + * dividers and configuring the peripheral dedicated clocks, all from the + * BOARD_* clock options in board.h. + * + ****************************************************************************/ + +void ra_clockconfig(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_RA8M1_RA_CLOCKCONFIG_H */ diff --git a/arch/arm/src/ra8m1/ra_gpio.c b/arch/arm/src/ra8m1/ra_gpio.c new file mode 100644 index 00000000000..bc1a64242b2 --- /dev/null +++ b/arch/arm/src/ra8m1/ra_gpio.c @@ -0,0 +1,115 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "ra_gpio.h" +#include "hardware/ra8m1_pinmap.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ra_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + * cfgset.cfg is written to the pin's PmnPFS register in a single 32-bit + * access: PMR/PSEL/PCR/NCODR/DSCR select the pin's function and drive + * characteristics, while PDR/PODR set its initial direction/output level + * -- PmnPFS.PDR and PmnPFS.PODR are the same physical bits as + * PORTm.PCNTR1's PDR/PODR (RA8M1 User's Manual 19.2.5), so no separate + * PCNTR1 write is needed here. + * + ****************************************************************************/ + +void ra_configgpio(gpio_pinset_t cfgset) +{ + uint8_t regval; + + regval = R_PFS_PWPR_PFSWE; + putreg8(0, R_PFS_PWPR); + putreg8(regval, R_PFS_PWPR); + + putreg32(cfgset.cfg, R_PFS(cfgset.port, cfgset.pin)); + + regval = R_PFS_PWPR_B0WI; + putreg8(0, R_PFS_PWPR); + putreg8(regval, R_PFS_PWPR); +} + +/**************************************************************************** + * Name: ra_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void ra_gpiowrite(gpio_pinset_t pinset, bool value) +{ + if (value) + { + putreg16((1 << pinset.pin), R_PORT_POSR(pinset.port)); + } + else + { + putreg16((1 << pinset.pin), R_PORT_PORR(pinset.port)); + } +} + +/**************************************************************************** + * Name: ra_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool ra_gpioread(gpio_pinset_t pinset) +{ + return (getreg16(R_PORT_PIDR(pinset.port)) & + (uint16_t)(0x01 << pinset.pin)); +} diff --git a/arch/arm/src/ra8m1/ra_gpio.h b/arch/arm/src/ra8m1/ra_gpio.h new file mode 100644 index 00000000000..aa858036138 --- /dev/null +++ b/arch/arm/src/ra8m1/ra_gpio.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_RA_GPIO_H +#define __ARCH_ARM_SRC_RA8M1_RA_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "hardware/ra8m1_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Must be big enough to hold the 32-bit encoding */ + +typedef struct gpio_pinset +{ + uint8_t port; + uint8_t pin; + uint32_t cfg; +}gpio_pinset_t; + +/**************************************************************************** + * Name: ra_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +void ra_configgpio(gpio_pinset_t cfgset); + +/**************************************************************************** + * Name: ra_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void ra_gpiowrite(gpio_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: ra_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool ra_gpioread(gpio_pinset_t pinset); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_RA8M1_RA_GPIO_H */ diff --git a/arch/arm/src/ra8m1/ra_icu.c b/arch/arm/src/ra8m1/ra_icu.c new file mode 100644 index 00000000000..36ccad376c2 --- /dev/null +++ b/arch/arm/src/ra8m1/ra_icu.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_icu.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" +#include "hardware/ra8m1_icu.h" +#include "hardware/ra8m1_elc.h" +#include "ra_icu.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ra_attach_icu + * + * Description: + * Every ICU IELSR slot is runtime-configurable -- any peripheral event + * can be routed to any slot. This wires each enabled SCI_B channel's + * RXI/TXI/TEI/ERI events into the slots that irq.h assigned them + * (SCIn_RXI/TXI/TEI/ERI), so their vector numbers actually fire. + * + ****************************************************************************/ + +void ra_attach_icu(void) +{ +#ifdef CONFIG_RA_SCI0_UART + putreg32(EVENT_SCI0_RXI, R_ICU_IELSR(SCI0_RXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI0_TXI, R_ICU_IELSR(SCI0_TXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI0_TEI, R_ICU_IELSR(SCI0_TEI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI0_ERI, R_ICU_IELSR(SCI0_ERI - RA_IRQ_FIRST)); +#endif +#ifdef CONFIG_RA_SCI1_UART + putreg32(EVENT_SCI1_RXI, R_ICU_IELSR(SCI1_RXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI1_TXI, R_ICU_IELSR(SCI1_TXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI1_TEI, R_ICU_IELSR(SCI1_TEI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI1_ERI, R_ICU_IELSR(SCI1_ERI - RA_IRQ_FIRST)); +#endif +#ifdef CONFIG_RA_SCI2_UART + putreg32(EVENT_SCI2_RXI, R_ICU_IELSR(SCI2_RXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI2_TXI, R_ICU_IELSR(SCI2_TXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI2_TEI, R_ICU_IELSR(SCI2_TEI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI2_ERI, R_ICU_IELSR(SCI2_ERI - RA_IRQ_FIRST)); +#endif +#ifdef CONFIG_RA_SCI3_UART + putreg32(EVENT_SCI3_RXI, R_ICU_IELSR(SCI3_RXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI3_TXI, R_ICU_IELSR(SCI3_TXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI3_TEI, R_ICU_IELSR(SCI3_TEI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI3_ERI, R_ICU_IELSR(SCI3_ERI - RA_IRQ_FIRST)); +#endif +#ifdef CONFIG_RA_SCI4_UART + putreg32(EVENT_SCI4_RXI, R_ICU_IELSR(SCI4_RXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI4_TXI, R_ICU_IELSR(SCI4_TXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI4_TEI, R_ICU_IELSR(SCI4_TEI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI4_ERI, R_ICU_IELSR(SCI4_ERI - RA_IRQ_FIRST)); +#endif +#ifdef CONFIG_RA_SCI9_UART + putreg32(EVENT_SCI9_RXI, R_ICU_IELSR(SCI9_RXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI9_TXI, R_ICU_IELSR(SCI9_TXI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI9_TEI, R_ICU_IELSR(SCI9_TEI - RA_IRQ_FIRST)); + putreg32(EVENT_SCI9_ERI, R_ICU_IELSR(SCI9_ERI - RA_IRQ_FIRST)); +#endif +} + +/**************************************************************************** + * Name: ra_clear_ir + * + * Description: + * Clear the latched interrupt status flag (IELSR.IR) for the ICU slot + * backing the given IRQ number. + * + ****************************************************************************/ + +void ra_clear_ir(int irq) +{ + uint32_t slot = irq - RA_IRQ_FIRST; + + modifyreg32(R_ICU_IELSR(slot), R_ICU_IELSR_IR, 0); + getreg32(R_ICU_IELSR(slot)); +} diff --git a/arch/arm/src/ra8m1/ra_icu.h b/arch/arm/src/ra8m1/ra_icu.h new file mode 100644 index 00000000000..503d2d82773 --- /dev/null +++ b/arch/arm/src/ra8m1/ra_icu.h @@ -0,0 +1,37 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_icu.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_RA_ICU_H +#define __ARCH_ARM_SRC_RA8M1_RA_ICU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/ra8m1_icu.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +void ra_attach_icu(void); +void ra_clear_ir(int irq); + +#endif diff --git a/arch/arm/src/ra8m1/ra_irq.c b/arch/arm/src/ra8m1/ra_irq.c new file mode 100644 index 00000000000..9a555585bd2 --- /dev/null +++ b/arch/arm/src/ra8m1/ra_irq.c @@ -0,0 +1,387 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "nvic.h" +#include "arm_internal.h" +#include "ra_icu.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ + NVIC_SYSH_PRIORITY_DEFAULT) + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ra_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +/**************************************************************************** + * Name: ra_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +static inline void ra_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void ra_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", getreg32( + NVIC_INTCTRL), getreg32(NVIC_VECTAB)); + irqinfo(" IRQ ENABLE: %08x %08x %08x\n", getreg32( + NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE), + getreg32(NVIC_IRQ64_95_ENABLE)); + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", getreg32( + NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", getreg32( + NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32( + NVIC_IRQ20_23_PRIORITY), getreg32( + NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32( + NVIC_IRQ36_39_PRIORITY), getreg32( + NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), getreg32( + NVIC_IRQ52_55_PRIORITY), getreg32( + NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY)); + irqinfo(" %08x\n", getreg32(NVIC_IRQ64_67_PRIORITY)); + + leave_critical_section(flags); +} + +#else +# define ra_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: ra_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int ra_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + int n; + + DEBUGASSERT(irq >= RA_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= RA_IRQ_FIRST) + { + n = irq - RA_IRQ_FIRST; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; + *bit = (uint32_t)1 << (n & 0x1f); + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == RA_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == RA_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == RA_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == RA_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regaddr; + + int num_priority_registers; + int i; + + /* Disable all interrupts */ + + for (i = 0; i < NR_IRQS - RA_IRQ_FIRST; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* The NVIC ICTR register (bits 0-4) holds the number of interrupt + * lines that the NVIC supports: + * + * 0 -> 32 interrupt lines, 8 priority registers + * 1 -> 64 " " " ", 16 priority registers + * 2 -> 96 " " " ", 32 priority registers + * ... + */ + + num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; + + /* Now set all of the interrupt lines to the default priority */ + + regaddr = NVIC_IRQ0_3_PRIORITY; + while (num_priority_registers--) + { + putreg32(DEFPRIORITY32, regaddr); + regaddr += 4; + } + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(RA_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(RA_IRQ_HARDFAULT, arm_hardfault, NULL); + + /* Attach the ICU events to the IRQ vector table */ + + ra_attach_icu(); + + ra_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + + ra_dumpnvic("initial", RA_IRQ_FIRST + 32); + + /* And finally, enable interrupts */ + + up_irq_enable(); +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (ra_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= RA_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (ra_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= RA_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } +} + +/**************************************************************************** + * Name: arm_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT( + irq >= RA_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < RA_IRQ_FIRST) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= RA_IRQ_FIRST; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + ra_dumpnvic("prioritize", irq); + return OK; +} + +#endif diff --git a/arch/arm/src/ra8m1/ra_lowputc.c b/arch/arm/src/ra8m1/ra_lowputc.c new file mode 100644 index 00000000000..67b080737de --- /dev/null +++ b/arch/arm/src/ra8m1/ra_lowputc.c @@ -0,0 +1,419 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "ra_clockconfig.h" +#include "ra_lowputc.h" +#include "ra_gpio.h" +#include "hardware/ra8m1_sci.h" +#include "hardware/ra8m1_mstp.h" +#include "hardware/ra8m1_system.h" + +/* The board.h file may redefine pin configurations defined in ra_pinmap.h */ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RA8M1 only implements SCI_B0-SCI_B4 and SCI_B9 (SCI_B5-8 do not exist). */ + +/* Is there a serial console? It could be on SCI0-4 or 9 */ + +#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI0_UART) +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI1_UART) +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI2_UART) +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#elif defined(CONFIG_SCI3_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI3_UART) +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#elif defined(CONFIG_SCI4_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI4_UART) +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#elif defined(CONFIG_SCI9_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI9_UART) +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#else +#ifndef CONFIG_NO_SERIAL_CONSOLE +#warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting" +#endif + +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#undef HAVE_CONSOLE +#endif + +#if defined(HAVE_CONSOLE) + +/* Select SCI_B parameters for the selected console */ + +# if defined(CONFIG_SCI0_SERIAL_CONSOLE) +# define RA_CONSOLE_BASE R_SCI_B0_BASE +# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB31 +# define RA_CONSOLE_BAUD CONFIG_SCI0_BAUD +# define RA_CONSOLE_BITS CONFIG_SCI0_BITS +# define RA_CONSOLE_PARITY CONFIG_SCI0_PARITY +# define RA_CONSOLE_2STOP CONFIG_SCI0_2STOP +# elif defined(CONFIG_SCI1_SERIAL_CONSOLE) +# define RA_CONSOLE_BASE R_SCI_B1_BASE +# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB30 +# define RA_CONSOLE_BAUD CONFIG_SCI1_BAUD +# define RA_CONSOLE_BITS CONFIG_SCI1_BITS +# define RA_CONSOLE_PARITY CONFIG_SCI1_PARITY +# define RA_CONSOLE_2STOP CONFIG_SCI1_2STOP +# elif defined(CONFIG_SCI2_SERIAL_CONSOLE) +# define RA_CONSOLE_BASE R_SCI_B2_BASE +# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB29 +# define RA_CONSOLE_BAUD CONFIG_SCI2_BAUD +# define RA_CONSOLE_BITS CONFIG_SCI2_BITS +# define RA_CONSOLE_PARITY CONFIG_SCI2_PARITY +# define RA_CONSOLE_2STOP CONFIG_SCI2_2STOP +# elif defined(CONFIG_SCI3_SERIAL_CONSOLE) +# define RA_CONSOLE_BASE R_SCI_B3_BASE +# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB28 +# define RA_CONSOLE_BAUD CONFIG_SCI3_BAUD +# define RA_CONSOLE_BITS CONFIG_SCI3_BITS +# define RA_CONSOLE_PARITY CONFIG_SCI3_PARITY +# define RA_CONSOLE_2STOP CONFIG_SCI3_2STOP +# elif defined(CONFIG_SCI4_SERIAL_CONSOLE) +# define RA_CONSOLE_BASE R_SCI_B4_BASE +# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB27 +# define RA_CONSOLE_BAUD CONFIG_SCI4_BAUD +# define RA_CONSOLE_BITS CONFIG_SCI4_BITS +# define RA_CONSOLE_PARITY CONFIG_SCI4_PARITY +# define RA_CONSOLE_2STOP CONFIG_SCI4_2STOP +# elif defined(CONFIG_SCI9_SERIAL_CONSOLE) +# define RA_CONSOLE_BASE R_SCI_B9_BASE +# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_MSTPB22 +# define RA_CONSOLE_BAUD CONFIG_SCI9_BAUD +# define RA_CONSOLE_BITS CONFIG_SCI9_BITS +# define RA_CONSOLE_PARITY CONFIG_SCI9_PARITY +# define RA_CONSOLE_2STOP CONFIG_SCI9_2STOP +# else +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +# endif +# endif + +/* Configuration ************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ +#ifdef HAVE_CONSOLE +static spinlock_t g_ra_lowputc_lock = SP_UNLOCKED; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void arm_lowputc(char ch) +{ +#ifdef HAVE_CONSOLE + irqstate_t flags; + + for (; ; ) + { + while ((getreg32(RA_CONSOLE_BASE + R_SCI_B_CSR_OFFSET) + & R_SCI_B_CSR_TEND) == 0) + { + } + + /* Disable interrupts so that the test and the transmission are + * atomic. + */ + + flags = spin_lock_irqsave(&g_ra_lowputc_lock); + if ((getreg32(RA_CONSOLE_BASE + R_SCI_B_CSR_OFFSET) + & R_SCI_B_CSR_TEND) == R_SCI_B_CSR_TEND) + { + /* Send the character */ + + putreg32((uint32_t)ch & R_SCI_B_TDR_TDAT_MASK, + RA_CONSOLE_BASE + R_SCI_B_TDR_OFFSET); + + spin_unlock_irqrestore(&g_ra_lowputc_lock, flags); + return; + } + + spin_unlock_irqrestore(&g_ra_lowputc_lock, flags); + } +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +void up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + arm_lowputc(ch); +#endif +} + +/**************************************************************************** + * Name: ra_sci_baud_ccr2 + * + * Description: + * See ra_lowputc.h. Table 31.7 gives, for asynchronous mode, + * + * N = TCLK / (D x 2^(2n-1) x B) - 1 + * + * where N is BRR, n is CCR2.CKS (TCLK divided by 1, 4, 16 or 64) and D + * is 64, 32, 16 or 12 depending on BGDM/ABCS/ABCSE. Try every D and n + * and keep the pair with the smallest baud rate error. + * + ****************************************************************************/ + +uint32_t ra_sci_baud_ccr2(uint32_t sciclk_hz, uint32_t baud) +{ + static const uint8_t div_baud[4] = + { + 12, 16, 32, 64 + }; + + int64_t brr = 0; + uint32_t reg_brr = 0; + uint32_t best_brr = 0; + uint32_t actual_baudrate = 0; + int64_t error = 0; + int64_t min_error = INT64_MAX; + uint8_t best_n = 0; + uint8_t best_i = 0; + uint32_t regval = 0; + + for (uint8_t i = 0; i < 4; i++) + { + for (uint8_t n = 0; n < 4; n++) + { + uint32_t div_n = (n == 0) ? 1 : (1U << (2 * n - 1)); + uint32_t multiplier = (n == 0) ? 2UL : 1UL; + + /* The products below reach several billion (for example 64 x 32 + * x 3000000 baud), so they must be 64-bit. + */ + + brr = (int64_t)(((uint64_t)sciclk_hz * 100UL * multiplier) / + ((uint64_t)div_baud[i] * div_n * baud)) - 100; + + /* A negative value means this setting can not reach the requested + * baud rate; use its fastest one (N = 0), which is the closest. + */ + + if (brr < 0) + { + brr = 0; + } + + reg_brr = (uint32_t)((brr + 50) / 100); + + if (reg_brr > 255) + { + continue; + } + + actual_baudrate = (sciclk_hz * multiplier) / + (div_baud[i] * div_n * (reg_brr + 1)); + + /* Error in thousandths of a percent. The baud rate difference + * times 100000 does not fit in 32 bits, so it is 64-bit and + * signed. + */ + + error = (((int64_t)actual_baudrate - (int64_t)baud) * 100000) / + (int64_t)baud; + + /* Store the best values if we find a new minimum error */ + + if (llabs(error) < llabs(min_error)) + { + min_error = error; + best_n = n; + best_i = i; + best_brr = reg_brr; + } + } + } + + switch (best_i) + { + case 0: + regval = R_SCI_B_CCR2_ABCSE; + break; + + case 1: + regval = R_SCI_B_CCR2_BGDM | R_SCI_B_CCR2_ABCS; + break; + + case 2: + regval = R_SCI_B_CCR2_BGDM; + break; + + default: + break; + } + + regval |= (best_brr << R_SCI_B_CCR2_BRR_SHIFT); + regval |= ((uint32_t)best_n << R_SCI_B_CCR2_CKS_SHIFT); + + return regval; +} + +/**************************************************************************** + * Name: ra_lowsetup + * + * Description: + * This performs basic initialization of the USART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void ra_lowsetup(void) +{ +#ifdef HAVE_CONSOLE + uint32_t regval; + + /* Configure only the console's own pins. This must key off which + * channel is the console (CONFIG_SCIn_SERIAL_CONSOLE), not off which + * SCI_B drivers are built in (CONFIG_RA_SCIn_UART): several channels + * may be enabled at once, but ra_lowsetup only ever brings up the one + * that is the console. + */ + +#if defined(CONFIG_SCI0_SERIAL_CONSOLE) + ra_configgpio(GPIO_SCI0_RX); + ra_configgpio(GPIO_SCI0_TX); +#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) + ra_configgpio(GPIO_SCI1_RX); + ra_configgpio(GPIO_SCI1_TX); +#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) + ra_configgpio(GPIO_SCI2_RX); + ra_configgpio(GPIO_SCI2_TX); +#elif defined(CONFIG_SCI3_SERIAL_CONSOLE) + ra_configgpio(GPIO_SCI3_RX); + ra_configgpio(GPIO_SCI3_TX); +#elif defined(CONFIG_SCI4_SERIAL_CONSOLE) + ra_configgpio(GPIO_SCI4_RX); + ra_configgpio(GPIO_SCI4_TX); +#elif defined(CONFIG_SCI9_SERIAL_CONSOLE) + ra_configgpio(GPIO_SCI9_RX); + ra_configgpio(GPIO_SCI9_TX); +#endif + + putreg16((R_SYSTEM_PRCR_S_PRKEY_V0XA5 | R_SYSTEM_PRCR_S_PRC1), + R_SYSTEM_PRCR_S); + modifyreg32(R_MSTP_MSTPCRB, RA_CONSOLE_MTSP, 0); + putreg16(R_SYSTEM_PRCR_S_PRKEY_V0XA5, R_SYSTEM_PRCR_S); + + /* Disable the channel while it is configured */ + + regval = 0; + putreg32(regval, RA_CONSOLE_BASE + R_SCI_B_CCR0_OFFSET); + + /* Baud rate generator: ra_clockconfig() has already set SCICLK, which + * is the baud rate generator's input clock (CCR3.BPEN is 0 after + * reset). Load the console baud rate, with the remaining CCR2 fields + * chosen for the smallest error. + */ + + regval = ra_sci_baud_ccr2(RA_SCICLK_FREQUENCY, RA_CONSOLE_BAUD); + putreg32(regval, RA_CONSOLE_BASE + R_SCI_B_CCR2_OFFSET); + + regval = (R_SCI_B_CCR0_TE | R_SCI_B_CCR0_RE); + putreg32(regval, RA_CONSOLE_BASE + R_SCI_B_CCR0_OFFSET); +#endif /* HAVE_CONSOLE */ +} diff --git a/arch/arm/src/ra8m1/ra_lowputc.h b/arch/arm/src/ra8m1/ra_lowputc.h new file mode 100644 index 00000000000..9eefafc60f1 --- /dev/null +++ b/arch/arm/src/ra8m1/ra_lowputc.h @@ -0,0 +1,109 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA8M1_RA_LOWPUTC_H +#define __ARCH_ARM_SRC_RA8M1_RA_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: ra_lowsetup + * + * Description: + * Called at the very beginning of _start. + * Performs low level initialization including setup of the console UART. + * This UART done early so that the serial console is available for + * debugging very early in the boot sequence. + * + ****************************************************************************/ + +void ra_lowsetup(void); + +/**************************************************************************** + * Name: ra_sci_baud_ccr2 + * + * Description: + * Find the SCI_B baud rate generator settings closest to the requested + * baud rate for the given SCICLK (the baud rate generator input clock, + * TCLK, when CCR3.BPEN is 0), following RA8M1 User's Manual Table 31.7 + * for asynchronous mode. + * + * Input Parameters: + * sciclk_hz - SCICLK frequency, in Hz. + * baud - Requested baud rate. + * + * Returned Value: + * The CCR2 bits to set: BGDM/ABCS/ABCSE, BRR and CKS. All other CCR2 + * bits are 0. + * + ****************************************************************************/ + +uint32_t ra_sci_baud_ccr2(uint32_t sciclk_hz, uint32_t baud); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_RA8M1_RA_LOWPUTC_H */ diff --git a/arch/arm/src/ra8m1/ra_option_setting.c b/arch/arm/src/ra8m1/ra_option_setting.c new file mode 100644 index 00000000000..4deec08bbd0 --- /dev/null +++ b/arch/arm/src/ra8m1/ra_option_setting.c @@ -0,0 +1,372 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_option_setting.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Option-setting memory images: OFS0, OFS1, OFS2 and OFS1_SEL. + * + * The MCU samples these flash words at reset to decide the watchdog start-up + * state, the voltage detection level, the HOCO, the debug behaviour, ECC and + * the DCDC converter. Each one is a const object in a section of its own; + * the linker script (ek_ra8m1.ld) places the section at the fixed hardware + * address and the flash tool programs it together with the image. The + * values come from the BOARD_OFS* options in the board's board.h. + * + * This is a flat (no TrustZone) image, so only the secure-region registers + * are used. OFS1 is the register at 0x0300_A200 (OFS1_SEC in the manual); + * OFS1_SEL is programmed as 0 so that every OFS1 field is taken from it. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "hardware/ra8m1_option_setting.h" +#include "ra_start.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Option values from board.h -> OFS0/OFS1/OFS2 fields. Every value the + * board gives is checked, so an invalid one fails to build. + * + * With auto start off, every field of that watchdog reads as the erased + * (all ones) value: register start mode, and the remaining fields are not + * used, so their BOARD_* options need not be defined. + */ + +#ifndef BOARD_OFS0_IWDT_AUTOSTART +# error "board.h must define BOARD_OFS0_IWDT_AUTOSTART" +#endif +#ifndef BOARD_OFS0_WDT_AUTOSTART +# error "board.h must define BOARD_OFS0_WDT_AUTOSTART" +#endif +#if !defined(BOARD_OFS1_VDSEL_MV) || !defined(BOARD_OFS1_LVD0_RESET) || \ + !defined(BOARD_OFS1_PVD0_LOWPOWER) || !defined(BOARD_OFS1_HOCO_START) || \ + !defined(BOARD_OFS1_SWDBG) || !defined(BOARD_OFS1_INITECC) +# error "board.h must define all the BOARD_OFS1_* options" +#endif +#ifndef BOARD_OFS2_DCDC +# error "board.h must define BOARD_OFS2_DCDC" +#endif +#ifndef BOARD_HOCO_FREQUENCY +# error "board.h must define BOARD_HOCO_FREQUENCY" +#endif + +/* OFS0: IWDT */ + +#define RA_OFS0_IWDT_ALL_ONES \ + (R_OFS0_IWDTSTRT | \ + (R_OFS0_IWDTTOPS_MASK << R_OFS0_IWDTTOPS_SHIFT) | \ + (R_OFS0_IWDTCKS_MASK << R_OFS0_IWDTCKS_SHIFT) | \ + (R_OFS0_IWDTRPES_MASK << R_OFS0_IWDTRPES_SHIFT) | \ + (R_OFS0_IWDTRPSS_MASK << R_OFS0_IWDTRPSS_SHIFT) | \ + R_OFS0_IWDTRSTIRQS | R_OFS0_IWDTSTPCTL) + +#if BOARD_OFS0_IWDT_AUTOSTART +# if !defined(BOARD_OFS0_IWDT_TIMEOUT) || !defined(BOARD_OFS0_IWDT_CLKDIV) || \ + !defined(BOARD_OFS0_IWDT_WINDOW_END) || \ + !defined(BOARD_OFS0_IWDT_WINDOW_START) || \ + !defined(BOARD_OFS0_IWDT_RESET) || \ + !defined(BOARD_OFS0_IWDT_STOP_IN_SLEEP) +# error "IWDT auto start: board.h must define all the BOARD_OFS0_IWDT_* options" +# endif + +# if BOARD_OFS0_IWDT_TIMEOUT == 128 +# define RA_OFS0_IWDT_TOPS_VAL R_OFS0_IWDTTOPS_128 +# elif BOARD_OFS0_IWDT_TIMEOUT == 512 +# define RA_OFS0_IWDT_TOPS_VAL R_OFS0_IWDTTOPS_512 +# elif BOARD_OFS0_IWDT_TIMEOUT == 1024 +# define RA_OFS0_IWDT_TOPS_VAL R_OFS0_IWDTTOPS_1024 +# elif BOARD_OFS0_IWDT_TIMEOUT == 2048 +# define RA_OFS0_IWDT_TOPS_VAL R_OFS0_IWDTTOPS_2048 +# else +# error "BOARD_OFS0_IWDT_TIMEOUT must be 128, 512, 1024 or 2048" +# endif + +# if BOARD_OFS0_IWDT_CLKDIV == 1 +# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV1 +# elif BOARD_OFS0_IWDT_CLKDIV == 16 +# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV16 +# elif BOARD_OFS0_IWDT_CLKDIV == 32 +# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV32 +# elif BOARD_OFS0_IWDT_CLKDIV == 64 +# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV64 +# elif BOARD_OFS0_IWDT_CLKDIV == 128 +# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV128 +# elif BOARD_OFS0_IWDT_CLKDIV == 256 +# define RA_OFS0_IWDT_CKS_VAL R_OFS0_IWDTCKS_DIV256 +# else +# error "BOARD_OFS0_IWDT_CLKDIV must be 1, 16, 32, 64, 128 or 256" +# endif + +# if BOARD_OFS0_IWDT_WINDOW_END == 75 +# define RA_OFS0_IWDT_RPES_VAL R_OFS0_IWDTRPES_75 +# elif BOARD_OFS0_IWDT_WINDOW_END == 50 +# define RA_OFS0_IWDT_RPES_VAL R_OFS0_IWDTRPES_50 +# elif BOARD_OFS0_IWDT_WINDOW_END == 25 +# define RA_OFS0_IWDT_RPES_VAL R_OFS0_IWDTRPES_25 +# elif BOARD_OFS0_IWDT_WINDOW_END == 0 +# define RA_OFS0_IWDT_RPES_VAL R_OFS0_IWDTRPES_0 +# else +# error "BOARD_OFS0_IWDT_WINDOW_END must be 75, 50, 25 or 0" +# endif + +# if BOARD_OFS0_IWDT_WINDOW_START == 25 +# define RA_OFS0_IWDT_RPSS_VAL R_OFS0_IWDTRPSS_25 +# elif BOARD_OFS0_IWDT_WINDOW_START == 50 +# define RA_OFS0_IWDT_RPSS_VAL R_OFS0_IWDTRPSS_50 +# elif BOARD_OFS0_IWDT_WINDOW_START == 75 +# define RA_OFS0_IWDT_RPSS_VAL R_OFS0_IWDTRPSS_75 +# elif BOARD_OFS0_IWDT_WINDOW_START == 100 +# define RA_OFS0_IWDT_RPSS_VAL R_OFS0_IWDTRPSS_100 +# else +# error "BOARD_OFS0_IWDT_WINDOW_START must be 25, 50, 75 or 100" +# endif + +# if BOARD_OFS0_IWDT_RESET +# define RA_OFS0_IWDT_RESET_BIT R_OFS0_IWDTRSTIRQS +# else +# define RA_OFS0_IWDT_RESET_BIT 0 +# endif +# if BOARD_OFS0_IWDT_STOP_IN_SLEEP +# define RA_OFS0_IWDT_STOP_BIT R_OFS0_IWDTSTPCTL +# else +# define RA_OFS0_IWDT_STOP_BIT 0 +# endif +# define RA_OFS0_IWDT \ + (RA_OFS0_IWDT_TOPS_VAL | RA_OFS0_IWDT_CKS_VAL | \ + RA_OFS0_IWDT_RPES_VAL | RA_OFS0_IWDT_RPSS_VAL | \ + RA_OFS0_IWDT_RESET_BIT | RA_OFS0_IWDT_STOP_BIT) +#else +# define RA_OFS0_IWDT RA_OFS0_IWDT_ALL_ONES +#endif + +/* OFS0: WDT */ + +#define RA_OFS0_WDT_ALL_ONES \ + (R_OFS0_WDT0STRT | \ + (R_OFS0_WDT0TOPS_MASK << R_OFS0_WDT0TOPS_SHIFT) | \ + (R_OFS0_WDT0CKS_MASK << R_OFS0_WDT0CKS_SHIFT) | \ + (R_OFS0_WDT0RPES_MASK << R_OFS0_WDT0RPES_SHIFT) | \ + (R_OFS0_WDT0RPSS_MASK << R_OFS0_WDT0RPSS_SHIFT) | \ + R_OFS0_WDT0RSTIRQS | R_OFS0_WDT0STPCTL) + +#if BOARD_OFS0_WDT_AUTOSTART +# if !defined(BOARD_OFS0_WDT_TIMEOUT) || !defined(BOARD_OFS0_WDT_CLKDIV) || \ + !defined(BOARD_OFS0_WDT_WINDOW_END) || \ + !defined(BOARD_OFS0_WDT_WINDOW_START) || \ + !defined(BOARD_OFS0_WDT_RESET) || \ + !defined(BOARD_OFS0_WDT_STOP_IN_SLEEP) +# error "WDT auto start: board.h must define all the BOARD_OFS0_WDT_* options" +# endif + +# if BOARD_OFS0_WDT_TIMEOUT == 1024 +# define RA_OFS0_WDT_TOPS_VAL R_OFS0_WDT0TOPS_1024 +# elif BOARD_OFS0_WDT_TIMEOUT == 4096 +# define RA_OFS0_WDT_TOPS_VAL R_OFS0_WDT0TOPS_4096 +# elif BOARD_OFS0_WDT_TIMEOUT == 8192 +# define RA_OFS0_WDT_TOPS_VAL R_OFS0_WDT0TOPS_8192 +# elif BOARD_OFS0_WDT_TIMEOUT == 16384 +# define RA_OFS0_WDT_TOPS_VAL R_OFS0_WDT0TOPS_16384 +# else +# error "BOARD_OFS0_WDT_TIMEOUT must be 1024, 4096, 8192 or 16384" +# endif + +# if BOARD_OFS0_WDT_CLKDIV == 4 +# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV4 +# elif BOARD_OFS0_WDT_CLKDIV == 64 +# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV64 +# elif BOARD_OFS0_WDT_CLKDIV == 128 +# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV128 +# elif BOARD_OFS0_WDT_CLKDIV == 512 +# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV512 +# elif BOARD_OFS0_WDT_CLKDIV == 2048 +# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV2048 +# elif BOARD_OFS0_WDT_CLKDIV == 8192 +# define RA_OFS0_WDT_CKS_VAL R_OFS0_WDT0CKS_DIV8192 +# else +# error "BOARD_OFS0_WDT_CLKDIV must be 4, 64, 128, 512, 2048 or 8192" +# endif + +# if BOARD_OFS0_WDT_WINDOW_END == 75 +# define RA_OFS0_WDT_RPES_VAL R_OFS0_WDT0RPES_75 +# elif BOARD_OFS0_WDT_WINDOW_END == 50 +# define RA_OFS0_WDT_RPES_VAL R_OFS0_WDT0RPES_50 +# elif BOARD_OFS0_WDT_WINDOW_END == 25 +# define RA_OFS0_WDT_RPES_VAL R_OFS0_WDT0RPES_25 +# elif BOARD_OFS0_WDT_WINDOW_END == 0 +# define RA_OFS0_WDT_RPES_VAL R_OFS0_WDT0RPES_0 +# else +# error "BOARD_OFS0_WDT_WINDOW_END must be 75, 50, 25 or 0" +# endif + +# if BOARD_OFS0_WDT_WINDOW_START == 25 +# define RA_OFS0_WDT_RPSS_VAL R_OFS0_WDT0RPSS_25 +# elif BOARD_OFS0_WDT_WINDOW_START == 50 +# define RA_OFS0_WDT_RPSS_VAL R_OFS0_WDT0RPSS_50 +# elif BOARD_OFS0_WDT_WINDOW_START == 75 +# define RA_OFS0_WDT_RPSS_VAL R_OFS0_WDT0RPSS_75 +# elif BOARD_OFS0_WDT_WINDOW_START == 100 +# define RA_OFS0_WDT_RPSS_VAL R_OFS0_WDT0RPSS_100 +# else +# error "BOARD_OFS0_WDT_WINDOW_START must be 25, 50, 75 or 100" +# endif + +# if BOARD_OFS0_WDT_RESET +# define RA_OFS0_WDT_RESET_BIT R_OFS0_WDT0RSTIRQS +# else +# define RA_OFS0_WDT_RESET_BIT 0 +# endif +# if BOARD_OFS0_WDT_STOP_IN_SLEEP +# define RA_OFS0_WDT_STOP_BIT R_OFS0_WDT0STPCTL +# else +# define RA_OFS0_WDT_STOP_BIT 0 +# endif +# define RA_OFS0_WDT \ + (RA_OFS0_WDT_TOPS_VAL | RA_OFS0_WDT_CKS_VAL | \ + RA_OFS0_WDT_RPES_VAL | RA_OFS0_WDT_RPSS_VAL | \ + RA_OFS0_WDT_RESET_BIT | RA_OFS0_WDT_STOP_BIT) +#else +# define RA_OFS0_WDT RA_OFS0_WDT_ALL_ONES +#endif + +#define RA_OFS0 (R_OFS0_RESERVED | RA_OFS0_IWDT | RA_OFS0_WDT) + +/* OFS1. PVDAS, PVDLPSEL, HOCOEN and SWDBG are active low: the bit is set + * when the feature is off. + */ + +#if BOARD_OFS1_VDSEL_MV == 2850 +# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_2_85V +#elif BOARD_OFS1_VDSEL_MV == 2580 +# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_2_58V +#elif BOARD_OFS1_VDSEL_MV == 2150 +# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_2_15V +#elif BOARD_OFS1_VDSEL_MV == 2000 +# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_2_00V +#elif BOARD_OFS1_VDSEL_MV == 1900 +# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_1_90V +#elif BOARD_OFS1_VDSEL_MV == 1800 +# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_1_80V +#elif BOARD_OFS1_VDSEL_MV == 1700 +# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_1_70V +#elif BOARD_OFS1_VDSEL_MV == 1600 +# define RA_OFS1_VDSEL_VAL R_OFS1_VDSEL_1_60V +#else +# error "BOARD_OFS1_VDSEL_MV must be 2850, 2580, 2150, 2000, 1900, 1800, 1700 or 1600" +#endif + +/* The HOCO frequency after reset is the same BOARD_HOCO_FREQUENCY that + * ra_clockconfig.h uses as the HOCO frequency. + */ + +#if BOARD_HOCO_FREQUENCY == 16000000 +# define RA_OFS1_HOCOFRQ_VAL R_OFS1_HOCOFRQ0_16MHZ +#elif BOARD_HOCO_FREQUENCY == 18000000 +# define RA_OFS1_HOCOFRQ_VAL R_OFS1_HOCOFRQ0_18MHZ +#elif BOARD_HOCO_FREQUENCY == 20000000 +# define RA_OFS1_HOCOFRQ_VAL R_OFS1_HOCOFRQ0_20MHZ +#elif BOARD_HOCO_FREQUENCY == 32000000 +# define RA_OFS1_HOCOFRQ_VAL R_OFS1_HOCOFRQ0_32MHZ +#elif BOARD_HOCO_FREQUENCY == 48000000 +# define RA_OFS1_HOCOFRQ_VAL R_OFS1_HOCOFRQ0_48MHZ +#else +# error "BOARD_HOCO_FREQUENCY must be 16, 18, 20, 32 or 48 MHz" +#endif + +#if BOARD_OFS1_LVD0_RESET +# define RA_OFS1_PVDAS_BIT 0 +#else +# define RA_OFS1_PVDAS_BIT R_OFS1_PVDAS +#endif + +#if BOARD_OFS1_PVD0_LOWPOWER +# define RA_OFS1_PVDLPSEL_BIT 0 +#else +# define RA_OFS1_PVDLPSEL_BIT R_OFS1_PVDLPSEL +#endif + +#if BOARD_OFS1_HOCO_START +# define RA_OFS1_HOCOEN_BIT 0 +#else +# define RA_OFS1_HOCOEN_BIT R_OFS1_HOCOEN +#endif + +#if BOARD_OFS1_SWDBG +# define RA_OFS1_SWDBG_BIT 0 +#else +# define RA_OFS1_SWDBG_BIT R_OFS1_SWDBG +#endif + +#if BOARD_OFS1_INITECC +# define RA_OFS1_INITECCEN_BIT R_OFS1_INITECCEN +#else +# define RA_OFS1_INITECCEN_BIT 0 +#endif + +#define RA_OFS1 \ + (R_OFS1_RESERVED | RA_OFS1_VDSEL_VAL | RA_OFS1_PVDAS_BIT | \ + RA_OFS1_PVDLPSEL_BIT | RA_OFS1_HOCOEN_BIT | RA_OFS1_HOCOFRQ_VAL | \ + RA_OFS1_SWDBG_BIT | RA_OFS1_INITECCEN_BIT) + +/* OFS2 */ + +#if BOARD_OFS2_DCDC +# define RA_OFS2 (R_OFS2_RESERVED | R_OFS2_DCDCEN) +#else +# define RA_OFS2 R_OFS2_RESERVED +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* "used" and the KEEP() in the linker script keep the sections themselves. + * The objects have external linkage and ra_start.c references them, because + * nothing else refers to this file and the linker would otherwise not pull + * it out of the library at all. + */ + +const uint32_t g_ra_option_setting_ofs0 + __attribute__((section(".option_setting_ofs0"), used)) = RA_OFS0; + +const uint32_t g_ra_option_setting_ofs2 + __attribute__((section(".option_setting_ofs2"), used)) = RA_OFS2; + +const uint32_t g_ra_option_setting_ofs1 + __attribute__((section(".option_setting_ofs1"), used)) = RA_OFS1; + +const uint32_t g_ra_option_setting_ofs1_sel + __attribute__((section(".option_setting_ofs1_sel"), used)) = + R_OFS1_SEL_ALL_SECURE; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/ra8m1/ra_serial.c b/arch/arm/src/ra8m1/ra_serial.c new file mode 100644 index 00000000000..4fca4ba5588 --- /dev/null +++ b/arch/arm/src/ra8m1/ra_serial.c @@ -0,0 +1,1200 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +#include +#endif + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" + +#include "hardware/ra8m1_sci.h" +#include "hardware/ra8m1_mstp.h" +#include "hardware/ra8m1_system.h" +#include "ra_clockconfig.h" +#include "ra_lowputc.h" +#include "ra_icu.h" +#include "ra_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RA8M1 only implements SCI_B0-SCI_B4 and SCI_B9 (SCI_B5-8 do not exist). */ + +/* Is there a serial console? */ + +#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI0_UART) +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI1_UART) +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI2_UART) +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#elif defined(CONFIG_SCI3_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI3_UART) +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#elif defined(CONFIG_SCI4_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI4_UART) +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#elif defined(CONFIG_SCI9_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI9_UART) +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#define HAVE_CONSOLE 1 +#else +#ifndef CONFIG_NO_SERIAL_CONSOLE +#warning "No valid CONFIG_SCIn_SERIAL_CONSOLE Setting" +#endif + +#undef CONFIG_SCI0_SERIAL_CONSOLE +#undef CONFIG_SCI1_SERIAL_CONSOLE +#undef CONFIG_SCI2_SERIAL_CONSOLE +#undef CONFIG_SCI3_SERIAL_CONSOLE +#undef CONFIG_SCI4_SERIAL_CONSOLE +#undef CONFIG_SCI9_SERIAL_CONSOLE +#undef HAVE_CONSOLE +#endif + +/* First pick the console and ttys0. */ + +#if defined(CONFIG_SCI0_SERIAL_CONSOLE) +#define CONSOLE_DEV g_uart0port /* UART0 is console */ +#define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +#define UART0_ASSIGNED 1 +#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) +#define CONSOLE_DEV g_uart1port /* UART1 is console */ +#define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +#define UART1_ASSIGNED 1 +#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) +#define CONSOLE_DEV g_uart2port /* UART2 is console */ +#define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +#define UART2_ASSIGNED 1 +#elif defined(CONFIG_SCI3_SERIAL_CONSOLE) +#define CONSOLE_DEV g_uart3port /* UART3 is console */ +#define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */ +#define UART3_ASSIGNED 1 +#elif defined(CONFIG_SCI4_SERIAL_CONSOLE) +#define CONSOLE_DEV g_uart4port /* UART4 is console */ +#define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ +#define UART4_ASSIGNED 1 +#elif defined(CONFIG_SCI9_SERIAL_CONSOLE) +#define CONSOLE_DEV g_uart9port /* UART9 is console */ +#define TTYS0_DEV g_uart9port /* UART9 is ttyS0 */ +#define UART9_ASSIGNED 1 +#else +#undef CONSOLE_DEV /* No console */ +#if defined(CONFIG_RA_SCI0_UART) +#define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +#define UART0_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI1_UART) +#define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +#define UART1_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI2_UART) +#define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +#define UART2_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI3_UART) +#define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */ +#define UART3_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI4_UART) +#define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ +#define UART4_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI9_UART) +#define TTYS0_DEV g_uart9port /* UART9 is ttyS0 */ +#define UART9_ASSIGNED 1 +#endif +#endif + +/* Pick ttys1. */ + +#if defined(CONFIG_RA_SCI0_UART) && !defined(UART0_ASSIGNED) +#define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +#define UART0_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI1_UART) && !defined(UART1_ASSIGNED) +#define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +#define UART1_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI2_UART) && !defined(UART2_ASSIGNED) +#define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +#define UART2_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI3_UART) && !defined(UART3_ASSIGNED) +#define TTYS1_DEV g_uart3port /* UART3 is ttyS1 */ +#define UART3_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI4_UART) && !defined(UART4_ASSIGNED) +#define TTYS1_DEV g_uart4port /* UART4 is ttyS1 */ +#define UART4_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI9_UART) && !defined(UART9_ASSIGNED) +#define TTYS1_DEV g_uart9port /* UART9 is ttyS1 */ +#define UART9_ASSIGNED 1 +#endif + +/* Pick ttys2. */ + +#if defined(CONFIG_RA_SCI0_UART) && !defined(UART0_ASSIGNED) +#define TTYS2_DEV g_uart0port /* UART0 is ttyS2 */ +#define UART0_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI1_UART) && !defined(UART1_ASSIGNED) +#define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */ +#define UART1_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI2_UART) && !defined(UART2_ASSIGNED) +#define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +#define UART2_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI3_UART) && !defined(UART3_ASSIGNED) +#define TTYS2_DEV g_uart3port /* UART3 is ttyS2 */ +#define UART3_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI4_UART) && !defined(UART4_ASSIGNED) +#define TTYS2_DEV g_uart4port /* UART4 is ttyS2 */ +#define UART4_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI9_UART) && !defined(UART9_ASSIGNED) +#define TTYS2_DEV g_uart9port /* UART9 is ttyS2 */ +#define UART9_ASSIGNED 1 +#endif + +/* Pick ttys3. */ + +#if defined(CONFIG_RA_SCI0_UART) && !defined(UART0_ASSIGNED) +#define TTYS3_DEV g_uart0port /* UART0 is ttyS3 */ +#define UART0_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI1_UART) && !defined(UART1_ASSIGNED) +#define TTYS3_DEV g_uart1port /* UART1 is ttyS3 */ +#define UART1_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI2_UART) && !defined(UART2_ASSIGNED) +#define TTYS3_DEV g_uart2port /* UART2 is ttyS3 */ +#define UART2_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI3_UART) && !defined(UART3_ASSIGNED) +#define TTYS3_DEV g_uart3port /* UART3 is ttyS3 */ +#define UART3_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI4_UART) && !defined(UART4_ASSIGNED) +#define TTYS3_DEV g_uart4port /* UART4 is ttyS3 */ +#define UART4_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI9_UART) && !defined(UART9_ASSIGNED) +#define TTYS3_DEV g_uart9port /* UART9 is ttyS3 */ +#define UART9_ASSIGNED 1 +#endif + +/* Pick ttys4. */ + +#if defined(CONFIG_RA_SCI0_UART) && !defined(UART0_ASSIGNED) +#define TTYS4_DEV g_uart0port /* UART0 is ttyS4 */ +#define UART0_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI1_UART) && !defined(UART1_ASSIGNED) +#define TTYS4_DEV g_uart1port /* UART1 is ttyS4 */ +#define UART1_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI2_UART) && !defined(UART2_ASSIGNED) +#define TTYS4_DEV g_uart2port /* UART2 is ttyS4 */ +#define UART2_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI3_UART) && !defined(UART3_ASSIGNED) +#define TTYS4_DEV g_uart3port /* UART3 is ttyS4 */ +#define UART3_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI4_UART) && !defined(UART4_ASSIGNED) +#define TTYS4_DEV g_uart4port /* UART4 is ttyS4 */ +#define UART4_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI9_UART) && !defined(UART9_ASSIGNED) +#define TTYS4_DEV g_uart9port /* UART9 is ttyS4 */ +#define UART9_ASSIGNED 1 +#endif + +/* Pick ttys5. */ + +#if defined(CONFIG_RA_SCI0_UART) && !defined(UART0_ASSIGNED) +#define TTYS5_DEV g_uart0port /* UART0 is ttyS5 */ +#define UART0_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI1_UART) && !defined(UART1_ASSIGNED) +#define TTYS5_DEV g_uart1port /* UART1 is ttyS5 */ +#define UART1_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI2_UART) && !defined(UART2_ASSIGNED) +#define TTYS5_DEV g_uart2port /* UART2 is ttyS5 */ +#define UART2_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI3_UART) && !defined(UART3_ASSIGNED) +#define TTYS5_DEV g_uart3port /* UART3 is ttyS5 */ +#define UART3_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI4_UART) && !defined(UART4_ASSIGNED) +#define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */ +#define UART4_ASSIGNED 1 +#elif defined(CONFIG_RA_SCI9_UART) && !defined(UART9_ASSIGNED) +#define TTYS5_DEV g_uart9port /* UART9 is ttyS5 */ +#define UART9_ASSIGNED 1 +#endif + +#define SCI_UART_ERR_BITS (R_SCI_B_CSR_PER | R_SCI_B_CSR_FER | \ + R_SCI_B_CSR_ORER) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_rxinterrupt(int irq, void *context, void *arg); +static int up_txinterrupt(int irq, void *context, void *arg); +static int up_erinterrupt(int irq, void *context, void *arg); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct up_dev_s +{ + const uint32_t scibase; /* Base address of SCI_B registers */ + uint32_t mstp; /* Module Stop Control Register bit */ + uint32_t baud; /* Configured baud */ + uint32_t sr; /* Saved status bits */ + uint8_t rxirq; /* IRQ associated with this SCI */ + uint8_t txirq; /* IRQ associated with this SCI */ + uint8_t teirq; /* IRQ associated with this SCI */ + uint8_t erirq; /* IRQ associated with this SCI */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7, 8 or 9) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; + +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#if defined(CONFIG_RA_SCI0_UART) +static char g_uart0rxbuffer[CONFIG_SCI0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_SCI0_TXBUFSIZE]; +#endif +#if defined(CONFIG_RA_SCI1_UART) +static char g_uart1rxbuffer[CONFIG_SCI1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_SCI1_TXBUFSIZE]; +#endif +#if defined(CONFIG_RA_SCI2_UART) +static char g_uart2rxbuffer[CONFIG_SCI2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_SCI2_TXBUFSIZE]; +#endif +#if defined(CONFIG_RA_SCI3_UART) +static char g_uart3rxbuffer[CONFIG_SCI3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_SCI3_TXBUFSIZE]; +#endif +#if defined(CONFIG_RA_SCI4_UART) +static char g_uart4rxbuffer[CONFIG_SCI4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_SCI4_TXBUFSIZE]; +#endif +#if defined(CONFIG_RA_SCI9_UART) +static char g_uart9rxbuffer[CONFIG_SCI9_RXBUFSIZE]; +static char g_uart9txbuffer[CONFIG_SCI9_TXBUFSIZE]; +#endif + +#if defined(CONFIG_RA_SCI0_UART) +static struct up_dev_s g_uart0priv = +{ + .scibase = R_SCI_B0_BASE, + .mstp = R_MSTP_MSTPCRB_MSTPB31, + .rxirq = SCI0_RXI, + .txirq = SCI0_TXI, + .teirq = SCI0_TEI, + .erirq = SCI0_ERI, + .baud = CONFIG_SCI0_BAUD, + .parity = CONFIG_SCI0_PARITY, + .bits = CONFIG_SCI0_BITS, + .stopbits2 = CONFIG_SCI0_2STOP, +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_SCI0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +#if defined(CONFIG_RA_SCI1_UART) +static struct up_dev_s g_uart1priv = +{ + .scibase = R_SCI_B1_BASE, + .mstp = R_MSTP_MSTPCRB_MSTPB30, + .rxirq = SCI1_RXI, + .txirq = SCI1_TXI, + .teirq = SCI1_TEI, + .erirq = SCI1_ERI, + .baud = CONFIG_SCI1_BAUD, + .parity = CONFIG_SCI1_PARITY, + .bits = CONFIG_SCI1_BITS, + .stopbits2 = CONFIG_SCI1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_SCI1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +#if defined(CONFIG_RA_SCI2_UART) +static struct up_dev_s g_uart2priv = +{ + .scibase = R_SCI_B2_BASE, + .mstp = R_MSTP_MSTPCRB_MSTPB29, + .rxirq = SCI2_RXI, + .txirq = SCI2_TXI, + .teirq = SCI2_TEI, + .erirq = SCI2_ERI, + .baud = CONFIG_SCI2_BAUD, + .parity = CONFIG_SCI2_PARITY, + .bits = CONFIG_SCI2_BITS, + .stopbits2 = CONFIG_SCI2_2STOP, +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_SCI2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +#if defined(CONFIG_RA_SCI3_UART) +static struct up_dev_s g_uart3priv = +{ + .scibase = R_SCI_B3_BASE, + .mstp = R_MSTP_MSTPCRB_MSTPB28, + .rxirq = SCI3_RXI, + .txirq = SCI3_TXI, + .teirq = SCI3_TEI, + .erirq = SCI3_ERI, + .baud = CONFIG_SCI3_BAUD, + .parity = CONFIG_SCI3_PARITY, + .bits = CONFIG_SCI3_BITS, + .stopbits2 = CONFIG_SCI3_2STOP, +}; + +static uart_dev_t g_uart3port = +{ + .recv = + { + .size = CONFIG_SCI3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +#if defined(CONFIG_RA_SCI4_UART) +static struct up_dev_s g_uart4priv = +{ + .scibase = R_SCI_B4_BASE, + .mstp = R_MSTP_MSTPCRB_MSTPB27, + .rxirq = SCI4_RXI, + .txirq = SCI4_TXI, + .teirq = SCI4_TEI, + .erirq = SCI4_ERI, + .baud = CONFIG_SCI4_BAUD, + .parity = CONFIG_SCI4_PARITY, + .bits = CONFIG_SCI4_BITS, + .stopbits2 = CONFIG_SCI4_2STOP, +}; + +static uart_dev_t g_uart4port = +{ + .recv = + { + .size = CONFIG_SCI4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart4priv, +}; +#endif + +#if defined(CONFIG_RA_SCI9_UART) +static struct up_dev_s g_uart9priv = +{ + .scibase = R_SCI_B9_BASE, + .mstp = R_MSTP_MSTPCRB_MSTPB22, + .rxirq = SCI9_RXI, + .txirq = SCI9_TXI, + .teirq = SCI9_TEI, + .erirq = SCI9_ERI, + .baud = CONFIG_SCI9_BAUD, + .parity = CONFIG_SCI9_PARITY, + .bits = CONFIG_SCI9_BITS, + .stopbits2 = CONFIG_SCI9_2STOP, +}; + +static uart_dev_t g_uart9port = +{ + .recv = + { + .size = CONFIG_SCI9_RXBUFSIZE, + .buffer = g_uart9rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI9_TXBUFSIZE, + .buffer = g_uart9txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart9priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->scibase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->scibase + offset); +} + +/**************************************************************************** + * Name: up_disableallints + ****************************************************************************/ + +static void up_disableallints(struct up_dev_s *priv, uint32_t *ie) +{ + irqstate_t flags; + uint32_t regval = 0; + + /* The following must be atomic */ + + flags = enter_critical_section(); + if (ie) + { + /* Return the current interrupt mask */ + + *ie = up_serialin(priv, R_SCI_B_CCR0_OFFSET); + } + + /* Disable all interrupts */ + + regval = up_serialin(priv, R_SCI_B_CCR0_OFFSET) & + ~(R_SCI_B_CCR0_TIE | R_SCI_B_CCR0_RIE); + up_serialout(priv, R_SCI_B_CCR0_OFFSET, regval); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_sci_config + * + * Description: + * Configure the SCI_B baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static void up_sci_config(struct up_dev_s *priv) +{ + uint32_t regval = 0; + + /* Disable the channel while it is (re)configured */ + + up_serialout(priv, R_SCI_B_CCR0_OFFSET, 0); + + /* Character length and stop bits live in CCR3.CHR/CCR3.STP. Unlike the + * legacy SCI, SCI_B has no separate SCMR.CHR1 -- CCR3.CHR is a single + * 2-bit field: 00/01 = 9-bit, 10 = 8-bit (reset value), 11 = 7-bit. + */ + + regval = up_serialin(priv, R_SCI_B_CCR3_OFFSET); + regval &= ~(R_SCI_B_CCR3_CHR_MASK << R_SCI_B_CCR3_CHR_SHIFT); + + if (priv->bits == 9) + { + regval |= R_SCI_B_CCR3_CHR_V00; + } + else if (priv->bits == 7) + { + regval |= R_SCI_B_CCR3_CHR_V11; + } + else + { + regval |= R_SCI_B_CCR3_CHR_V10; + } + + if (priv->stopbits2) + { + regval |= R_SCI_B_CCR3_STP; + } + else + { + regval &= ~R_SCI_B_CCR3_STP; + } + + regval &= ~(R_SCI_B_CCR3_MOD_MASK << R_SCI_B_CCR3_MOD_SHIFT); + regval |= R_SCI_B_CCR3_MOD_ASYNCHRONOUS; + up_serialout(priv, R_SCI_B_CCR3_OFFSET, regval); + + /* Parity lives in CCR1.PE/CCR1.PM */ + + regval = up_serialin(priv, R_SCI_B_CCR1_OFFSET); + regval &= ~(R_SCI_B_CCR1_PE | R_SCI_B_CCR1_PM); + + if (priv->parity > 0) + { + regval |= R_SCI_B_CCR1_PE; + if (priv->parity == 1) + { + regval |= R_SCI_B_CCR1_PM; + } + } + + up_serialout(priv, R_SCI_B_CCR1_OFFSET, regval); + + /* The baud rate generator lives in CCR2 (BGDM/ABCS/ABCSE, CKS and BRR). + * Its clock is SCICLK, not PCLKA, as long as the synchronizer bypass + * (CCR3.BPEN) stays off. ra_sci_baud_ccr2() picks the settings with the + * smallest error (RA8M1 User's Manual Table 31.7). + */ + + regval = up_serialin(priv, R_SCI_B_CCR2_OFFSET); + regval &= ~(R_SCI_B_CCR2_BGDM | R_SCI_B_CCR2_ABCS | R_SCI_B_CCR2_ABCSE | + (R_SCI_B_CCR2_BRR_MASK << R_SCI_B_CCR2_BRR_SHIFT) | + (R_SCI_B_CCR2_CKS_MASK << R_SCI_B_CCR2_CKS_SHIFT)); + regval |= ra_sci_baud_ccr2(RA_SCICLK_FREQUENCY, priv->baud); + up_serialout(priv, R_SCI_B_CCR2_OFFSET, regval); + + /* Re-enable the channel: transmit/receive plus their interrupts */ + + regval = (R_SCI_B_CCR0_TE | R_SCI_B_CCR0_RE | R_SCI_B_CCR0_TIE | + R_SCI_B_CCR0_RIE | R_SCI_B_CCR0_TEIE); + up_serialout(priv, R_SCI_B_CCR0_OFFSET, regval); +} + +static int up_setup(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Dispatch on the channel's own base address rather than a global + * #elif: several SCI_B channels may be enabled at once (see the + * ttyS0-ttyS5 assignment ladder above), so GPIO setup must be chosen + * per-device, not per-build. + */ + +#if defined(CONFIG_RA_SCI0_UART) + if (priv->scibase == R_SCI_B0_BASE) + { + ra_configgpio(GPIO_SCI0_RX); + ra_configgpio(GPIO_SCI0_TX); + } + +#endif +#if defined(CONFIG_RA_SCI1_UART) + if (priv->scibase == R_SCI_B1_BASE) + { + ra_configgpio(GPIO_SCI1_RX); + ra_configgpio(GPIO_SCI1_TX); + } + +#endif +#if defined(CONFIG_RA_SCI2_UART) + if (priv->scibase == R_SCI_B2_BASE) + { + ra_configgpio(GPIO_SCI2_RX); + ra_configgpio(GPIO_SCI2_TX); + } + +#endif +#if defined(CONFIG_RA_SCI3_UART) + if (priv->scibase == R_SCI_B3_BASE) + { + ra_configgpio(GPIO_SCI3_RX); + ra_configgpio(GPIO_SCI3_TX); + } + +#endif +#if defined(CONFIG_RA_SCI4_UART) + if (priv->scibase == R_SCI_B4_BASE) + { + ra_configgpio(GPIO_SCI4_RX); + ra_configgpio(GPIO_SCI4_TX); + } + +#endif +#if defined(CONFIG_RA_SCI9_UART) + if (priv->scibase == R_SCI_B9_BASE) + { + ra_configgpio(GPIO_SCI9_RX); + ra_configgpio(GPIO_SCI9_TX); + } + +#endif + + up_shutdown(dev); + + putreg16((R_SYSTEM_PRCR_S_PRKEY_V0XA5 | R_SYSTEM_PRCR_S_PRC1), + R_SYSTEM_PRCR_S); + modifyreg32(R_MSTP_MSTPCRB, priv->mstp, 0); + putreg16(R_SYSTEM_PRCR_S_PRKEY_V0XA5, R_SYSTEM_PRCR_S); + + up_sci_config(priv); + + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the SCI_B channel. + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Reset SCI_B control */ + + up_serialout(priv, R_SCI_B_CCR0_OFFSET, 0); + + /* Stop the channel's module clock */ + + putreg16((R_SYSTEM_PRCR_S_PRKEY_V0XA5 | R_SYSTEM_PRCR_S_PRC1), + R_SYSTEM_PRCR_S); + modifyreg32(R_MSTP_MSTPCRB, priv->mstp, 1); + putreg16(R_SYSTEM_PRCR_S_PRKEY_V0XA5, R_SYSTEM_PRCR_S); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the SCI to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->rxirq, up_rxinterrupt, dev); + if (ret < 0) + { + return ret; + } + + ret = irq_attach(priv->txirq, up_txinterrupt, dev); + if (ret < 0) + { + irq_detach(priv->rxirq); + return ret; + } + + ret = irq_attach(priv->erirq, up_erinterrupt, dev); + if (ret < 0) + { + irq_detach(priv->erirq); + return ret; + } + + up_enable_irq(priv->rxirq); + up_enable_irq(priv->txirq); + up_enable_irq(priv->erirq); + + return ret; +} + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + up_disable_irq(priv->rxirq); + up_disable_irq(priv->txirq); + up_disable_irq(priv->erirq); + irq_detach(priv->rxirq); + irq_detach(priv->txirq); + irq_detach(priv->erirq); +} + +/**************************************************************************** + * Name: up_rxinterrupt + * + * Description: + * This is the common SCI RX interrupt handler. + * + ****************************************************************************/ + +static int up_rxinterrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + + ra_clear_ir(irq); + uart_recvchars(dev); + return OK; +} + +/**************************************************************************** + * Name: up_txinterrupt + * + * Description: + * This is the common SCI TX interrupt handler. + * + ****************************************************************************/ + +static int up_txinterrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + + ra_clear_ir(irq); + uart_xmitchars(dev); + + return OK; +} + +/**************************************************************************** + * Name: up_erinterrupt + * + * Description: + * This is the common SCI Error interrupt handler. + * + ****************************************************************************/ + +static int up_erinterrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct up_dev_s *priv; + uint32_t regval = 0; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct up_dev_s *)dev->priv; + + /* Save for error reporting */ + + priv->sr = up_serialin(priv, R_SCI_B_CSR_OFFSET) & SCI_UART_ERR_BITS; + + /* Errors are cleared through the dedicated CFCLR register, not by + * writing CSR directly. + */ + + regval = R_SCI_B_CFCLR_ORERC | R_SCI_B_CFCLR_PERC | + R_SCI_B_CFCLR_FERC | R_SCI_B_CFCLR_ERSC; + up_serialout(priv, R_SCI_B_CFCLR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + int ret = -ENOTTY; + + return ret; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the SCI. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return the error information in the saved status */ + + *status = priv->sr; + priv->sr = 0; + + /* Then return the actual received byte. RDR.RDAT is 9 bits wide, but + * only the low 8 matter for byte-oriented (7/8-bit) transfers. + */ + + return (int)(up_serialin(priv, R_SCI_B_RDR_OFFSET) & + R_SCI_B_RDR_RDAT_MASK & 0xff); +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t regval; + + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + /* Enable the RX interrupt */ + + regval = up_serialin(priv, R_SCI_B_CCR0_OFFSET); + regval |= (R_SCI_B_CCR0_RIE); + up_serialout(priv, R_SCI_B_CCR0_OFFSET, regval); + +#endif + } + else + { + /* Disable the RX interrupt */ + + regval = up_serialin(priv, R_SCI_B_CCR0_OFFSET); + regval &= ~(R_SCI_B_CCR0_RIE); + up_serialout(priv, R_SCI_B_CCR0_OFFSET, regval); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive holding register is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + return (up_serialin(priv, + R_SCI_B_CSR_OFFSET) & R_SCI_B_CSR_RDRF) == + R_SCI_B_CSR_RDRF; +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the SCI + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + up_serialout(priv, R_SCI_B_TDR_OFFSET, + (uint32_t)ch & R_SCI_B_TDR_TDAT_MASK); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t regval; + + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + /* Enable the TX interrupt */ + + regval = up_serialin(priv, R_SCI_B_CCR0_OFFSET); + regval |= (R_SCI_B_CCR0_TIE); + up_serialout(priv, R_SCI_B_CCR0_OFFSET, regval); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); + +#endif + } + else + { + /* Disable the TX interrupt */ + + regval = up_serialin(priv, R_SCI_B_CCR0_OFFSET); + regval &= ~(R_SCI_B_CCR0_TIE); + up_serialout(priv, R_SCI_B_CCR0_OFFSET, regval); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the transmit holding register is empty (CSR.TDRE) + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + bool ret = + ((up_serialin(priv, + R_SCI_B_CSR_OFFSET) & R_SCI_B_CSR_TDRE) == + R_SCI_B_CSR_TDRE); + + return ret; +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the transmit holding and shift registers are empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + bool ret = + ((up_serialin(priv, + R_SCI_B_CSR_OFFSET) & R_SCI_B_CSR_TEND) == + R_SCI_B_CSR_TEND); + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_earlyserialinit + * + * Description: + * Performs the low level SCI initialization early in debug so that the + * serial console will be available during boot up. This must be called + * before arm_serialinit. + * + ****************************************************************************/ + +void arm_earlyserialinit(void) +{ + /* Disable all SCIS */ + +#ifdef TTYS0_DEV + up_disableallints(TTYS0_DEV.priv, NULL); +#endif +#ifdef TTYS1_DEV + up_disableallints(TTYS1_DEV.priv, NULL); +#endif +#ifdef TTYS2_DEV + up_disableallints(TTYS2_DEV.priv, NULL); +#endif +#ifdef TTYS3_DEV + up_disableallints(TTYS3_DEV.priv, NULL); +#endif +#ifdef TTYS4_DEV + up_disableallints(TTYS4_DEV.priv, NULL); +#endif +#ifdef TTYS5_DEV + up_disableallints(TTYS5_DEV.priv, NULL); +#endif + +#ifdef HAVE_CONSOLE + /* Configuration whichever one is the console */ + + CONSOLE_DEV.isconsole = true; + + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that arm_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_CONSOLE + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all SCIs */ + +#ifdef TTYS0_DEV + uart_register("/dev/ttyS0", &TTYS0_DEV); +#endif +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +#ifdef TTYS4_DEV + uart_register("/dev/ttyS4", &TTYS4_DEV); +#endif +#ifdef TTYS5_DEV + uart_register("/dev/ttyS5", &TTYS5_DEV); +#endif +} diff --git a/arch/arm/src/ra8m1/ra_start.c b/arch/arm/src/ra8m1/ra_start.c new file mode 100644 index 00000000000..f77472a8f9b --- /dev/null +++ b/arch/arm/src/ra8m1/ra_start.c @@ -0,0 +1,158 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include "arch/board/board.h" +#include "arm_internal.h" +#include "nvic.h" +#include "ra_clockconfig.h" +#include "ra_lowputc.h" +#include "ra_start.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HEAP_BASE ((uint32_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Nothing calls into ra_option_setting.c, so without a reference the linker + * would leave it out of the library and the option-setting words (OFS0, + * OFS1, OFS2, OFS1_SEL) would not be in the image. This table only exists + * to reference them; it is not used at run time. + */ + +static const uint32_t * const g_ra_option_setting_refs[] + __attribute__((used)) = +{ + &g_ra_option_setting_ofs0, + &g_ra_option_setting_ofs2, + &g_ra_option_setting_ofs1, + &g_ra_option_setting_ofs1_sel +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +const uintptr_t g_idle_topstack = HEAP_BASE; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the CONSOLE USART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) arm_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + + /* Configure the uart so that we can get debug output as soon as possible */ + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + { + *dest++ = 0; + } + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = (const uint32_t *)_eronly, dest = (uint32_t *)_sdata; + dest < (uint32_t *)_edata; + ) + { + *dest++ = *src++; + } + + ra_clockconfig(); + arm_fpuconfig(); + ra_lowsetup(); + showprogress('A'); + + /* Perform early serial initialization */ +#ifdef USE_EARLYSERIALINIT + arm_earlyserialinit(); +#endif + showprogress('B'); + + /* Initialize onboard resources */ + + ra_boardinitialize(); + + showprogress('C'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + + nx_start(); + + /* Shouldn't get here */ + + for (; ; ) + { + } +} diff --git a/arch/arm/src/ra8m1/ra_start.h b/arch/arm/src/ra8m1/ra_start.h new file mode 100644 index 00000000000..5c2faf8003f --- /dev/null +++ b/arch/arm/src/ra8m1/ra_start.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_start.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA_START_H +#define __ARCH_ARM_SRC_RA_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Option-setting memory words (ra_option_setting.c) */ + +extern const uint32_t g_ra_option_setting_ofs0; +extern const uint32_t g_ra_option_setting_ofs2; +extern const uint32_t g_ra_option_setting_ofs1; +extern const uint32_t g_ra_option_setting_ofs1_sel; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void ra_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_RA_START_H */ diff --git a/arch/arm/src/ra8m1/ra_timerisr.c b/arch/arm/src/ra8m1/ra_timerisr.c new file mode 100644 index 00000000000..e67377c9f3c --- /dev/null +++ b/arch/arm/src/ra8m1/ra_timerisr.c @@ -0,0 +1,130 @@ +/**************************************************************************** + * arch/arm/src/ra8m1/ra_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "arm_internal.h" +#include "chip.h" +#include "ra_clockconfig.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SysTick is clocked from the processor clock (CLKSOURCE is set below), + * which is CPUCLK: on RA8M1 that is not ICLK. + */ + +#define SYSTICK_CLOCK (RA_CPUCLK_FREQUENCY) + +#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#define SYSTICK_MAX 0x00ffffff +#if SYSTICK_RELOAD > SYSTICK_MAX +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: ra_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARMV8M_SYSTICK) && !defined(CONFIG_TIMER_ARCH) +static int ra_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + nxsched_process_timer(); + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(NVIC_SYSH12_15_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); + putreg32(regval, NVIC_SYSH12_15_PRIORITY); + + /* Make sure that the SYSTICK clock source is set correctly */ + +#if defined(CONFIG_ARMV8M_SYSTICK) && defined(CONFIG_TIMER_ARCH) + up_timer_set_lowerhalf(systick_initialize(true, SYSTICK_CLOCK, -1)); +#else + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + irq_attach(RA_IRQ_SYSTICK, (xcpt_t)ra_timerisr, NULL); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(RA_IRQ_SYSTICK); +#endif +}