| .. |
|
sam_adc.h
|
SAMA5 ADC+TC: Several updates/fixes from ongoing debug
|
2013-10-25 08:46:57 -06:00 |
|
sam_aic.h
|
SAMA5 interrupt handling logic
|
2013-07-22 11:54:39 -06:00 |
|
sam_aximx.h
|
SAMA5: Adapt clocking for different boot modes. New header files for AXI matrix, BSC, and SFR
|
2013-07-23 13:54:49 -06:00 |
|
sam_bsc.h
|
SAMA5: Adapt clocking for different boot modes. New header files for AXI matrix, BSC, and SFR
|
2013-07-23 13:54:49 -06:00 |
|
sam_can.h
|
SAMA5 CAN: Fix a data alignment problem
|
2013-11-03 10:41:24 -06:00 |
|
sam_dmac.h
|
SAMA5 HSMCI: Disable TX DMA. it is not reliable
|
2013-09-23 13:54:32 -06:00 |
|
sam_ehci.h
|
SAMA5/ECHI: Debug register access, add logic to determine transfer size, fix setting of control bit in token
|
2013-08-23 16:23:15 -06:00 |
|
sam_emac.h
|
SAMA5 GMAC and GMII support is code complete and ready for test
|
2013-09-27 13:12:04 -06:00 |
|
sam_gmac.h
|
SAMA5 GMAC: Various fixes from initial debug
|
2013-09-29 15:03:57 -06:00 |
|
sam_gpbr.h
|
SAMA5: Add GPBR register definitions
|
2013-10-19 10:22:21 -06:00 |
|
sam_hsmc.h
|
Add SAMA5 HSMC register definitions and logic to reconfigure the NOR FLASH
|
2013-07-29 10:56:21 -06:00 |
|
sam_hsmci.h
|
SAMA5 HSMCI: Disable TX DMA. it is not reliable
|
2013-09-23 13:54:32 -06:00 |
|
sam_isi.h
|
Minor changes while pondering a camera interface
|
2013-10-29 16:57:06 -06:00 |
|
sam_lcdc.h
|
SAMA5 LCDC: Correct how framebuffer memory was being mapped; Remove options to get framebuffer memory in various. Because of the mapping and aligment requirements, those options really cannot be supported
|
2013-10-13 13:08:05 -06:00 |
|
sam_matrix.h
|
SAMA5: Adapt clocking for different boot modes. New header files for AXI matrix, BSC, and SFR
|
2013-07-23 13:54:49 -06:00 |
|
sam_memorymap.h
|
SAMA5: Register definition file for camera interface
|
2013-10-26 08:25:58 -06:00 |
|
sam_mpddrc.h
|
Various changes to get SAMA5 SDRAM working. Marginally functional, but there is more to be done
|
2013-08-02 18:30:27 -06:00 |
|
sam_ohci.h
|
Add few more EHCI definitions
|
2013-08-18 13:01:13 -06:00 |
|
sam_pinmap.h
|
Add SAMA5D3 pin multiplexing definitions
|
2013-07-23 09:47:01 -06:00 |
|
sam_pio.h
|
Add SAMA5 GPIO configuration support
|
2013-07-22 20:59:47 -06:00 |
|
sam_pit.h
|
SAMA5 interrupt handling logic
|
2013-07-22 11:54:39 -06:00 |
|
sam_pmc.h
|
SAMA5: Barebones TWI driver implementation
|
2013-09-11 16:48:56 -06:00 |
|
sam_pwm.h
|
SAMA5 PWM: Add first cut at PWM driver
|
2013-11-06 10:55:12 -06:00 |
|
sam_rtc.h
|
SAMA5: Hook RTC into build system; Finish RTC alarm logic; Verify correct behavior of the basic RTC functionality
|
2013-10-19 10:41:20 -06:00 |
|
sam_sfr.h
|
SAMA5: EHCI now handles low- and full-speed connections by giving them to OHCI; OHCI now uses the work queue to defer interrupt processing; If both OHCI and EHCI are enabled, EHCI is the master of the UHPHS interrupt
|
2013-08-24 11:34:24 -06:00 |
|
sam_spi.h
|
SAMA5: Add basic SPI suppport (untested)
|
2013-08-04 11:08:20 -06:00 |
|
sam_ssc.h
|
SAMA5 SSC: Add SSC register definition header file
|
2013-10-30 16:15:51 -06:00 |
|
sam_tc.h
|
SAMA5: Hook in timer/counter logic so that it can driver periodic ADC sampling
|
2013-10-24 12:35:42 -06:00 |
|
sam_trng.h
|
SAMA5 TRNG: /dev/random appears to be functional
|
2013-10-20 12:08:39 -06:00 |
|
sam_twi.h
|
SAMA5 TWI: Misc improvements during debug (still not getting interupts)
|
2013-09-12 12:25:31 -06:00 |
|
sam_uart.h
|
Add support SAMA5 UART and serial driver
|
2013-07-22 19:16:37 -06:00 |
|
sam_udphs.h
|
SAMA5 UDPHS: Fix DMA channel vs. matching endpoint
|
2013-09-04 15:08:19 -06:00 |
|
sam_wdt.h
|
SAMA5: Hook RTC into build system; Finish RTC alarm logic; Verify correct behavior of the basic RTC functionality
|
2013-10-19 10:41:20 -06:00 |
|
sama5d3x_memorymap.h
|
SAMA5 Timer/counter library
|
2013-10-23 14:53:37 -06:00 |
|
sama5d3x_pinmap.h
|
Minor changes while pondering a camera interface
|
2013-10-29 16:57:06 -06:00 |
