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This patch adds a driver framework to control individual FPGA reset and clock gates. For FPGA devices, only the fabric (FIC0/FIC1/FIC3) clock and reset can be controlled, which affects the whole fabric / domain. This is problematic for obvious reasons. For MSS peripherals, clocks and reset are controlled individually for each peripheral via MSS memory mapped registers (MPFS_SYSREG). To get the same capability for FPGA peripherals, the same controller needs to be fabricated on the FPGA. However, the FPGA clock/reset controller is entirely user dependent, so a generic implementation is not possible. However, a generic driver is needed in order to build the current FPGA peripheral drivers. A stub implementation of the driver is provided in order to achieve this. Signed-off-by: Ville Juven <ville.juven@unikie.com> |
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| CMakeLists.txt | ||
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