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fc5c01dc70
The RWDT register offsets were incorrectly set to ESP32-S3 values instead of ESP32 values. This was introduced when the code was refactored from using the local NuttX header hardware/esp32_rtccntl.h (which had the correct offsets) to using the HAL library headers, and the offsets were moved inline into esp32_wdt.c with wrong values. Correct the offsets to match the actual ESP32 register layout from soc/rtc_cntl_reg.h (RTC_CNTL_WDTCONFIG0_REG at 0x8c, INT_ENA at 0x3c, etc). Without this fix, all RWDT operations (enable, configure timeout, enable interrupt, acknowledge interrupt, feed, write-protect) were targeting wrong memory addresses, rendering the RWDT completely non-functional. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com> |
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