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eaaba5e0a1
Wire the shared Ameba PWM driver (arch/arm/src/common/ameba/ameba_pwm.c) to RTL8721F (amebagreen2). The chip spreads PWM across four four-channel timers (TIM4..TIM7); this port drives TIM4 as the single time base with four compare channels, matching the shared driver's model. A new ameba_pwm_chip.h supplies the RTL8721F specifics taken from the SDK fwlib headers: TIM4 at the non-secure base 0x41000000, 40 MHz input clock, IRQ 11 (TIMER4_IRQ), crossbar pad-mux codes 111..114 (PINMUX_FUNCTION_TIM4_PWM0..3) and the distinct function/clock enable bits (APBPeriph_PWM0 / APBPeriph_PWM0_CLOCK). The board registers one timer at /dev/pwm0 with channel 1 on PB18 and channel 2 on PB19 for the pwm example; edit the table to match a board's wiring. The common driver is not touched. Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn> Assisted-by: Claude <noreply@anthropic.com> |
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