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e96fb6b118
Includes a Mini-UART NSH console for the 4B, tested on the 4GB RAM model. Part of an I2C driver which can only read, boiler-plate for a SPI driver, and a GPIO driver with limited pins. Some tools are present for automatically fetching the boot files and creating the `config.txt` file based on selected Kconfig options.
131 lines
6.6 KiB
C
131 lines
6.6 KiB
C
/****************************************************************************
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* arch/arm64/src/bcm2711/hardware/bcm2711_gpio.h
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*
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* Author: Matteo Golin <matteo.golin@gmail.com>
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_SRC_BCM2711_GPIO_H
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#define __ARCH_ARM64_SRC_BCM2711_GPIO_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "bcm2711_memmap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define BCM_GPIO_NUM 58 /* Number of GPIO pins */
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/* GPIO register offset definitions */
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#define BCM_GPIO_GPFSEL0_OFFSET 0x00 /* GPIO function select 0 */
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#define BCM_GPIO_GPFSEL1_OFFSET 0x04 /* GPIO function select 1 */
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#define BCM_GPIO_GPFSEL2_OFFSET 0x08 /* GPIO function select 2 */
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#define BCM_GPIO_GPFSEL3_OFFSET 0x0c /* GPIO function select 3 */
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#define BCM_GPIO_GPFSEL4_OFFSET 0x10 /* GPIO function select 4 */
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#define BCM_GPIO_GPFSEL5_OFFSET 0x14 /* GPIO function select 5 */
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#define BCM_GPIO_GPSET0_OFFSET 0x1c /* GPIO pin output set 0 */
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#define BCM_GPIO_GPSET1_OFFSET 0x20 /* GPIO pin output set 1 */
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#define BCM_GPIO_GPCLR0_OFFSET 0x28 /* GPIO pin output clear 0 */
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#define BCM_GPIO_GPCLR1_OFFSET 0x2c /* GPIO pin output clear 1 */
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#define BCM_GPIO_GPLEV0_OFFSET 0x34 /* GPIO pin level 0 */
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#define BCM_GPIO_GPLEV1_OFFSET 0x38 /* GPIO pin level 1 */
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#define BCM_GPIO_GPEDS0_OFFSET 0x40 /* GPIO pin event detect status 0 */
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#define BCM_GPIO_GPEDS1_OFFSET 0x44 /* GPIO pin event detect status 1 */
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#define BCM_GPIO_GPREN0_OFFSET 0x4c /* GPIO pin rise edge detect enable 0 */
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#define BCM_GPIO_GPREN1_OFFSET 0x50 /* GPIO pin rise edge detect enable 1 */
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#define BCM_GPIO_GPFEN0_OFFSET 0x58 /* GPIO pin fall edge detect enable 0 */
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#define BCM_GPIO_GPFEN1_OFFSET 0x5c /* GPIO pin fall edge detect enable 1 */
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#define BCM_GPIO_GPHEN0_OFFSET 0x64 /* GPIO pin high detect enable 0 */
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#define BCM_GPIO_GPHEN1_OFFSET 0x68 /* GPIO pin high detect enable 1 */
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#define BCM_GPIO_GPLEN0_OFFSET 0x70 /* GPIO pin low detect enable 0 */
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#define BCM_GPIO_GPLEN1_OFFSET 0x74 /* GPIO pin low detect enable 1 */
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#define BCM_GPIO_GPAREN0_OFFSET 0x7c /* GPIO pin async rise edge detect 0 */
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#define BCM_GPIO_GPAREN1_OFFSET 0x80 /* GPIO pin async rise edge detect 1 */
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#define BCM_GPIO_GPAFEN0_OFFSET 0x88 /* GPIO pin async fall edge detect 0 */
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#define BCM_GPIO_GPAFEN1_OFFSET 0x8c /* GPIO pin async fall edge detect 1 */
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#define BCM_GPIO_PUP_PDN_REG0_OFFSET 0xe4 /* GPIO pullup/down reg 0 */
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#define BCM_GPIO_PUP_PDN_REG1_OFFSET 0xe8 /* GPIO pullup/down reg 1 */
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#define BCM_GPIO_PUP_PDN_REG2_OFFSET 0xec /* GPIO pullup/down reg 2 */
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#define BCM_GPIO_PUP_PDN_REG3_OFFSET 0xf0 /* GPIO pullup/down reg 3 */
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/* GPIO register address definitions */
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#define _BCM_GP_REG(reg) (BCM_GPIO_BASEADDR + (reg))
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#define BCM_GPIO_GPFSEL0 _BCM_GP_REG(BCM_GPIO_GPFSEL0_OFFSET)
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#define BCM_GPIO_GPFSEL1 _BCM_GP_REG(BCM_GPIO_GPFSEL1_OFFSET)
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#define BCM_GPIO_GPFSEL2 _BCM_GP_REG(BCM_GPIO_GPFSEL2_OFFSET)
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#define BCM_GPIO_GPFSEL3 _BCM_GP_REG(BCM_GPIO_GPFSEL3_OFFSET)
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#define BCM_GPIO_GPFSEL4 _BCM_GP_REG(BCM_GPIO_GPFSEL4_OFFSET)
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#define BCM_GPIO_GPFSEL5 _BCM_GP_REG(BCM_GPIO_GPFSEL5_OFFSET)
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#define BCM_GPIO_GPSET0 _BCM_GP_REG(BCM_GPIO_GPSET0_OFFSET)
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#define BCM_GPIO_GPSET1 _BCM_GP_REG(BCM_GPIO_GPSET1_OFFSET)
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#define BCM_GPIO_GPCLR0 _BCM_GP_REG(BCM_GPIO_GPCLR0_OFFSET)
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#define BCM_GPIO_GPCLR1 _BCM_GP_REG(BCM_GPIO_GPCLR1_OFFSET)
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#define BCM_GPIO_GPLEV0 _BCM_GP_REG(BCM_GPIO_GPLEV0_OFFSET)
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#define BCM_GPIO_GPLEV1 _BCM_GP_REG(BCM_GPIO_GPLEV1_OFFSET)
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#define BCM_GPIO_GPEDS0 _BCM_GP_REG(BCM_GPIO_GPEDS0_OFFSET)
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#define BCM_GPIO_GPEDS1 _BCM_GP_REG(BCM_GPIO_GPEDS1_OFFSET)
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#define BCM_GPIO_GPREN0 _BCM_GP_REG(BCM_GPIO_GPREN0_OFFSET)
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#define BCM_GPIO_GPREN1 _BCM_GP_REG(BCM_GPIO_GPREN1_OFFSET)
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#define BCM_GPIO_GPFEN0 _BCM_GP_REG(BCM_GPIO_GPFEN0_OFFSET)
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#define BCM_GPIO_GPFEN1 _BCM_GP_REG(BCM_GPIO_GPFEN1_OFFSET)
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#define BCM_GPIO_GPHEN0 _BCM_GP_REG(BCM_GPIO_GPHEN0_OFFSET)
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#define BCM_GPIO_GPHEN1 _BCM_GP_REG(BCM_GPIO_GPHEN1_OFFSET)
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#define BCM_GPIO_GPLEN0 _BCM_GP_REG(BCM_GPIO_GPLEN0_OFFSET)
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#define BCM_GPIO_GPLEN1 _BCM_GP_REG(BCM_GPIO_GPLEN1_OFFSET)
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#define BCM_GPIO_GPAREN0 _BCM_GP_REG(BCM_GPIO_GPAREN0_OFFSET)
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#define BCM_GPIO_GPAREN1 _BCM_GP_REG(BCM_GPIO_GPAREN1_OFFSET)
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#define BCM_GPIO_GPAFEN0 _BCM_GP_REG(BCM_GPIO_GPAFEN0_OFFSET)
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#define BCM_GPIO_GPAFEN1 _BCM_GP_REG(BCM_GPIO_GPAFEN1_OFFSET)
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#define BCM_GPIO_PUP_PDN_CNTRL_REG0 _BCM_GP_REG(BCM_GPIO_PUP_PDN_REG0_OFFSET)
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#define BCM_GPIO_PUP_PDN_CNTRL_REG1 _BCM_GP_REG(BCM_GPIO_PUP_PDN_REG1_OFFSET)
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#define BCM_GPIO_PUP_PDN_CNTRL_REG2 _BCM_GP_REG(BCM_GPIO_PUP_PDN_REG2_OFFSET)
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#define BCM_GPIO_PUP_PDN_CNTRL_REG3 _BCM_GP_REG(BCM_GPIO_PUP_PDN_REG3_OFFSET)
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/* GPIO register bit definitions */
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#define BCM_GPIO_FS_IN 0x0 /* Pin is input */
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#define BCM_GPIO_FS_OUT 0x1 /* Pin is output */
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#define BCM_GPIO_FS_ALT0 0x4 /* Pin is alternate func 0 */
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#define BCM_GPIO_FS_ALT1 0x5 /* Pin is alternate func 1 */
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#define BCM_GPIO_FS_ALT2 0x6 /* Pin is alternate func 2 */
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#define BCM_GPIO_FS_ALT3 0x7 /* Pin is alternate func 3 */
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#define BCM_GPIO_FS_ALT4 0x3 /* Pin is alternate func 4 */
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#define BCM_GPIO_FS_ALT5 0x2 /* Pin is alternate func 5 */
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/* Any register that does not have specific bit masks listed here is omitted
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* because the control is done via a single bit, which corresponds bit N to
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* pin N. It is up to the programmer to read the data sheet to know whether
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* to use register 0, 1, ..., n.
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*/
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#define BCM_GPIO_NORES 0x0 /* No resistor */
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#define BCM_GPIO_PULLUP 0x1 /* Pull-up resistor */
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#define BCM_GPIO_PULLDOWN 0x2 /* Pull-down resistor */
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/* TODO: how to encode alternative function table to preproc definitions? */
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#endif // __ARCH_ARM64_SRC_BCM2711_GPIO_H
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