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Use per-instance aligned buffers for memory that SDMMC IDMA cannot access directly or that does not meet cache alignment requirements. Copy writes before IDMA and copy successful bounced reads in the waiting thread. Report the configured capacity through maxrequest. Keep a positive IDMA RAM allow-list and runtime setup validation. Invalidate only the actual DMA destination, prioritize errors over DATAEND, and stop data access before releasing buffer ownership. Reset an active data path on abort while restoring host bus settings; clear cancellation state and handle immediate/watchdog-start errors. This commit contains the STM32H7 driver and its Kconfig changes only. The preceding commit supplies the common SDIO/MMCSD functionality. Assisted-by: Codex:GPT-6 Signed-off-by: msli-dev <747640013@qq.com> |
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