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https://github.com/apache/nuttx.git
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e09048cc88
Correct duplicate "is is" word found in 181 files throughout the codebase. In most cases "is is" was changed to "is", but in contexts like "MCU is is sleep mode" it was corrected to "MCU in sleep mode". Also fixes a "the the" typo in net/inet/inet_sockif.c. This is a pure style/documentation fix that improves code readability. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
266 lines
9.2 KiB
C
266 lines
9.2 KiB
C
/****************************************************************************
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* boards/arm/sam34/sam4s-xplained-pro/include/board.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAM34_SAM4S_XPLAINED_PRO_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAM34_SAM4S_XPLAINED_PRO_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# ifdef CONFIG_SAM34_GPIO_IRQ
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# include <arch/irq.h>
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# endif
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* After power-on reset, the sam4s device is running on a 4MHz internal RC.
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* These definitions will configure clocking with MCK = 120MHz, PLLA = 240,
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* and CPU=120MHz.
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*/
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#define BOARD_32KOSC_FREQUENCY (32768)
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#define BOARD_SCLK_FREQUENCY (BOARD_32KOSC_FREQUENCY)
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#define BOARD_MAINOSC_FREQUENCY (12000000)
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/* Main oscillator register settings */
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#define BOARD_CKGR_MOR_MOSCXTST (63 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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#ifdef CONFIG_SAM34_UDP
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/* PLLA configuration:
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*
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* Source: 12MHz crystall at 12MHz
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* PLLmul: 10
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* PLLdiv: 1 (bypassed)
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* Fpll: (12MHz * 20) / 1 = 240MHz
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*/
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# define BOARD_CKGR_PLLAR_MUL (19 << PMC_CKGR_PLLAR_MUL_SHIFT)
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# define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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# define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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# define BOARD_PLLA_FREQUENCY (20*BOARD_MAINOSC_FREQUENCY) /* PLLA = 240Mhz */
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/* PMC master clock register settings */
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# define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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# define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
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# define BOARD_MCK_FREQUENCY (BOARD_PLLA_FREQUENCY/2) /* MCK = 120Mhz */
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# define BOARD_CPU_FREQUENCY (BOARD_PLLA_FREQUENCY/2) /* CPU = 120Mhz */
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/* USB UTMI PLL start-up time */
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# define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
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#else
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/* PLLA configuration:
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*
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* Source: 12MHz crystall at 12MHz
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* PLLmul: 10
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* PLLdiv: 1 (bypassed)
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* Fpll: (12MHz * 10) / 1 = 120MHz
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*/
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# define BOARD_CKGR_PLLAR_MUL (9 << PMC_CKGR_PLLAR_MUL_SHIFT)
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# define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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# define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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# define BOARD_PLLA_FREQUENCY (10*BOARD_MAINOSC_FREQUENCY) /* PLLA = 120Mhz */
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/* PMC master clock register settings */
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# define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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# define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
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# define BOARD_MCK_FREQUENCY (BOARD_PLLA_FREQUENCY) /* MCK = 120Mhz */
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# define BOARD_CPU_FREQUENCY (BOARD_PLLA_FREQUENCY) /* CPU = 120Mhz */
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#endif
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV+1)).
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*
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* MCI_SPEED = MCK / (2*(CLKDIV+1))
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* CLKDIV = MCI / MCI_SPEED / 2 - 1
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*/
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/* MCK = 120MHz, CLKDIV = 149, MCI_SPEED = 120MHz / 2 * (149+1) = 400 KHz */
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#define HSMCI_INIT_CLKDIV (149 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 120MHz, CLKDIV = 3, MCI_SPEED = 120MHz / 2 * (3+1) = 15 MHz */
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#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 120MHz, CLKDIV = 0, MCI_SPEED = 120MHz / 2 * (2+1) = 20 MHz */
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#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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#ifdef CONFIG_SAM34_UDP
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/* The PLL clock (USB_48M or UDPCK) is driven from the output of the PLL,
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* PLLACK. The PLL clock must be 48MHz. PLLACK can be divided down via the
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* PMC USB register to provide the PLL clock. So in order to use the USB
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* feature, the PLL output must be a multiple of 48MHz.
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*
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* PLLACK = 240MHz, USBDIV=4, USB_48M = 240 MHz / (4 + 1) = 48MHz
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* PLLACK = 192MHz, USBDIV=5, USB_48M = 192 MHz / (3 + 1) = 48MHz
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*/
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# define BOARD_PMC_USBS (0)
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# define BOARD_PMC_USBDIV (4 << PMC_USB_USBDIV_SHIFT)
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#endif
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/* FLASH wait states:
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*
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* DC Characteristics
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*
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* Parameter Min Typ Max
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* ---------------------- ----- ----- ----
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* Vddcore DC Supply Core 1.08V 1.2V 1.32V
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* Vvddio DC Supply I/Os 1.62V 3.3V 3.6V
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*
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* Wait Maximum
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* Vddcore Vvddio States Frequency (MHz)
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* ------- ---------- ------ ---------------
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* 1.08V 1.62-3.6V 0 16
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* " " " "-" " 1 33
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* " " " "-" " 2 50
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* " " " "-" " 3 67
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* " " " "-" " 4 84
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* " " " "-" " 5 100
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* 1.08V 2.7-3.6V 0 20
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* " " " "-" " 1 40
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* " " " "-" " 2 60
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* " " " "-" " 3 80
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* " " " "-" " 4 100
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* 1.2V 1.62-3.6V 0 17
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* " " " "-" " 1 34
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* " " " "-" " 2 52
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* " " " "-" " 3 69
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* " " " "-" " 4 87
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* " " " "-" " 5 104
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* " " " "-" " 6 121
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* 1.2V 2.7-3.6V 0 21
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* " " " "-" " 1 42
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* " " " "-" " 2 63
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* " " " "-" " 3 84
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* " " " "-" " 4 105
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* " " " "-" " 5 123 << SELECTION
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*/
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#define BOARD_FWS 5
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/* LED definitions **********************************************************/
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/* There are two LEDs on board the SAM4S Xplained Pro board, One of these
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* can be controlled by software in the SAM4S:
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*
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* LED GPIO
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* ---------------- -----
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* D301 Yellow LED PC23
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*
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* Both can be illuminated by driving the GPIO output to ground (low).
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_D301 0
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_D301_BIT (1 << BOARD_D301)
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined.
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* In that case, the usage by the board port is defined in
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* include/board.h and src/up_leds.c.
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* The LEDs are used to encode OS-related events as follows:
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*
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* SYMBOL Val Meaning LED state
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* D301
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* ----------------------- --- ----------------------- --------------
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF */
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#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */
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#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */
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#define LED_STACKCREATED 1 /* Idle stack created ON */
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#define LED_INIRQ 2 /* In an interrupt OFF */
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#define LED_SIGNAL 2 /* In a signal handler OFF */
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#define LED_ASSERTION 4 /* An assertion failed No change */
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#define LED_PANIC 3 /* The system has crashed Flash @ 250ms */
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#define LED_IDLE 4 /* MCU is in sleep mode Not used */
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#define LED_D301_OFF true /* GPIO high for OFF */
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#define LED_D301_ON false /* GPIO low for ON */
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/* Thus if D301 is statically on, NuttX has successfully booted and is,
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* apparently, running normally.
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*/
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/* Button definitions *******************************************************/
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/* Mechanical buttons:
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*
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* The SAM4S Xplained Pro has two mechanical buttons.
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* One button is the RESET button connected to the SAM4S reset line and the
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* other is a generic user configurable button labeled SW0.
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* When a button is pressed it will drive the I/O line to GND.
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*
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* PA2 SW0
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*/
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#define BUTTON_SW0 0
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#define NUM_BUTTONS 1
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#define BUTTON_SW0_BIT (1 << BUTTON_SW0)
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/* NAND *********************************************************************/
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#define GPIO_SMC_RB (GPIO_INPUT | GPIO_SMC_NWAIT)
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/* Address for transferring command bytes to the nandflash, CLE A22 */
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#define BOARD_NCS0_NAND_CMDADDR 0x60400000
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/* Address for transferring address bytes to the nandflash, ALE A21 */
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#define BOARD_NCS0_NAND_ADDRADDR 0x60200000
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/* Address for transferring data bytes to the nandflash. */
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#define BOARD_NCS0_NAND_DATAADDR 0x60000000
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#endif /* __BOARDS_ARM_SAM34_SAM4S_XPLAINED_PRO_INCLUDE_BOARD_H */
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