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26ec938064
New RISC-V chip port for the GigaDevice GD32VW55x (Nuclei N307, Wi-Fi 6 and BLE 5.3 combo), with the GD32VW553K-START board. Core: - ECLIC interrupt controller, clock tree (160 MHz / 40 MHz HXTAL), 64-bit machine timer, serial (USART0/UART1/UART2) and RTC. - The instruction cache must be enabled in head.S or the UART drops characters under load; the mask ROM uses the first 0x200 bytes of SRAM so the image is linked at 0x20000200; the RTC needs PMU_CTL0.BKPWEN or the register writes are silently discarded. - The ECLIC only auto-clears the interrupt pending bit in hardware-vectored mode, so the trap dispatch clears it for edge-triggered sources or they re-fire forever (level-triggered peripherals clear their own). Peripherals: DMA (8 channels), GPIO + EXTI, SPI (optional DMA), I2C0/I2C1 (the new STM32-v2-style IP, not the GD32F4 one), ADC, PWM and input capture on the timers, both watchdogs, PROGMEM, TRNG and CRC. All use the standard NuttX lower-half interfaces and direct register access, not the vendor SPL. Three user LEDs (GPIOC), and a software reset through the Nuclei SysTimer. Internal flash: it is a system-in-package NOR die behind the real-time decryption block, so it is not programmed through the FMC registers -- the driver goes through the mask ROM API (rom_flash_*), the same way the vendor code does. PROGMEM can be mounted as LittleFS; the region sits below the Wi-Fi NVDS and must not overlap it. Wi-Fi (wlan0), station and softAP: - The MAC/PHY, RF and WPA supplicant are linked as prebuilt BSD-3 libraries. They are RTOS-agnostic, so the OS binding is a sys_* facade on NuttX primitives (gdwifi/wrapper_nuttx.c). Critical sections mask by ECLIC priority threshold, not by disabling every interrupt, or the MAC misses its microsecond deadlines. - The lwIP stack of the SDK is not used: the interface is a netdev_lowerhalf driver driven by the standard tools (wapi, ifup, renew, ping, dhcpd). EAPOL is handed to the supplicant instead of the IP stack. The lowerhalf "priority" field is the work-queue id (HPWORK/ LPWORK), not a task priority -- a wrong value makes receive() never run and every packet is dropped. - The vendor gives the radio 32 KB of shared SRAM as an extra heap; this needs CONFIG_MM_REGIONS >= 2 or the kernel silently drops the region. - The DHCP client needs CONFIG_NETUTILS_DHCPC_BOOTP_FLAGS=0x8000 so the server answers the OFFER by broadcast. - softAP (wapi master mode -> wifi_management_ap_start): the single-VIF firmware does station or AP at a time. Use WPA2, not WPA3: the SAE handshake is deep on the stack and overflows the elliptic-curve crypto with the default task stacks, so the Wi-Fi configs raise CONFIG_INIT_STACKSIZE/DEFAULT_TASK_STACKSIZE. Vendor SDK: cloned by the build at "context" time, pinned to a validated commit and patched in place -- so CI can build with nothing preinstalled, the same pattern as esp-hal-3rdparty. The prebuilt libraries are built for the hard-float ilp32f ABI. BLE 5.3, marked EXPERIMENTAL and off by default: the prebuilt libble is an all-in-one controller plus RivieraWaves host (GAP/GATT/SMP inside the blob) with no HCI transport, so the port drives the vendor host directly (ble_adp_*, ble_adv_*, ble_gap_*) instead of registering a bt_driver_s. The SDK's radio interrupt handlers must be attached to the NuttX IRQ table (they are reached through the ECLIC hardware vector table in the vendor build); attaching also keeps --gc-sections from dropping them. It ships with no configuration; enabling it advertises as "NuttX", connectable. Boards: gd32vw553k-start with nsh, wapi, sta_softap, periph and littlefs configurations, and the board added to the CI build list. Tested on hardware (GD32VW553K-START): NSH, the peripheral drivers (TRNG entropy and the LEDs exercised), LittleFS (write, read, survives a reboot), the full Wi-Fi station path (scan, WPA2, DHCP, ping to the internet), the softAP (a client associates with WPA2, gets an address from the board's DHCP server, and pings the board), and BLE (advertises as "NuttX"; a central connects and enumerates the GATT database). Assisted-by: Claude Opus 4.8 Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| hc | ||
| mips | ||
| misco | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| index.rst | ||