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176 lines
10 KiB
C
176 lines
10 KiB
C
/********************************************************************************************
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* arch/arm/src/samdl/chip/saml_nvmctrl.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_NVMCTRL_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_NVMCTRL_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* NVMCTRL register offsets *****************************************************************/
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#define SAM_NVMCTRL_CTRLA_OFFSET 0x0000 /* Control A register */
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#define SAM_NVMCTRL_CTRLB_OFFSET 0x0004 /* Control B register */
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#define SAM_NVMCTRL_PARAM_OFFSET 0x0008 /* NVM parameter register */
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#define SAM_NVMCTRL_INTENCLR_OFFSET 0x000c /* Interrupt clear register */
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#define SAM_NVMCTRL_INTENSET_OFFSET 0x0010 /* Interrupt set register */
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#define SAM_NVMCTRL_INTFLAG_OFFSET 0x0014 /* Interface flags status and clear register */
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#define SAM_NVMCTRL_STATUS_OFFSET 0x0018 /* Status register */
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#define SAM_NVMCTRL_ADDR_OFFSET 0x001c /* Address register */
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#define SAM_NVMCTRL_LOCK_OFFSET 0x0020 /* Lock section register */
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/* NVMCTRL register addresses ***************************************************************/
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#define SAM_NVMCTRL_CTRLA (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLA_OFFSET)
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#define SAM_NVMCTRL_CTRLB (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLB_OFFSET)
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#define SAM_NVMCTRL_INTENCLR (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTENCLR_OFFSET)
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#define SAM_NVMCTRL_INTENSET (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTENSET_OFFSET)
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#define SAM_NVMCTRL_INTFLAG (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTFLAG_OFFSET)
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#define SAM_NVMCTRL_STATUS (SAM_NVMCTRL_BASE+SAM_NVMCTRL_STATUS_OFFSET)
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#define SAM_NVMCTRL_ADDR (SAM_NVMCTRL_BASE+SAM_NVMCTRL_ADDR_OFFSET)
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#define SAM_NVMCTRL_LOCK (SAM_NVMCTRL_BASE+SAM_NVMCTRL_LOCK_OFFSET)
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/* NVMCTRL register bit definitions *********************************************************/
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/* Control A register */
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#define NVMCTRL_CTRLA_CMD_SHIFT (0) /* Bits 0-6: Command */
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#define NVMCTRL_CTRLA_CMD_MASK (0x7f << NVMCTRL_CTRLA_CMD_SHIFT)
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# define NVMCTRL_CTRLA_CMD_ER (0x02 << NVMCTRL_CTRLA_CMD_SHIFT) /* Erase Row */
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# define NVMCTRL_CTRLA_CMD_WP (0x04 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Page */
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# define NVMCTRL_CTRLA_CMD_EAR (0x05 << NVMCTRL_CTRLA_CMD_SHIFT) /* Erase Auxiliary Row */
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# define NVMCTRL_CTRLA_CMD_WAP (0x06 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Auxiliary Page */
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# define NVMCTRL_CTRLA_CMD_RWWEEER (0x1a << NVMCTRL_CTRLA_CMD_SHIFT) /* RWWEE Erase Row */
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# define NVMCTRL_CTRLA_CMD_RWWEEWP (0x1a << NVMCTRL_CTRLA_CMD_SHIFT) /* RWWEE Write page */
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# define NVMCTRL_CTRLA_CMD_LR (0x40 << NVMCTRL_CTRLA_CMD_SHIFT) /* Lock Region */
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# define NVMCTRL_CTRLA_CMD_UR (0x41 << NVMCTRL_CTRLA_CMD_SHIFT) /* Unlock Region */
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# define NVMCTRL_CTRLA_CMD_SPRM (0x42 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set power reduction mode */
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# define NVMCTRL_CTRLA_CMD_CPRM (0x43 << NVMCTRL_CTRLA_CMD_SHIFT) /* Clear power reduction mode */
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# define NVMCTRL_CTRLA_CMD_PBC (0x44 << NVMCTRL_CTRLA_CMD_SHIFT) /* Page Buffer Clear */
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# define NVMCTRL_CTRLA_CMD_SSB (0x45 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set Security Bit */
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# define NVMCTRL_CTRLA_CMD_INVALL (0x46 << NVMCTRL_CTRLA_CMD_SHIFT) /* Invalidate all cache lines */
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#define NVMCTRL_CTRLA_CMDEX_SHIFT (8) /* Bits 8-15: Command Execution */
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#define NVMCTRL_CTRLA_CMDEX_MASK (0xff << NVMCTRL_CTRLA_CMDEX_SHIFT)
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# define NVMCTRL_CTRLA_CMDEX (0xa5 << NVMCTRL_CTRLA_CMDEX_SHIFT)
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/* Control B register */
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#define NVMCTRL_CTRLB_RWS_SHIFT (1) /* Bits 1-4: NVM Read Wait States */
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#define NVMCTRL_CTRLB_RWS_MASK (15 << NVMCTRL_CTRLB_RWS_SHIFT)
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# define NVMCTRL_CTRLB_RWS(n) ((uint32_t)(n) << NVMCTRL_CTRLB_RWS_SHIFT)
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#define NVMCTRL_CTRLB_MANW (1 << 7) /* Bit 7: Manual Write */
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#define NVMCTRL_CTRLB_SLEEPPRM_SHIFT (8) /* Bits 8-9: Power Reduction Mode during Sleep */
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#define NVMCTRL_CTRLB_SLEEPPRM_MASK (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT)
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# define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (0 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power on first access */
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# define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (1 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power when exit sleep */
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# define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Auto power reduction disabled */
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#define NVMCTRL_CTRLB_READMODE_SHIFT (16) /* Bits 16-17: NVMCTRL Read Mode */
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#define NVMCTRL_CTRLB_READMODE_MASK (3 << NVMCTRL_CTRLB_READMODE_SHIFT)
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# define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (0 << NVMCTRL_CTRLB_READMODE_SHIFT) /* No extra wait states on miss */
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# define NVMCTRL_CTRLB_READMODE_LOW_POWER (1 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Insert wait/reduce power */
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# define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (2 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Same wait on all access */
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#define NVMCTRL_CTRLB_CACHEDIS (1 << 18) /* Bit 18: Cache Disable */
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/* NVM parameter register */
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#define NVMCTRL_PARAM_NVMP_SHIFT (0) /* Bits 0-15: NVM Pages */
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#define NVMCTRL_PARAM_NVMP_MASK (0xffff << NVMCTRL_PARAM_NVMP_SHIFT)
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# define NVMCTRL_PARAM_NVMP(n) ((uint32_t)(n) << NVMCTRL_PARAM_NVMP_SHIFT)
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#define NVMCTRL_PARAM_PSZ_SHIFT (16) /* Bits 16-18: Page Size */
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#define NVMCTRL_PARAM_PSZ_MASK (7 << NVMCTRL_PARAM_PSZ_SHIFT)
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# define NVMCTRL_PARAM_PSZ_8B (0 << NVMCTRL_PARAM_PSZ_SHIFT) /* 8 bytes */
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# define NVMCTRL_PARAM_PSZ_16B (1 << NVMCTRL_PARAM_PSZ_SHIFT) /* 16 bytes */
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# define NVMCTRL_PARAM_PSZ_32B (2 << NVMCTRL_PARAM_PSZ_SHIFT) /* 32 bytes */
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# define NVMCTRL_PARAM_PSZ_64B (3 << NVMCTRL_PARAM_PSZ_SHIFT) /* 64 bytes */
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# define NVMCTRL_PARAM_PSZ_128B (4 << NVMCTRL_PARAM_PSZ_SHIFT) /* 128 bytes */
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# define NVMCTRL_PARAM_PSZ_256B (5 << NVMCTRL_PARAM_PSZ_SHIFT) /* 256 bytes */
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# define NVMCTRL_PARAM_PSZ_512B (6 << NVMCTRL_PARAM_PSZ_SHIFT) /* 512 bytes */
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# define NVMCTRL_PARAM_PSZ_1KB (7 << NVMCTRL_PARAM_PSZ_SHIFT) /* 1024 bytes */
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#define NVMCTRL_PARAM_RWWEEP_SHIFT (20) /* Bits 20-31: Read while write EEPROM emulation area pages */
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#define NVMCTRL_PARAM_RWWEEP_MASK (0xfff << NVMCTRL_PARAM_RWWEEP_SHIFT)
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# define NVMCTRL_PARAM_RWWEEP(n) ((uint32_t)(n) << NVMCTRL_PARAM_RWWEEP_SHIFT)
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/* Interrupt clear register */
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/* Interrupt set register */
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/* Interface flags status and clear register */
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#define NVMCTRL_INT_READY (1 << 0) /* Bit 0: NVM Ready Interrupt */
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#define NVMCTRL_INT_ERROR (1 << 1) /* Bit 1: Error Interrupt */
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/* Status register */
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#define NVMCTRL_STATUS_PRM (1 << 0) /* Bit 0: Power Reduction Mode */
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#define NVMCTRL_STATUS_LOAD (1 << 1) /* Bit 1: NVM Page Buffer Active Loading */
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#define NVMCTRL_STATUS_PROGE (1 << 2) /* Bit 2: Programming Error Status */
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#define NVMCTRL_STATUS_LOCKE (1 << 3) /* Bit 3: Lock Error Status */
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#define NVMCTRL_STATUS_NVME (1 << 4) /* Bit 4: NVM Error */
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#define NVMCTRL_STATUS_SB (1 << 8) /* Bit 8: Security Bit Status */
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/* Address register */
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#define NVMCTRL_ADDR_MASK (0x001fffff) /* Bits 0-20: NVM Address */
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/* Lock section register */
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#define NVMCTRL_LOCK_REGION(n) (1 << (n)) /* Region n is locked */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAML21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_NVMCTRL_H */
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