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This patch addresses two issues in the single-timer capture/compare tickless OS drivers for STM32 families (common m3m4 v1 for F1/F2/F3/F4/G4, F7, H7, and WB): 1. Zero-period handling: when up_timer_start() is called with a zero or negative duration (or period converts to 0 ticks), the driver now enables the compare match interrupt and immediately fires an event via EGR (CCxG), avoiding missed events or unexpected counter behavior. 2. Compare-match race condition: after programming CCR and enabling the compare interrupt, a post-check validates whether the free-running counter already reached or passed count + period during register configuration. If elapsed, the interrupt is forced immediately via EGR, preventing the counter from missing the match and hanging until a full 32-bit rollover (approx. 71 minutes at 1 MHz). Verified on real hardware: - STM32H743ZI (IED R550): validated with ping, sleep, and usleep. - STM32G431KB (Nucleo-G431KB): validated with uptime, sleep, and usleep. Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com> |
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