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ae7525d195
The register index layout for D16-D31 and FPU_CONTEXT_REGS was guarded
by CONFIG_ARM_HAVE_DPFPU32 (hardware capability) in three header files,
but all save/restore code in the corresponding .S files gates on
CONFIG_ARM_DPFPU32 (software enable).
These two macros are distinct:
CONFIG_ARM_HAVE_DPFPU32 - set by chip via 'select'; means hardware
has D16-D31 registers
CONFIG_ARM_DPFPU32 - user-selectable; means software has chosen
to use D16-D31 (requires hardware support)
When ARM_HAVE_DPFPU32=y and ARM_DPFPU32=n, the header defined
REG_FPSCR at offset 64 and FPU_CONTEXT_REGS=65, while the assembly
only saved S0-S31+FPSCR (33 words), placing FPSCR at offset 32.
This mismatch causes incorrect register access and wrong xcptcontext
sizing.
Signed-off-by: yaojiaqi <yaojiaqi@lixiang.com>
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||