raiden00pl 7135c91b0f arch/arm/include/xmc4: add irq definitions for xmc4700 and xmc4800		2020-03-22 08:29:51 -06:00
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chip.h	In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.	2018-12-03 17:41:59 -06:00
irq.h	arch/arm/include/xmc4: add irq definitions for xmc4700 and xmc4800	2020-03-22 08:29:51 -06:00
xmc4500_irq.h	arch/arm/include/xmc4: add irq definitions for xmc4700 and xmc4800	2020-03-22 08:29:51 -06:00
xmc4700_irq.h	arch/arm/include/xmc4: add irq definitions for xmc4700 and xmc4800	2020-03-22 08:29:51 -06:00
xmc4800_irq.h	arch/arm/include/xmc4: add irq definitions for xmc4700 and xmc4800	2020-03-22 08:29:51 -06:00