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Drives the speed of the four application cores. The rate is set to any of the operating points the vendor validates, all of which share a core voltage, so this touches no regulator. The cores run from the PLL being reprogrammed, so they park on a slower clock first, through a selector the vendor names as glitch free. While parked the PLL is stopped, given new dividers, restarted and watched until it locks; if it never locks the cores stay parked, since returning them to an unlocked PLL does not fail safely. Above a gigahertz the bus ratio must be two to one before the cores return: the bus fabric does not reach beyond about eight hundred megahertz. That is the one step in the sequence software cannot recover from, so the mux is moved before the ratio. The rate is measured rather than derived. The cores are counted against the crystal derived time counter and the result reported beside what the clock tree computes, because the manual and the vendor's code number the CPU PLL's outputs differently. The core selector's parent is cpupll_fout1, and the three CPU PLL outputs are marked CLK_GET_RATE_NOCACHE since this driver reprograms that PLL at run time. Assisted-by: Claude:claude-opus-5 Signed-off-by: Justin Hammond <justin@dynam.ac> |
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