Gregory Nutt ffca71b9bf Alexey T, Bitbuck Issue 73: ... Lower part of STM32 CAN driver arch/arm/src/stm32/stm32_can.c uses all three hw tx mailboxes and clears TXFP bit in the CAN_MCR register (it means transmission order is defined by identifier and mailbox number). This creates situation when order frames are put in upper part of CAN driver (via can_write) and order frames are sent on bus can be different (and I experience this in wild). Since CAN driver API pretends to be "file like" I expect data to be read from fd the same order it is written. So I consider described behaviour to be a bug. I propose either to set TXFP bit in the CAN_MCR register (FIFO transmit order) or to use only one mailbox.		2017-10-19 06:34:54 -06:00
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include	BCM2708: Fleshes out GPIO interrupt logic.	2017-10-18 10:13:10 -06:00
src	Alexey T, Bitbuck Issue 73:	2017-10-19 06:34:54 -06:00
Kconfig	BCM2708: Add system timer register definitions and a partial implementation of the tickless mode timer.	2017-10-17 13:54:54 -06:00