raiden00pl acc296ef09 arm/stm32n6: configure board clocks after ROM boot ... In the nominal ROM clock configuration, flash boot leaves PLL1 driving the CPU at 400 MHz. Skipping clock setup when PLL1 is already selected makes SysTick run twice as fast as the board's 200 MHz configuration expects. Switch CPU and system clocks to HSI before reconfiguring PLL1, then apply the board clock tree. Remove the incorrect comments claiming CFGR1 and CFGR2 lock after the first clock switch. Assisted-by: Codex:GPT-6 Signed-off-by: raiden00pl <raiden00@railab.me>		2026-10-06 15:34:14 -03:00
..
arm	arm/stm32n6: configure board clocks after ROM boot	2026-10-06 15:34:14 -03:00
arm64	arch/arm64: refuse reserved syscalls from user space	2026-10-01 23:14:53 +08:00
avr
ceva	arch/atomic: remove up_testset in spinlock	2026-09-08 08:58:54 +08:00
dummy
hc
mips	arch/mips/pic32mz: do not exceed the requested SPI frequency.	2026-10-05 12:30:56 -03:00
misoc
or1k
renesas
risc-v	arch/risc-v: refuse reserved syscalls from user mode	2026-10-01 23:14:53 +08:00
sim	arch/sim: buffer several mouse reports	2026-09-25 10:36:28 +02:00
sparc	arch/atomic: remove up_testset in spinlock	2026-09-08 08:58:54 +08:00
tricore	arch/atomic: remove up_testset in spinlock	2026-09-08 08:58:54 +08:00
x86	arch/x86: Add -P to CPP to suppress linemarkers.	2026-09-17 16:21:59 +08:00
x86_64	arch/x86_64: Implement up_addrenv_fork() and provide POSIX fork().	2026-09-24 18:02:36 -03:00
xtensa	espressif: stop leaking a Wi-Fi interrupt handle on every esp_wifi_start()	2026-09-30 13:25:42 -03:00
z16
z80
CMakeLists.txt
Kconfig	arch/xtensa: Provide POSIX fork() on the ESP32-S3.	2026-09-26 11:13:57 -03:00