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279e1ec458
Add the General PWM Timer (GPT) as a generic timer, registered as /dev/timerN through the upper-half timer driver. GPT0-7 are 32-bit, GPT8-13 are 16-bit, and the timeout can be changed while running. Give each ICU event used by GPT its own enum value instead of a __COUNTER__-based macro, since the latter can hand out a different number at every use. Live period changes to the same prescaler now reload through GTPBR (the buffered period register) instead of stopping the counter, matching Renesas's own FSP driver, and fix a hardware-confirmed bug where an uninitialized GTPBR silently corrupted the period after the first cycle. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Assisted-by: Claude:claude-sonnet-5 Signed-off-by: leocafonso <leocafonso@gmail.com>
245 lines
10 KiB
C
245 lines
10 KiB
C
/****************************************************************************
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* arch/arm/include/ra8m1/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_RA8M1_CHIP_H
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#define __ARCH_ARM_INCLUDE_RA8M1_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_R7FA8M1AFECAM)
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# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
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# define RA_NGPT 8 /* GPT0-7 */
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# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
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# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */
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# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
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# if defined(CONFIG_ARMV8M_HAVE_ITCM)
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# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
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# else
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# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV8M_HAVE_DTCM)
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# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
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# else
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# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECBD)
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# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
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# define RA_NGPT 8 /* GPT0-7 */
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# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
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# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */
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# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
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# if defined(CONFIG_ARMV8M_HAVE_ITCM)
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# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
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# else
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# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV8M_HAVE_DTCM)
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# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
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# else
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# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFB)
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# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
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# define RA_NGPT 8 /* GPT0-7 */
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# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
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# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */
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# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
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# if defined(CONFIG_ARMV8M_HAVE_ITCM)
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# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
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# else
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# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV8M_HAVE_DTCM)
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# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
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# else
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# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFC)
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# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
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# define RA_NGPT 8 /* GPT0-7 */
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# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
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# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */
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# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
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# if defined(CONFIG_ARMV8M_HAVE_ITCM)
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# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
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# else
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# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV8M_HAVE_DTCM)
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# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
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# else
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# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AFECFP)
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# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
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# define RA_NGPT 8 /* GPT0-7 */
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# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
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# define RA_FLASH_SIZE (1024*1024) /* 1024Kb FLASH */
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# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
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# if defined(CONFIG_ARMV8M_HAVE_ITCM)
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# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
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# else
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# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV8M_HAVE_DTCM)
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# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
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# else
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# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECAM)
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# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
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# define RA_NGPT 8 /* GPT0-7 */
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# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
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# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */
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# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
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# if defined(CONFIG_ARMV8M_HAVE_ITCM)
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# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
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# else
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# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV8M_HAVE_DTCM)
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# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
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# else
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# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECBD)
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# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
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# define RA_NGPT 8 /* GPT0-7 */
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# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
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# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */
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# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
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# if defined(CONFIG_ARMV8M_HAVE_ITCM)
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# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
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# else
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# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV8M_HAVE_DTCM)
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# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
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# else
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# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFB)
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# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
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# define RA_NGPT 8 /* GPT0-7 */
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# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
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# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */
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# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
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# if defined(CONFIG_ARMV8M_HAVE_ITCM)
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# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
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# else
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# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV8M_HAVE_DTCM)
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# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
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# else
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# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFC)
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# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
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# define RA_NGPT 8 /* GPT0-7 */
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# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
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# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */
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# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
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# if defined(CONFIG_ARMV8M_HAVE_ITCM)
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# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
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# else
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# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV8M_HAVE_DTCM)
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# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
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# else
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# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_R7FA8M1AHECFP)
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# define RA_NSCI_B 6 /* SCI_B0-4, SCI_B9 (not contiguous: no SCI_B5-8) */
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# define RA_NGPT 8 /* GPT0-7 */
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# define RA_RAM_SIZE (896*1024) /* 896Kb RAM */
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# define RA_FLASH_SIZE (2016*1024) /* 2016Kb FLASH */
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# define RA_DATA_FLASH_SIZE (12*1024) /* 12Kb DATA_FLASH */
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# if defined(CONFIG_ARMV8M_HAVE_ITCM)
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# define RA_ITCM_SIZE (64*1024) /* 64Kb ITCM on TCM interface */
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# else
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# define RA_ITCM_SIZE (0) /* No ITCM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV8M_HAVE_DTCM)
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# define RA_DTCM_SIZE (64*1024) /* 64Kb DTCM on TCM interface */
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# else
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# define RA_DTCM_SIZE (0) /* No DTCM on TCM interface */
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# endif
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#else
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# error "Unsupported RA8M1 chip"
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#endif
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/* NVIC Priority Levels *****************************************************/
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/* Each priority field holds a priority value, 0-15. The lower
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* the value, the greater the priority of the corresponding
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* interrupt. The processor implements only bits[7:4] of each
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* field, bits[3:0] read as zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_RA8M1_CHIP_H */
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