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80d6f34cd7
- Add imxrt118x compatible IOMUX definitions, named as IOMUX_VER3. This is the same IP as what is used for example for IMX9. Instead of directly copying the support from imx9, pack the padconfig into the same 32-bit value used for GPIO for easy use. - Add imxrt118x compatible rgpio driver. This is the same GPIO block as what has been used in imx9. Instead of directly copying the support from IMX9, add pin muxing directly into GPIO driver as well, to keep the usage compatible with existing IMXRT boards. Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
121 lines
5.1 KiB
C
121 lines
5.1 KiB
C
/****************************************************************************
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* arch/arm/include/imxrt/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
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#define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_MIMXRT1021CAG4A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1021CAF4A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1021DAF5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1021DAG5A)
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/* MIMXRT1021CAG4A - 144 pin, 400MHz Industrial
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* MIMXRT1021CAF4A - 100 pin, 400MHz Industrial
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* MIMXRT1021DAF5A - 100 pin, 500MHz Consumer
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* MIMXRT1021DAG5A - 144 pin, 500MHz Consumer
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*/
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# define IMXRT_OCRAM_SIZE (256 * 1024) /* 256Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 5 /* Five total ports */
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/* but 4 doesn't exist */
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#elif defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
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/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz
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* MIMXRT1051DVL6A - Consumer, Reduced Features, 600MHz
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* MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1052DVL6A - Consumer, Full Feature, 600MHz
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*/
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# define IMXRT_OCRAM_SIZE (512 * 1024) /* 512Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 5 /* Five total ports */
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#elif defined(CONFIG_ARCH_CHIP_MIMXRT1061DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1064DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1064CVL5A)
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/* MIMXRT1061CVL5A - Industrial, Reduced Features, 528MHz
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* MIMXRT1061DVL6A - Consumer, Reduced Features, 600MHz
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* MIMXRT1062CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1062DVL6A - Consumer, Full Feature, 600MHz
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* MIMXRT1064CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1064DVL6A - Consumer, Full Feature, 600MHz
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*/
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# define IMXRT_OCRAM_SIZE (1024 * 1024) /* 1024Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 9 /* Nine total ports */
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#elif defined(CONFIG_ARCH_CHIP_MIMXRT1176DVMAA)
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/* MIMXRT1170DVMA TODO
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*/
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# define IMXRT_GPIO_NPORTS 13 /* Thirteen total ports */
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#elif defined(CONFIG_ARCH_CHIP_MIMXRT1189CVM8C) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33)
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/* MIMXRT1189CVM8C - Dual-core Cortex-M33 + Cortex-M7 */
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# define IMXRT_GPIO_NPORTS 6 /* Six general purpose GPIO ports */
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#else
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# error "Unknown i.MX RT chip type"
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#endif
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds an 8-bit priority value, 0-15. The lower the
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* value, the greater the priority of the corresponding interrupt. The i.MX
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* RT processor implements only bits[7:4] of each field, bits[3:0] read as
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* zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is min pri */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt pri used */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */
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