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783e1b8808
Add ULP RISC-V coprocessor board support for esp32[-s2|-s3] Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
65 lines
1.7 KiB
Text
65 lines
1.7 KiB
Text
/****************************************************************************
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* boards/xtensa/esp32s2/common/scripts/esp32s2_ulp_riscv_sections.ld
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#include <nuttx/config.h>
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ENTRY(reset_vector)
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MEMORY
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{
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ram(RW) : ORIGIN = 0, LENGTH = CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
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}
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SECTIONS
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{
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. = ORIGIN(ram);
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.text :
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{
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*ulp_riscv_vectors.S.obj(.text.vectors) /* Default reset vector must link to offset 0x0 */
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*(.text)
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*(.text*)
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} >ram
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.rodata ALIGN(4):
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{
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*(.rodata)
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*(.rodata*)
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} > ram
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.data ALIGN(4):
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{
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*(.data)
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*(.data*)
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*(.sdata)
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*(.sdata*)
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} > ram
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.bss ALIGN(4) :
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{
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*(.bss)
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*(.bss*)
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*(.sbss)
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*(.sbss*)
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} >ram
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__stack_top = ORIGIN(ram) + LENGTH(ram);
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}
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