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AVR uses Hardward architecture with separate address space for program memory (flash) and data memory (RAM). Normal program flow can only access data memory which means that all variables - including const variables - have to be copied into RAM to be accessible. (This happens automatically during startup.) It is possible to work around this limitation in software but that can have severe impact on performance and/or API complexity. It is hardly feasible to change NuttX interfaces in a way that would allow to make use of this workaround. On newer AVR families, there is an alternative option enabled by this patch. These chips map part of their program memory (a 32kB window) into data memory address space. This patch leverages this feature and adds support for placing const variables into the mapped window. No copy to RAM is done for them. Const variables are therefore loaded directly from flash (not consuming RAM) while still being available to be used by any NuttX interface. Linker script of breadxavr board is changed to make use of these changes. Tested by verifying string addresses - parameters in printf call in a custom application (and also by running the application and verifying its output.) Documentation tested by build. Signed-off-by: Kerogit <kr.git@kerogit.eu>
252 lines
7 KiB
Text
252 lines
7 KiB
Text
/****************************************************************************
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* boards/avr/avrdx/breadxavr/scripts/breadxavr.ld
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Memory Regions ***********************************************************/
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/* -------------- ------ ------+------- -- ------ -- ------ --- ------ ----+------- ---
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* FLASH | REGISTERS I/O EXT I/O ISRAM | EEPROM
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* | REGISTERS REGISTERS |
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* -------------- ------ ------+------- -- ------ -- ------ --- ------ ----+------- ---
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* ATMEGA1284P 0x0000 128Kb | 0x0000 32 0x0020 64 0x0060 160 0x0100 16Kb| 0x0000 4Kb
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* -------------- ------ ------+------- -- ------ -- ------ --- ------ ----+------- ---
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* *Memory configuration A
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*/
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/* Use this instead of repeated magical number */
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__CHIP_FLASH_SIZE__ = 128K;
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/* VMA above 0x800000, must not collide with anything else,
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* arbitrary value otherwise.
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*/
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__RODATA_VMA__ = 0xa00000;
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/* Application configuration is supposed to pass this value
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* to linker so the default should not be used.
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*/
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__RODATA_SIZE__ = DEFINED(__RODATA_SIZE__) ? __RODATA_SIZE__ : 4K;
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/* Size increment matches chip's memory organization (boot, application
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* code and application data can be sized with 512B increments.)
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*/
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ASSERT (__RODATA_SIZE__ % 512 == 0,
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"__RODATA_SIZE__ must be a multiple of 512")
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/* Only 32kB of flash is mapped to data memory */
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ASSERT (__RODATA_SIZE__ <= 32K,
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"__RODATA_SIZE__ must not be larger than 32kB")
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/* Same as for __RODATA_SIZE__ */
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__RODATA_OFFSET__ = DEFINED(__RODATA_OFFSET__) ? __RODATA_OFFSET__ : 0;
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/* Size increment matches chip's memory organization (boot, application
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* code and application data can be sized with 512B increments.)
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*/
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ASSERT (__RODATA_OFFSET__ % 512 == 0,
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"__RODATA_OFFSET__ must be a multiple of 512")
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/* Only 32kB of flash is mapped to data memory */
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ASSERT (__RODATA_OFFSET__ <= 31K,
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"__RODATA_OFFSET__ must not be larger than 31kB")
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/* Also verify sum of size and offset */
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ASSERT (__RODATA_SIZE__ + __RODATA_OFFSET__ <= 32K,
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"Sum of __RODATA_SIZE__ and __RODATA_OFFSET__ must not be larger than 32kB")
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/* Set the origin to the very end of flash. 64K is a magical number
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* that constitutes of 32K (start of memory-mapped flash in data
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* memory address space) and 32K (end of the area, size of the rodata
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* section is subtracted from it.)
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*/
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__RODATA_ORIGIN__ = __RODATA_VMA__ + 64K - __RODATA_SIZE__ - __RODATA_OFFSET__;
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__RODATA_FLASH_START = __CHIP_FLASH_SIZE__ - __RODATA_SIZE__ - __RODATA_OFFSET__;
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MEMORY
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{
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flash (rx) : ORIGIN = 0, LENGTH = __CHIP_FLASH_SIZE__
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sram (rw!x) : ORIGIN = 0x804000, LENGTH = 16K
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eeprom (rw!x) : ORIGIN = 0x801400, LENGTH = 512
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rodata (r!x) : ORIGIN = __RODATA_ORIGIN__, LENGTH = __RODATA_SIZE__
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}
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ENTRY(__start)
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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.hash : { *(.hash) }
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.dynsym : { *(.dynsym) }
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.dynstr : { *(.dynstr) }
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.gnu.version : { *(.gnu.version) }
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.gnu.version_d : { *(.gnu.version_d) }
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.gnu.version_r : { *(.gnu.version_r) }
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.rel.init : { *(.rel.init) }
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.rela.init : { *(.rela.init) }
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.rel.text :
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{
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*(.rel.text)
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*(.rel.text.*)
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*(.rel.gnu.linkonce.t*)
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}
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.rela.text :
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{
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*(.rela.text)
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*(.rela.text.*)
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*(.rela.gnu.linkonce.t*)
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}
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.rel.fini : { *(.rel.fini) }
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.rela.fini : { *(.rela.fini) }
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.rel.rodata :
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{
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*(.rel.rodata)
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*(.rel.rodata.*)
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*(.rel.gnu.linkonce.r*)
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}
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.rela.rodata :
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{
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*(.rela.rodata)
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*(.rela.rodata.*)
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*(.rela.gnu.linkonce.r*)
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}
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.rel.data :
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{
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*(.rel.data)
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*(.rel.data.*)
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*(.rel.gnu.linkonce.d*)
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}
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.rela.data :
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{
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*(.rela.data)
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*(.rela.data.*)
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*(.rela.gnu.linkonce.d*)
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}
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.rel.ctors : { *(.rel.ctors) }
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.rela.ctors : { *(.rela.ctors) }
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.rel.dtors : { *(.rel.dtors) }
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.rela.dtors : { *(.rela.dtors) }
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.rel.got : { *(.rel.got) }
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.rela.got : { *(.rela.got) }
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.rel.bss : { *(.rel.bss) }
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.rela.bss : { *(.rela.bss) }
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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.text :
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{
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_stext = . ;
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*(.vectors)
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KEEP(*(.vectors))
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*(.progmem.gcc*)
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*(.progmem*)
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. = ALIGN(2);
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*(.init)
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*(.handlers)
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*(.text)
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*(.text.*)
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_etext = . ;
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} > flash
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_eronly = ABSOLUTE(.);
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.data :
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{
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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_edata = ABSOLUTE(.);
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} > sram AT > flash
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.bss :
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{
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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_ebss = ABSOLUTE(.);
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} > sram
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/* Global data not cleared after reset. */
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.noinit :
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{
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_snoinit = ABSOLUTE(.);
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*(.noinit*)
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_enoinit = ABSOLUTE(.);
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} > sram
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.rodata ABSOLUTE(__RODATA_ORIGIN__) : AT (ABSOLUTE(__RODATA_FLASH_START))
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{
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*(.rodata)
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*(.rodata*)
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*(.gnu.linkonce.r*)
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_rodata_end = ABSOLUTE(.);
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} > rodata
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.eeprom :
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{
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_seeprom = ABSOLUTE(.);
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*(.eeprom*)
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_eeeprom = ABSOLUTE(.);
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} > eeprom
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* DWARF debug sections.
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Symbols in the DWARF debugging sections are relative to the beginning
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of the section so we begin them at 0. */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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}
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