mirror of
https://github.com/apache/nuttx.git
synced 2026-08-02 12:49:00 +00:00
The message RAM does not behave correctly if lower 16 bits of buffer address overflow (upper 16 bits are set once in matrix driver for the entire CAN driver). For example message RAM starting at 0x2040fc20 would not work for buffers that go beyond 0x20410000 and MCAN would sent data located at 0x20400000 to the network. The same issue would occur even if TX buffers would start directly at 0x20410000. The upper 16 bits would still have 0x2040 value because of RX buffers located in 0x2040ffff range. This commit ensures the RAM is always located at the beginning of the data section and thus the overflow mentioned above should never occur. The alternative would be to use larger alignment, but the message RAM can have up to 4352 words and this would cause a significant padding. The RAM is also initialized to zero to ensure valid parity/ECC checksums. The address issue is not described anywhere in the manual, so it is possible this is caused by some incorrect configuration, but the context of the registers looks valid. This commit also fixes the compilation errors when the driver is run without data cache. Signed-off-by: Michal Lenc <michallenc@seznam.cz>
140 lines
4 KiB
Text
140 lines
4 KiB
Text
/****************************************************************************
|
|
* boards/arm/samv7/common/scripts/flash.ld.template
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*
|
|
* Licensed to the Apache Software Foundation (ASF) under one or more
|
|
* contributor license agreements. See the NOTICE file distributed with
|
|
* this work for additional information regarding copyright ownership. The
|
|
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
|
* "License"); you may not use this file except in compliance with the
|
|
* License. You may obtain a copy of the License at
|
|
*
|
|
* http://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
|
* License for the specific language governing permissions and limitations
|
|
* under the License.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#include <nuttx/config.h>
|
|
|
|
#define FLASH_START_ADDR 0x00400000
|
|
|
|
#ifdef CONFIG_ARMV7M_DTCM
|
|
# define SRAM_START_ADDR 0x20000000
|
|
#else
|
|
# define SRAM_START_ADDR 0x20400000
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMV7_FORMAT_MCUBOOT
|
|
# define MCUBOOT_HEADER_SIZE CONFIG_SAMV7_MCUBOOT_HEADER_SIZE
|
|
# ifdef CONFIG_BOARDCTL_BOOT_IMAGE
|
|
# define FLASH_OFFSET 0
|
|
# define FLASH_IMG_SIZE CONFIG_SAMV7_OTA_PRIMARY_SLOT_OFFSET
|
|
# else
|
|
# define FLASH_OFFSET (CONFIG_SAMV7_OTA_PRIMARY_SLOT_OFFSET + MCUBOOT_HEADER_SIZE)
|
|
# define FLASH_IMG_SIZE (CONFIG_SAMV7_OTA_SLOT_SIZE - MCUBOOT_HEADER_SIZE)
|
|
# endif
|
|
#else
|
|
# define FLASH_OFFSET 0
|
|
# define FLASH_IMG_SIZE CONFIG_ARCH_CHIP_SAMV7_MEM_FLASH
|
|
#endif
|
|
|
|
MEMORY
|
|
{
|
|
flash (rx) : ORIGIN = FLASH_START_ADDR + FLASH_OFFSET, LENGTH = FLASH_IMG_SIZE
|
|
sram (rwx) : ORIGIN = SRAM_START_ADDR, LENGTH = CONFIG_ARCH_CHIP_SAMV7_MEM_RAM
|
|
}
|
|
|
|
OUTPUT_ARCH(arm)
|
|
EXTERN(_vectors)
|
|
ENTRY(_stext)
|
|
|
|
SECTIONS
|
|
{
|
|
.text : {
|
|
_stext = ABSOLUTE(.);
|
|
*(.vectors)
|
|
*(.text .text.*)
|
|
*(.fixup)
|
|
*(.gnu.warning)
|
|
*(.rodata .rodata.*)
|
|
*(.gnu.linkonce.t.*)
|
|
*(.glue_7)
|
|
*(.glue_7t)
|
|
*(.got)
|
|
*(.gcc_except_table)
|
|
*(.gnu.linkonce.r.*)
|
|
_etext = ABSOLUTE(.);
|
|
} > flash
|
|
|
|
.init_section : {
|
|
_sinit = ABSOLUTE(.);
|
|
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
|
KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
|
|
_einit = ABSOLUTE(.);
|
|
} > flash
|
|
|
|
.ARM.extab : {
|
|
*(.ARM.extab*)
|
|
} > flash
|
|
|
|
__exidx_start = ABSOLUTE(.);
|
|
.ARM.exidx : {
|
|
*(.ARM.exidx*)
|
|
} > flash
|
|
__exidx_end = ABSOLUTE(.);
|
|
|
|
_eronly = ABSOLUTE(.);
|
|
|
|
/* The RAM vector table (if present) should lie at the beginning of SRAM */
|
|
|
|
.ram_vectors : {
|
|
*(.ram_vectors)
|
|
} > sram
|
|
|
|
.data : {
|
|
_sdata = ABSOLUTE(.);
|
|
*(.mcan)
|
|
*(.data .data.*)
|
|
*(.gnu.linkonce.d.*)
|
|
CONSTRUCTORS
|
|
. = ALIGN(4);
|
|
_edata = ABSOLUTE(.);
|
|
} > sram AT > flash
|
|
|
|
.ramfunc : ALIGN(4) {
|
|
_sramfuncs = ABSOLUTE(.);
|
|
*(.ramfunc .ramfunc.*)
|
|
_eramfuncs = ABSOLUTE(.);
|
|
} > sram AT > flash
|
|
|
|
_framfuncs = LOADADDR(.ramfunc);
|
|
|
|
.bss : {
|
|
_sbss = ABSOLUTE(.);
|
|
*(.bss .bss.*)
|
|
*(.gnu.linkonce.b.*)
|
|
*(COMMON)
|
|
. = ALIGN(4);
|
|
_ebss = ABSOLUTE(.);
|
|
} > sram
|
|
|
|
/* Stabs debugging sections. */
|
|
.stab 0 : { *(.stab) }
|
|
.stabstr 0 : { *(.stabstr) }
|
|
.stab.excl 0 : { *(.stab.excl) }
|
|
.stab.exclstr 0 : { *(.stab.exclstr) }
|
|
.stab.index 0 : { *(.stab.index) }
|
|
.stab.indexstr 0 : { *(.stab.indexstr) }
|
|
.comment 0 : { *(.comment) }
|
|
.debug_abbrev 0 : { *(.debug_abbrev) }
|
|
.debug_info 0 : { *(.debug_info) }
|
|
.debug_line 0 : { *(.debug_line) }
|
|
.debug_pubnames 0 : { *(.debug_pubnames) }
|
|
.debug_aranges 0 : { *(.debug_aranges) }
|
|
}
|