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60bf6827f2
- Add support for the IMX95LPD5EVK-19 evaluation kit (M7 core only)
- Firmware can be executed from ITCM, DDR or NOR flash
- configurations:
'nsh' A minimal configuration that only enables nsh shell
on a UART
'rpmsg' This configuration is similar to nsh but in addition
it offers the Remote Processing Messaging (RPMsg) service to
enable heterogeneous inter-core communication.
137 lines
3.8 KiB
Text
137 lines
3.8 KiB
Text
/****************************************************************************
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* boards/arm/imx95/imx95-evk/scripts/itcm.ld
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-FileCopyrightText: 2024 NXP
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*
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****************************************************************************/
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/*
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* Flash controller
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* 1) 32 MB of FlexSPI_1 at 0x0200:0000
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* The on-chip SRAM is split in these parts:
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* 1) 256Kb of program memory located at 0x0000:0000
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* 2) 256Kb of data memory beginning at the address 0x2000:0000
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* 3) 352Kb of OCRAM beginning at the address 0x2048:0000
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* 4) 4Mb of SDRAM located at 0x9000:0000
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*/
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MEMORY
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{
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m_interrupts (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000800
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flash (rx) : ORIGIN = 0x00000800, LENGTH = 0x0003F800
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sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
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ocram (rwx) : ORIGIN = 0x20480000, LENGTH = 352K
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}
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OUTPUT_ARCH(arm)
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EXTERN(_vectors)
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ENTRY(_stext)
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SECTIONS
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{
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.interrupts :
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{
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__VECTOR_TABLE = .;
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__Vectors = .;
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. = ALIGN(4);
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KEEP(*(.vectors)) /* Startup code */
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. = ALIGN(4);
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} > m_interrupts
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.text : {
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_stext = ABSOLUTE(.);
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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_etext = ABSOLUTE(.);
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} > flash
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.resource_table :
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{
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. = ALIGN(8);
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KEEP(*(.resource_table))
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. = ALIGN(4);
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} > flash
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.init_section : {
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_sinit = ABSOLUTE(.);
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KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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KEEP(*(.init_array .ctors))
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_einit = ABSOLUTE(.);
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} > flash
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.ARM.extab : {
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*(.ARM.extab*)
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} > flash
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__exidx_start = ABSOLUTE(.);
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.ARM.exidx : {
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*(.ARM.exidx*)
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} > flash
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__exidx_end = ABSOLUTE(.);
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_eronly = ABSOLUTE(.);
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.data : {
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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} > sram AT > flash
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.bss : {
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = ABSOLUTE(.);
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} > sram
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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_ram_start = ORIGIN(sram);
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_ram_size = LENGTH(sram);
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_ram_end = ORIGIN(sram) + LENGTH(sram);
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_ocram_start = ORIGIN(ocram);
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_ocram_size = LENGTH(ocram);
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_ocram_end = ORIGIN(ocram) + LENGTH(ocram);
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}
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