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186 lines
7.5 KiB
C
186 lines
7.5 KiB
C
/****************************************************************************
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* boards/arm/imx9/imx95-evk/include/board.h
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-FileCopyrightText: 2024 NXP
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_IMX9_IMX95_EVK_INCLUDE_BOARD_H
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#define __BOARDS_ARM_IMX9_IMX95_EVK_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define BOARD_XTAL_FREQUENCY 24000000
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#define BOARD_CPU_FREQUENCY BOARD_XTAL_FREQUENCY //FIXME
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#define LPUART3_CLK (LPUART3_CLK_ROOT_OSC_24M_CLK | CLOCK_DIV(1))
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#define LPI2C6_CLK (LPI2C6_CLK_ROOT_OSC_24M_CLK | CLOCK_DIV(1))
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#define LPSPI1_CLK (LPSPI1_CLK_ROOT_OSC_24M_CLK | CLOCK_DIV(1))
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#define FLEXCAN1_CLK (CAN1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK | CLOCK_DIV(5))
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/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/imxrt_autoleds.c. The LED is used to encode
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* OS-related events as follows:
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*
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* -------------------- ----------------------------- ------- -------
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* SYMBOL Meaning LED1 LED2
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* GREEN RED
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* -------------------- ----------------------------- ------- -------
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF */
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#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */
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#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */
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#define LED_STACKCREATED 1 /* Idle stack created ON OFF */
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#define LED_INIRQ 2 /* In an interrupt (No change) */
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#define LED_SIGNAL 2 /* In a signal handler (No change) */
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#define LED_ASSERTION 2 /* An assertion failed (No change) */
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#define LED_PANIC 3 /* The system has crashed OFF FLASH */
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#undef LED_IDLE /* Not used (Not used) */
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/* Default PAD configurations */
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#define IOMUX_LPI2C_DEFAULT (IOMUXC_PAD_OD_ENABLE | IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6)
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#define IOMUX_LPSPI_DEFAULT (IOMUXC_PAD_PU_ON | IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6)
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#define IOMUX_GPIO_DEFAULT (IOMUXC_PAD_FSEL_SLOW | IOMUXC_PAD_DSE_X6)
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/* UART pin muxings */
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#define MUX_LPUART3_RX IOMUX_CFG(IOMUXC_PAD_GPIO_IO15_LPUART3_RX, 0, IOMUXC_MUX_SION_ON)
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#define MUX_LPUART3_TX IOMUX_CFG(IOMUXC_PAD_GPIO_IO14_LPUART3_TX, IOMUXC_PAD_FSEL_SLOW | IOMUXC_PAD_DSE_X4, 0)
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/* FLEXIO to PWM pin muxings */
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/* EVK signals
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* GPIO_IO04 -> FLEXIO1_04
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* GPIO_IO05 -> FLEXIO1_05
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* GPIO_IO06 -> FLEXIO1_06
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* GPIO_IO07 -> FLEXIO1_07
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*/
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#define FLEXIO1_PWM0_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO04_FLEXIO1_FLEXIO04, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0)
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#define FLEXIO1_PWM1_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO05_FLEXIO1_FLEXIO05, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0)
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#define FLEXIO1_PWM2_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO06_FLEXIO1_FLEXIO06, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0)
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#define FLEXIO1_PWM3_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO07_FLEXIO1_FLEXIO07, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0)
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/* LPI2Cs */
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/* TPM3 ch3 to PWM pin GPIO_IO24 muxing */
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#define TPM3_PWM3_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO24_TPM3_CH3, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0)
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/* LPI2Cs */
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#define MUX_LPI2C6_SCL IOMUX_CFG(IOMUXC_PAD_GPIO_IO03_LPI2C6_SCL, IOMUX_LPI2C_DEFAULT, IOMUXC_MUX_SION_ON)
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#define MUX_LPI2C6_SDA IOMUX_CFG(IOMUXC_PAD_GPIO_IO02_LPI2C6_SDA, IOMUX_LPI2C_DEFAULT, IOMUXC_MUX_SION_ON)
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/* I2C reset functionality */
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#define GPIO_LPI2C1_SCL_RESET (GPIO_PORT1 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ONE)
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#define GPIO_LPI2C1_SDA_RESET (GPIO_PORT1 | GPIO_PIN1 | GPIO_OUTPUT | GPIO_OUTPUT_ONE)
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/* LPSPIs */
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#define MUX_LPSPI1_SCK IOMUX_CFG(IOMUXC_PAD_SAI1_TXD0_LPSPI1_SCK, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON)
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#define MUX_LPSPI1_MOSI IOMUX_CFG(IOMUXC_PAD_SAI1_RXD0_LPSPI1_SOUT, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON)
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#define MUX_LPSPI1_MISO IOMUX_CFG(IOMUXC_PAD_SAI1_TXC_LPSPI1_SIN, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON)
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/* SPI CS */
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#define MUX_LPSPI1_CS IOMUX_CFG(IOMUXC_PAD_SAI1_TXFS_GPIO1_IO11, IOMUX_GPIO_DEFAULT, IOMUXC_MUX_SION_ON)
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#define GPIO_LPSPI1_CS (GPIO_PORT1 | GPIO_PIN11 | GPIO_OUTPUT | GPIO_OUTPUT_ONE)
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/* FlexCAN */
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#define GPIO_FLEXCAN1_TX IOMUX_CFG(IOMUXC_PAD_PDM_CLK_CAN1_TX, IOMUX_GPIO_DEFAULT, IOMUXC_MUX_SION_ON)
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#define GPIO_FLEXCAN1_RX IOMUX_CFG(IOMUXC_PAD_PDM_BIT_STREAM0_CAN1_RX, IOMUX_GPIO_DEFAULT, IOMUXC_MUX_SION_ON)
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#define GPIO_FLEXCAN2_TX IOMUX_CFG(IOMUXC_PAD_GPIO_IO25_CAN2_TX, IOMUX_GPIO_DEFAULT, IOMUXC_MUX_SION_ON)
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#define GPIO_FLEXCAN2_RX IOMUX_CFG(IOMUXC_PAD_GPIO_IO27_CAN2_RX, IOMUX_GPIO_DEFAULT, IOMUXC_MUX_SION_ON)
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/* Set the PLL clocks as follows:
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*
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* - OSC24M : 24 MHz
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* - ARMPLL_OUT : 1692 MHz
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* - DRAMPLL : 933 MHz
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* - SYSPLL1 : 4000 MHz
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* - SYSPLL_PFD0 : 1000 MHz
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* - SYSPLL_PFD1 : 800 MHz
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* - SYSPLL_PFD2 : 625 MHz
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* - AUDIOPLL_OUT : OFF
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* - VIDEOPLL_OUT : OFF
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*
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* After reset all clock sources (OSCPLL) and root clocks (CLOCK_ROOT) are
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* running, but gated (LPCG).
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*
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* By default, all peripheral root clocks are set to the 24 MHz oscillator.
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*/
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#define ARMPLL_CFG PLL_CFG(IMX95_ARMPLL_BASE, false, PLL_PARMS(1, 2, 141, 0, 0))
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#define DRAMPLL_CFG PLL_CFG(IMX95_DRAMPLL_BASE, true, PLL_PARMS(1, 2, 155, 1, 2))
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#define PLL_CFGS \
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{ \
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PLL_CFG(IMX95_SYSPLL_BASE, true, PLL_PARMS(1, 4, 166, 2, 3)), \
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}
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#define PFD_CFGS \
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{ \
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PFD_CFG(IMX95_SYSPLL_BASE, 0, PFD_PARMS(4, 0, true)), \
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PFD_CFG(IMX95_SYSPLL_BASE, 1, PFD_PARMS(5, 0, true)), \
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PFD_CFG(IMX95_SYSPLL_BASE, 2, PFD_PARMS(6, 2, true)), \
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}
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_IMX9_IMX95_EVK_INCLUDE_BOARD_H */
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