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e96fb6b118
Includes a Mini-UART NSH console for the 4B, tested on the 4GB RAM model. Part of an I2C driver which can only read, boiler-plate for a SPI driver, and a GPIO driver with limited pins. Some tools are present for automatically fetching the boot files and creating the `config.txt` file based on selected Kconfig options.
112 lines
3.6 KiB
C
112 lines
3.6 KiB
C
/****************************************************************************
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* arch/arm64/include/bcm2711/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_INCLUDE_BCM2711_CHIP_H
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#define __ARCH_ARM64_INCLUDE_BCM2711_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Number of bytes in x kilobytes/megabytes/gigabytes */
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#define KB(x) ((x) << 10)
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#define MB(x) (KB(x) << 10)
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#define GB(x) (MB(UINT64_C(x)) << 10)
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/* TODO: config option for low peripheral mode */
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/* TODO: config option for GIC400 interrupt controller or legacy one */
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/* GIC-400 base address.
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* The GIC-400 uses GICv2 architecture.
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*/
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#if defined(CONFIG_BCM2711_LOW_PERIPHERAL)
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/* Low peripheral GIC address */
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#define BCM_GIC400_BASEADDR 0xff840000
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#else
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/* Used for both 35-bit addressing and legacy mode. */
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#define BCM_GIC400_BASEADDR 0x4c0040000
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#endif // defined(CONFIG_BCM2711_LOW_PERIPHERAL)
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#define BCM_GIC400_DISTOFFSET 0x00001000 /* Distributor */
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#define BCM_GIC400_RDISTOFFSET 0x00002000 /* CPU Interfaces */
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#define CONFIG_GICD_BASE (BCM_GIC400_BASEADDR + BCM_GIC400_DISTOFFSET)
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#define CONFIG_GICR_BASE (BCM_GIC400_BASEADDR + BCM_GIC400_RDISTOFFSET)
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#define CONFIG_GICR_OFFSET BCM_GIC400_RDISTOFFSET
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/* BCM2711 memory map: RAM and Device I/O
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* TODO: verify and test against all variants (1, 2, 4 & 8GB)
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*/
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#define CONFIG_RAMBANK1_ADDR (0x000000000)
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/* Both the 4GB and 8GB ram variants use all the size in RAMBANK1 */
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#if defined(CONFIG_RPI4B_RAM_4GB) || defined(CONFIG_RPI4B_RAM_8GB)
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#define CONFIG_RAMBANK1_SIZE GB(4) - MB(64)
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#endif /* defined(CONFIG_RPI4B_RAM_4GB) || defined(CONFIG_RPI4B_RAM_8GB) */
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/* The 8GB version begins to use a second RAM bank.
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* TODO: verify this works on 8GB
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*/
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#if defined(CONFIG_RPI4B_RAM_8GB)
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#define CONFIG_RAMBANK2_ADDR (0x100000000)
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#define CONFIG_RAMBANK2_SIZE GB(4)
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#endif /* defined(CONFIG_RPI4B_RAM_8GB) */
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/* TODO: for low peripheral mode this is valid, otherwise it might change */
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#define CONFIG_DEVICEIO_BASEADDR (0x0fc000000)
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#define CONFIG_DEVICEIO_SIZE MB(64)
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/* Raspberry Pi 4B loads NuttX at this address */
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#define CONFIG_LOAD_BASE 0x480000
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#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff)
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/****************************************************************************
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* Assembly Macros
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****************************************************************************/
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#ifdef __ASSEMBLY__
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.macro get_cpu_id xreg0
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mrs \xreg0, mpidr_el1
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ubfx \xreg0, \xreg0, #0, #8
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM64_INCLUDE_BCM2711_CHIP_H */
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