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https://github.com/apache/nuttx.git
synced 2026-08-07 05:27:17 +00:00
b561b4459b
copied over files, not modified properly yet Squashing lots of define errors to get ethernet.c working quick path rename Fix STM32_EMAC_BASE (and ICACHE/DCACHE Bases). Enable ETH, ETHTX, and ETHRX with CONFIG_STM32H5_ETHMAC (like H7 does). Fixed stm32_get_uniqueid Previously, an exception occurred as a result of calling this function. The problem turned out to be this line: uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i);. Dereferencing a 32-bit register as a 8-bit register seemed to be causing this issue. I think this function is better anyway, fewer register accesses and loop iterations. Turn on SBS peripheral when using Ethernet The SBS peripheral is required to be turned on because the ETH_SEL_PHY bits need to be set. Without turning this on, RMII mode is not possible. MII may not work either. Style Updates
112 lines
5.6 KiB
C
112 lines
5.6 KiB
C
/****************************************************************************
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* arch/arm/include/stm32h5/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32H5_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32H5_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
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# define STM32H5_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */
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# define STM32H5_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */
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# define STM32H5_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */
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#elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
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# define STM32H5_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */
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# define STM32H5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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# define STM32H5_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */
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#else
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# error "Unsupported STM32H5 chip"
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#endif
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#define STM32H5_NFSMC (1) /* Have FSMC memory controller */
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#define STM32H5_NATIM (2) /* Two advanced timers TIM1 and TIM8 */
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#define STM32H5_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */
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#define STM32H5_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */
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#define STM32H5_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */
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#define STM32H5_NBTIM (2) /* Two basic timers, TIM6-7 */
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#define STM32H5_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */
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#define STM32H5_NRNG (1) /* Random number generator (RNG) */
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#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
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# define STM32H5_NUART (6) /* UART 4-5, 7-8, 9, 12 */
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# define STM32H5_NUSART (5) /* USART 1-3, 6, 10-11 */
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#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
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# define STM32H5_NUART (2) /* UART 4-5 */
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# define STM32H5_NUSART (4) /* USART 1-3, 6*/
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#endif
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#define STM32H5_NLPUART (1) /* LPUART 1 */
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#define STM32H5_QSPI (0) /* No QuadSPI1 */
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#define STM32H5_OCTOSPI (1) /* OCTOSPI1*/
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#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
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# define STM32H5_NSPI (6) /* SPI1-SPI6 */
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# define STM32H5_NI2C (4) /* I2C1-4 */
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#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
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# define STM32H5_NSPI (3) /* SPI1-SPI3 */
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# define STM32H5_NI2C (3) /* I2C1-3 */
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#endif
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#define STM32H5_NSWPMI (0) /* No SWPMI1 */
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#define STM32H5_NUSBOTGFS (0) /* USB OTG FS */
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#define STM32H5_NUSBFS (1) /* No USB FS */
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#define STM32H5_NCAN (2) /* CAN1 */
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#define STM32H5_NSAI (2) /* SAI1-2 */
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#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
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# define STM32H5_NSDMMC (2) /* SDMMC interface */
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#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
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# define STM32H5_NSDMMC (1) /* SDMMC interface */
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#endif
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#define STM32H5_NDMA (2) /* DMA1-2 */
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#define STM32H5_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */
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#define STM32H5_NADC (2) /* 12-bit ADC1, up to 20 channels */
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#define STM32H5_NDAC (1) /* 12-bit DAC1 */
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#define STM32H5_NCRC (1) /* CRC */
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#define STM32H5_NCOMP (0) /* Comparators */
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#define STM32H5_NOPAMP (0) /* Operational Amplifiers */
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/* NVIC priority levels *****************************************************/
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/* 16 Programmable interrupt levels */
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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#if defined(CONFIG_STM32H5_HAVE_ETHERNET)
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# define STM32H5_NETHERNET 1 /* Ethernet MAC */
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#else
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# define STM32H5_NETHERNET 0 /* No Ethernet MAC */
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */
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