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The RP2350 datasheet (Table 198) states that IRQ priority levels are represented using 4 bits Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
41 lines
1.8 KiB
C
41 lines
1.8 KiB
C
/****************************************************************************
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* arch/arm/include/rp23xx/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_RP23XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_RP23XX_CHIP_H
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds an 8-bit value, but only the upper 4 bits [7:4]
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* are implemented by the processor (NVIC_PRIO_BITS = 4). The lower
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* 4 bits [3:0] are read as zero and ignore writes. A lower numeric value
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* indicates a higher interrupt priority.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits [7:4] set: lowest priority (15) */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint: priority level 8 */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* All bits [7:4] cleared: highest priority (0) */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* One step per priority level */
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#define ARMV8M_PERIPHERAL_INTERRUPTS 52
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#endif /* __ARCH_ARM_INCLUDE_RP23XX_CHIP_H */
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