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f4b6cf2b9f
Add basic support for RA4M1. The following perpheral are added: * GPIO * SCI (UART) * Clock (Just internal clock - HOCO) Signed-off-by: leocafonso <leocafonso@gmail.com>
87 lines
3.5 KiB
C
87 lines
3.5 KiB
C
/****************************************************************************
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* arch/arm/include/ra4/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_RA_CHIP_H
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#define __ARCH_ARM_INCLUDE_RA_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip */
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/* RA Family */
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/* Common FEATURES
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* Flash 256KB
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* DataFlash 8KB
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* SRAM 32+16KB
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*/
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/* Internal memory */
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# define RA_FLASH_SIZE (256*1024) /* 256KB */
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# define RA_SRAM0_SIZE (48*1024) /* 48KB */
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/* FEATURE R7FA4M1ABxxFP R7FA4M1ABxxLJ R7FA4M1ABxxFM R7FA4M1ABxxNB
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* ----------- ------------- ------------- ------------- -------------
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* Package LQFP100 LGA100 LQFP64 QFNP64
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* No. PIOs 81 81 49 49
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* SCI 4 4 4 4
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*
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* FEATURE R7FA4M1ABxxFL R7FA4M1ABxxNE R7FA4M1ABxxNF
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* ----------- ------------- ------------- -------------
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* Package LQFP48 QFNP48 QFN40
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* No. PIOs 33 33 25
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* SCI 4 4 4
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*/
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0-15. The lower the value, the
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* greater the priority of the corresponding interrupt. The processor
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* implements only bits[7:4] of each field, bits[3:0] read as zero and ignore
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* writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_RA_CHIP_H */
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