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a84257c885
- Add support for i.MX95 M7 core - Interprocessor communication by RPMSG and SCMI - Drivers available for UART, SPI, I2C, CAN, IO and timers
80 lines
3.2 KiB
C
80 lines
3.2 KiB
C
/****************************************************************************
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* arch/arm/include/imx9/irq.h
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-FileCopyrightText: 2024 NXP
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_IMX9_IRQ_H
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#define __ARCH_ARM_INCLUDE_IMX9_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
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# include <arch/imx9/imx95_irq.h>
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#else
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# error "Unrecognized i.MX9 architecture"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words
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* of memory in the IRQ to handle mapping tables.
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*/
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/* Common Processor Exceptions (vectors 0-15) */
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#define IMX9_IRQ_RESERVED (0) /* Reserved vector .. only used with
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* CONFIG_DEBUG_FEATURES */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset(not handled by IRQ) */
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#define IMX9_IRQ_NMI (2) /* Vector 2: Non-Maskable Int (NMI) */
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#define IMX9_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define IMX9_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define IMX9_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define IMX9_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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/* Vectors 7-10: Reserved */
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#define IMX9_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define IMX9_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define IMX9_IRQ_PENDSV (14) /* Vector 14: Pendable SSR */
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#define IMX9_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* Chip-Specific External interrupts */
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#define IMX9_IRQ_EXTINT (16) /* Vector number of the first ext int */
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#define ARMV7M_PERIPHERAL_INTERRUPTS IMX9_IRQ_NEXTINT
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#endif /* __ARCH_ARM_INCLUDE_IMX9_IRQ_H */
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