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8d50457dfc
Most tools used for compliance and SBOM generation use SPDX identifiers This change brings us a step closer to an easy SBOM generation. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
129 lines
5.2 KiB
C
129 lines
5.2 KiB
C
/****************************************************************************
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* arch/xtensa/src/esp32/hardware/esp32_pid.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_PID_H_
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#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_PID_H_
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define REG_PIDCTRL_BASE 0x3ff1f000
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/* Bits 1..7: 1 if interrupt will be triggering PID change */
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#define PIDCTRL_INTERRUPT_ENABLE_REG ((REG_PIDCTRL_BASE) + 0x000)
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/* PIDCTRL_INTERRUPT_ENABLE : R/W; bitpos: [7:1]; default: 0;
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* These bits are used to enable interrupt identification and processing.
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*/
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#define PIDCTRL_INTERRUPT_ENABLE 0x0000007f
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#define PIDCTRL_INTERRUPT_ENABLE_M (PIDCTRL_INTERRUPT_ENABLE_V << PIDCTRL_INTERRUPT_ENABLE_S)
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#define PIDCTRL_INTERRUPT_ENABLE_V 0x0000007f
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#define PIDCTRL_INTERRUPT_ENABLE_S 1
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/* Vectors for the various interrupt handlers */
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#define PIDCTRL_INTERRUPT_ADDR_1_REG ((REG_PIDCTRL_BASE) + 0x004)
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#define PIDCTRL_INTERRUPT_ADDR_2_REG ((REG_PIDCTRL_BASE) + 0x008)
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#define PIDCTRL_INTERRUPT_ADDR_3_REG ((REG_PIDCTRL_BASE) + 0x00c)
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#define PIDCTRL_INTERRUPT_ADDR_4_REG ((REG_PIDCTRL_BASE) + 0x010)
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#define PIDCTRL_INTERRUPT_ADDR_5_REG ((REG_PIDCTRL_BASE) + 0x014)
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#define PIDCTRL_INTERRUPT_ADDR_6_REG ((REG_PIDCTRL_BASE) + 0x018)
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#define PIDCTRL_INTERRUPT_ADDR_7_REG ((REG_PIDCTRL_BASE) + 0x01c)
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/* Delay, in CPU cycles, before switching to new PID */
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#define PIDCTRL_PID_DELAY_REG ((REG_PIDCTRL_BASE) + 0x020)
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/* PIDCTRL_PID_DELAY : R/W; bitpos: [11:0]; default: 20;
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* Delay until newly assigned PID is valid.
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*/
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#define PIDCTRL_PID_DELAY 0x00001fff
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#define PIDCTRL_PID_DELAY_M (PIDCTRL_PID_DELAY_V << PIDCTRL_PID_DELAY_S)
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#define PIDCTRL_PID_DELAY_V 0x00001fff
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#define PIDCTRL_PID_DELAY_S 0
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#define PIDCTRL_NMI_DELAY_REG ((REG_PIDCTRL_BASE) + 0x024)
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/* PIDCTRL_NMI_DELAY : R/W; bitpos: [11:0]; default: 16;
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* Delay for disabling CPU NMI interrupt mask signal.
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*/
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#define PIDCTRL_NMI_DELAY 0x00001fff
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#define PIDCTRL_NMI_DELAY_M (PIDCTRL_NMI_DELAY_V << PIDCTRL_NMI_DELAY_S)
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#define PIDCTRL_NMI_DELAY_V 0x00001fff
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#define PIDCTRL_NMI_DELAY_S 0
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/* Last detected interrupt. Set by hw on int. */
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#define PIDCTRL_LEVEL_REG ((REG_PIDCTRL_BASE) + 0x028)
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/* PID/prev int data for each int */
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#define PIDCTRL_FROM_REG(i) ((REG_PIDCTRL_BASE) + 0x028 + (0x4 * i))
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#define PIDCTRL_FROM_1_REG ((REG_PIDCTRL_BASE) + 0x02c)
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#define PIDCTRL_FROM_2_REG ((REG_PIDCTRL_BASE) + 0x030)
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#define PIDCTRL_FROM_3_REG ((REG_PIDCTRL_BASE) + 0x034)
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#define PIDCTRL_FROM_4_REG ((REG_PIDCTRL_BASE) + 0x038)
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#define PIDCTRL_FROM_5_REG ((REG_PIDCTRL_BASE) + 0x03c)
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#define PIDCTRL_FROM_6_REG ((REG_PIDCTRL_BASE) + 0x040)
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#define PIDCTRL_FROM_7_REG ((REG_PIDCTRL_BASE) + 0x044)
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/* PIDCTRL_FROM_INT : R/W; bitpos: [6:3]; default: 0;
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* Interrupt status of the system before the interrupt occurs.
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*/
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#define PIDCTRL_FROM_INT 0x0000000f
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#define PIDCTRL_FROM_INT_M (PIDCTRL_FROM_INT_V << PIDCTRL_FROM_INT_S)
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#define PIDCTRL_FROM_INT_V 0x0000000f
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#define PIDCTRL_FROM_INT_S 3
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/* PIDCTRL_FROM_PID : R/W; bitpos: [2:0]; default: 0;
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* Process running on the CPU before the interrupt occurs.
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*/
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#define PIDCTRL_FROM_PID 0x00000007
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#define PIDCTRL_FROM_PID_M (PIDCTRL_FROM_PID_V << PIDCTRL_FROM_PID_S)
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#define PIDCTRL_FROM_PID_V 0x00000007
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#define PIDCTRL_FROM_PID_S 0
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/* PID to be set after confirm routine */
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#define PIDCTRL_PID_NEW_REG ((REG_PIDCTRL_BASE) + 0x048)
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/* Write to kick off PID change */
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#define PIDCTRL_PID_CONFIRM_REG ((REG_PIDCTRL_BASE) + 0x04c)
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/* Write to mask NMI */
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#define PIDCTRL_NMI_MASK_ENABLE_REG ((REG_PIDCTRL_BASE) + 0x054)
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/* Write to unmask NMI */
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#define PIDCTRL_NMI_MASK_DISABLE_REG ((REG_PIDCTRL_BASE) + 0x058)
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#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_PID_H_ */
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