Tyler Bennett 54b7bf6e36 ADC Hardware register file updated for G0 ... First commit of ADC for G0. Have it working basically. Need to make changes regarding adccmn stuff. Added changes to make stm32_adc.c compatible with both G0 and other families. Add oversampling support. This is for G0 and L0. Add ADC oversampling to Kconfig. Use adccmn_modifyreg for all, updated hw file to accomodate G0. Style fixes. Move init of oversampling to a function, and call it if OVERSAMPLE is configured. Limited changes to stm32_bringup.c Style fixes to hardware/stm32_adc.h Changed nucleo-g0b1re to run at 64 MHz. Fixed errors in clock setup. Added defines for setting up ADC clock. Added code for STM32G0 ADC clock configuration. Added adc_ckmode_cfg function. ckmode bits were previously neglected, assuming async clock to ADC was used. Added other feedback from pull request #16500. Added feedback from pull request #16500. Changed format of STM32F0L0G0_HAVE_ADC_OVERSAMPLE config. Removed FARs from ioc_set_oversample. Fixed formatting of helps in Kconfig. Adjusted spacing on help content. Simplified adc_common_cfg. CCR_PRESC relies on board.h Fixed formatting Add ADC pinmaps for stm32g0		2025-06-17 21:25:39 +08:00
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include	arch/stm32c0: add FDCAN support	2025-06-09 15:26:12 -03:00
src	ADC Hardware register file updated for G0	2025-06-17 21:25:39 +08:00
CMakeLists.txt	arch/arm: migrate to SPDX identifier	2024-12-06 09:25:23 +08:00
Kconfig	arch/arm/stm32f0l0g0: Add STM32G0 Flash driver.	2025-05-07 21:37:25 -03:00