Justin Erenkrantz d98e7a7b68 risc-v/litex: For vexriscv, point docs at linux CPU variant instead of secure. ... The secure CPU variant of vexriscv immediately panics after bring up. However, the linux CPU variant of the vexriscv core does work successfully. Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>		2025-12-13 18:14:21 -03:00
..
arm	docs/stm32f429i-disco: Add the stm32f429i-disco picture	2025-11-27 18:27:46 -03:00
arm64	docs/platforms/raspberrypi-4b: Document cgol configuration	2025-11-14 16:57:10 +01:00
avr	arch/avr/src/avrdx: add support for TWI (I2C and SMBus) peripheral	2025-12-01 19:12:26 +08:00
ceva
hc	style: fix typos	2025-04-30 13:45:46 +08:00
mips	style: fix typos	2025-04-30 13:45:46 +08:00
misco	misco/lm32/boards/misoc: Migrate README.txt to RST	2025-05-08 03:04:04 +02:00
or1k
renesas	docs/rx65n-rsk2mb: Migrate README.txt to rst format	2025-09-12 07:20:04 +02:00
risc-v	risc-v/litex: For vexriscv, point docs at linux CPU variant instead of secure.	2025-12-13 18:14:21 -03:00
sim	docs/platforms/sim/sim/boards/sim: Clean up legacy SIM documentation.	2025-10-24 10:15:24 +02:00
sparc
tricore	board/tricore: rename tc397 chip board name	2025-08-26 16:09:34 +08:00
x86	Documentation: fix spelling	2025-05-15 11:33:41 +08:00
x86_64	boards/x86_64/qemu-intel64: add xHCI support to jumbo configs	2025-05-15 21:58:57 +08:00
xtensa	documentation: update flash encryption docs for Espressif devices	2025-12-11 11:29:26 +01:00
z16
z80
index.rst