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The common mips_cache.S only handles generic L1 cache operations and does not support L2 (secondary) cache operations required for the JZ4780 target. This commit introduces mti_cache.S to support both L1 and L2 cache operations. The mti_cache.S implementation is BSD licensed from Imagination Technologies. Signed-off-by: Lwazi Dube <lwazeh@gmail.com> |
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| .. | ||
| arm | ||
| arm64 | ||
| avr | ||
| dummy | ||
| hc/m9s12 | ||
| mips | ||
| misoc/lm32/misoc | ||
| or1k/mor1kx/or1k | ||
| renesas | ||
| risc-v | ||
| sim/sim/sim | ||
| sparc | ||
| tricore | ||
| x86/qemu/qemu-i486 | ||
| x86_64/qemu/qemu-intel64 | ||
| xtensa | ||
| z16/z16f/z16f2800100zcog | ||
| z80 | ||
| .gitignore | ||
| Board.mk | ||
| boardctl.c | ||
| CMakeLists.txt | ||
| dummy.c | ||
| Kconfig | ||
| Makefile | ||