| .. |
|
espressif
|
arch/xtensa/espressif: Add SHA accelerator features
|
2026-03-16 11:09:49 +08:00 |
|
CMakeLists.txt
|
arch/xtensa: Add support to disable signals actions related data struct
|
2026-01-18 08:24:13 -03:00 |
|
crt0.c
|
arch/crt0.c: revert entry _start
|
2025-12-10 19:06:04 +08:00 |
|
Make.defs
|
arch/xtensa: Add support to disable signals actions related data struct
|
2026-01-18 08:24:13 -03:00 |
|
mpu.h
|
|
|
|
xtensa.h
|
arch/xtensa/src/common: Create SoC-specific initialization routine
|
2026-02-27 08:12:19 -03:00 |
|
xtensa_asm_utils.h
|
|
|
|
xtensa_assert.c
|
style: fix spelling in code comments and strings
|
2025-05-23 10:48:41 +08:00 |
|
xtensa_attr.h
|
|
|
|
xtensa_backtrace.c
|
style: fix spelling in code comments and strings
|
2025-05-23 10:48:41 +08:00 |
|
xtensa_cache.c
|
comments: update text typo pre-empted to preempted
|
2025-05-12 15:01:37 +08:00 |
|
xtensa_checkstack.c
|
arch: rename STACK_ALIGNMENT to STACKFRAME_ALIGN across all architectures
|
2026-01-22 15:37:24 +08:00 |
|
xtensa_context.S
|
xtensa/isa: fix build break if compiler without ISA - XCHAL_HAVE_THREADPTR support
|
2025-07-21 12:56:31 +02:00 |
|
xtensa_coproc.S
|
|
|
|
xtensa_counter.h
|
|
|
|
xtensa_cpenable.c
|
arch/xtensa: replace critical_section with spinlock.
|
2026-02-02 21:17:20 +08:00 |
|
xtensa_cpuinfo.c
|
arch/xtensa: fix build errors related to data types on ESP32|S2|S3
|
2025-04-18 09:32:58 +08:00 |
|
xtensa_cpuint.c
|
xtensa: support more than 32 cpu interrupts
|
2025-07-04 11:26:07 -03:00 |
|
xtensa_createstack.c
|
arch: rename STACK_ALIGNMENT to STACKFRAME_ALIGN across all architectures
|
2026-01-22 15:37:24 +08:00 |
|
xtensa_debug.c
|
arch/xtensa: fix build errors related to data types on ESP32|S2|S3
|
2025-04-18 09:32:58 +08:00 |
|
xtensa_dispatch_syscall.S
|
|
|
|
xtensa_exit.c
|
|
|
|
xtensa_fpucmp.c
|
|
|
|
xtensa_getintstack.c
|
|
|
|
xtensa_hostfs.c
|
|
|
|
xtensa_idle.c
|
|
|
|
xtensa_initialize.c
|
arch/xtensa/src/common: Create SoC-specific initialization routine
|
2026-02-27 08:12:19 -03:00 |
|
xtensa_initialstate.c
|
Revert "arch/xtensa: set PS.EXCM initial value to 1 while new thread created"
|
2025-03-19 11:47:31 -03:00 |
|
xtensa_int_handlers.S
|
arch/xtensa: Add support to disable signals actions related data struct
|
2026-01-18 08:24:13 -03:00 |
|
xtensa_irqdispatch.c
|
arch: fix addrenv_switch changing this_task causing exceptions
|
2026-01-17 18:23:06 -03:00 |
|
xtensa_loadstore.S
|
|
|
|
xtensa_lowputs.c
|
|
|
|
xtensa_macros.S
|
|
|
|
xtensa_mm.h
|
|
|
|
xtensa_modifyreg8.c
|
|
|
|
xtensa_modifyreg16.c
|
|
|
|
xtensa_modifyreg32.c
|
|
|
|
xtensa_mpu.c
|
|
|
|
xtensa_nputs.c
|
|
|
|
xtensa_oneshot.c
|
arch/xtensa: replace critical_section with spinlock.
|
2026-02-02 21:17:20 +08:00 |
|
xtensa_panic.S
|
|
|
|
xtensa_perf.c
|
arch: Flag all definitions of up_perf_* functions with CONFIG_ARCH_HAVE_PERF_EVENTS
|
2025-06-06 17:31:10 +08:00 |
|
xtensa_pthread_start.c
|
|
|
|
xtensa_registerdump.c
|
|
|
|
xtensa_releasestack.c
|
|
|
|
xtensa_saveusercontext.c
|
xtensa/isa: fix build break if compiler without ISA - XCHAL_HAVE_THREADPTR support
|
2025-07-21 12:56:31 +02:00 |
|
xtensa_schedsigaction.c
|
sched/signal: Optimize code logic
|
2026-01-27 21:24:31 +08:00 |
|
xtensa_sigdeliver.c
|
arch/xtensa: Fix a race condition in xtensa_sig_deliver for SMP
|
2025-08-01 08:54:39 -03:00 |
|
xtensa_signal_dispatch.c
|
arch/xtensa: Add support to disable signals actions related data struct
|
2026-01-18 08:24:13 -03:00 |
|
xtensa_signal_handler.S
|
|
|
|
xtensa_simcall.S
|
|
|
|
xtensa_smpcall.c
|
|
|
|
xtensa_stackframe.c
|
arch: rename STACK_ALIGNMENT to STACKFRAME_ALIGN across all architectures
|
2026-01-22 15:37:24 +08:00 |
|
xtensa_swint.c
|
|
|
|
xtensa_task_start.c
|
|
|
|
xtensa_tcbinfo.c
|
|
|
|
xtensa_timer.h
|
|
|
|
xtensa_tls.c
|
|
|
|
xtensa_user_handler.S
|
|
|
|
xtensa_usestack.c
|
arch: Add stack alignment and stack size checking when CONFIG_TLS_ALIGNED=y
|
2026-01-22 22:18:11 +08:00 |
|
xtensa_vectors.S
|
|
|
|
xtensa_window_vector.S
|
|
|
|
xtensa_windowspill.S
|
|
|