Jacob Dahl 659f47a824 arch/arm/stm32h7/i2c: use per-instance RCC registers for clock and reset ... stm32_i2c_init() and stm32_i2c_deinit() hardcoded APB1LENR/APB1LRSTR while taking the enable and reset bits from the per-instance config. That is correct for I2C1-3, but I2C4 is on APB4: its clk_bit and reset_bit are RCC_APB4ENR_I2C4EN and RCC_APB4RSTR_I2C4RST, both bit 7, and bit 7 of APB1LENR/APB1LRSTR is TIM13. So for I2C4 the driver enabled and pulsed the reset of TIM13 instead, and never reset the I2C4 peripheral at all. I2C4 still works because rcc_enableapb4() enables I2C4EN at boot, but the peripheral reset that stm32_i2c_reset() (CONFIG_I2C_RESET) relies on to clear a wedged I2C state machine never happens, and deinit gates TIM13 while leaving the I2C4 clock running. Store the clock enable and reset register addresses in struct stm32_i2c_config_s next to the bits, and use them in stm32_i2c_init() and stm32_i2c_deinit(). Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>		2026-08-06 08:49:20 -03:00
..
include	!arch/arm: Use r9 as the PIC base register.	2026-08-06 01:38:23 +08:00
src	arch/arm/stm32h7/i2c: use per-instance RCC registers for clock and reset	2026-08-06 08:49:20 -03:00
CMakeLists.txt
Kconfig	arch/arm/rtl8721f: add RTL8721F (Green2) chip and EVB board skeleton	2026-07-30 17:04:14 +08:00