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2c736d0860
The I- and D-Caches were disabled, so all code ran from flash through the prefetch buffer and all data accesses went to SRAM. Enable both caches in nsh and netnsh, and link the data memory in KSEG0 instead of KSEG1 so that it goes through the D-Cache (KSEG0 is uncached when the caches are disabled). CONFIG_BOARD_LOOPSPERMSEC is recalibrated with calib_udelay for the cached configuration. CoreMark (XC32 v6.00, -O2) goes from 82.5 to 544.6 iterations/s. The average ping round trip time drops from 0.74 to 0.56 ms for 64-byte packets and from 1.92 to 0.93 ms for 1400-byte packets. Tested on the EV49N51A with XC32: 5000 pings of 1472 bytes at 2 ms intervals with payload checking, ifdown/ifup cycles, telnet sessions and CoreMark. With Pinguino GCC: 2000 pings of 1472 bytes and 1000 small pings at 3 ms intervals. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| index.rst | ||