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nuttx/boards/xtensa/esp32/common/scripts/mcuboot_sections.ld
Tiago Medicci Serrano c17e16eaed xtensa/espressif: Update common-source integration for Xtensa devices 
This commit updates the common-source integration for Xtensa-based
Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger
common-source update split by architecture for better maintainability.

Major components updated:
- IRQ allocator refactoring with intr_alloc integration
- Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.)
- Espressif components upgrade to release/master.b-test
- Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.)
- Wireless adapters (Wi-Fi and BLE)
- esp_timer migration to the common-source path for Xtensa devices
- Common-source power management implementation (auto-sleep and wakeup paths)
- Board defconfigs for all Xtensa Espressif boards
- SMP support improvements for ESP32-S3
- Critical section handling improvements

Key architectural changes:
- IRQ Allocator: The new interrupt allocator enables multiple mapping
  options from interrupt sources to CPU interrupts, providing flexibility
  required by modern peripherals. Although this introduces breaking changes
  to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE
  Kconfig option is explicitly checked during startup to ensure proper
  configuration. This validation prevents runtime issues from configuration
  mismatches.
- Xtensa-specific interrupt handling via esp_xtensa_intr.c providing
  NuttX-native implementations of xt_ints_on/off and interrupt handlers,
  avoiding conflicts with NuttX's core Xtensa macros.
- Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific
  RTC/RT-timer code to common-source Espressif integration, including
  esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates.
- Power management consolidation: Xtensa PM follows the common-source
  implementation, including common-source auto-sleep behavior, UART/Wi-Fi
  wakeup coordination, and tickless-safe sleep flow compatibility.

Note: This is a large commit to maintain bisectability. Breaking the
changes into smaller commits would result in non-building intermediate
states across the common-source infrastructure update.

Tested configurations:
- All defconfigs were tested, including `ostest`.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-03-29 00:33:11 +08:00

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/****************************************************************************
* boards/xtensa/esp32/common/scripts/mcuboot_sections.ld
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Default entry point: */
ENTRY(__start);
SECTIONS
{
.metadata :
{
/* Magic for load header */
LONG(0xace637d3)
/* Application entry point address */
KEEP(*(.entry_addr))
/* IRAM metadata:
* - Destination address (VMA) for IRAM region
* - Flash offset (LMA) for start of IRAM region
* - Size of IRAM region
*/
LONG(ADDR(.iram0.vectors))
LONG(LOADADDR(.iram0.vectors))
LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors))
/* DRAM metadata:
* - Destination address (VMA) for DRAM region
* - Flash offset (LMA) for start of DRAM region
* - Size of DRAM region
*/
LONG(ADDR(.dram0.data))
LONG(LOADADDR(.dram0.data))
LONG(SIZEOF(.dram0.data))
} >metadata
_image_drom_vma = ADDR(.flash.rodata);
_image_drom_lma = LOADADDR(.flash.rodata);
_image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma;
.flash.rodata :
{
. = ALIGN(4);
_srodata = ABSOLUTE(.);
*(EXCLUDE_FILE (*libarch.a:esp32_spiflash.* esp32_start.*
*libarch.a:*esp_loader.*
*libarch.a:*uart_hal.*
*libarch.a:*mmu_hal.*
) .rodata)
*(EXCLUDE_FILE (*libarch.a:esp32_spiflash.* esp32_start.*
*libarch.a:*esp_loader.*
*libarch.a:*uart_hal.*
*libarch.a:*mmu_hal.*
) .rodata.*)
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
_sinit = ABSOLUTE(.);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
_einit = ABSOLUTE(.);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* This table MUST be 4-byte aligned */
_erodata = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
} >drom0_0_seg AT>ROM
/* Send .iram0 code to iram */
.iram0.vectors :
{
/* Vectors go to IRAM */
_init_start = ABSOLUTE(.);
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
. = 0x0;
KEEP (*(.window_vectors.text));
. = 0x180;
KEEP (*(.xtensa_level2_vector.text));
. = 0x1c0;
KEEP (*(.xtensa_level3_vector.text));
. = 0x200;
KEEP (*(.xtensa_level4_vector.text));
. = 0x240;
KEEP (*(.xtensa_level5_vector.text));
. = 0x280;
KEEP (*(.debug_exception_vector.text));
. = 0x2c0;
KEEP (*(.nmi_vector.text));
. = 0x300;
KEEP (*(.kernel_exception_vector.text));
. = 0x340;
KEEP (*(.user_exception_vector.text));
. = 0x3c0;
KEEP (*(.double_exception_vector.text));
. = 0x400;
*(.*_vector.literal)
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
_init_end = ABSOLUTE(.);
} >iram0_0_seg AT>ROM
.iram0.text :
{
/* Code marked as running out of IRAM */
_iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*)
esp32_start.*(.literal .text .literal.* .text.*)
*libphy.a:(.literal .text .literal.* .text.*)
*librtc.a:(.literal .text .literal.* .text.*)
*libpp.a:(.literal .text .literal.* .text.*)
*libhal.a:(.literal .text .literal.* .text.*)
*libarch.a:esp32_spiflash.*(.literal .text .literal.* .text.*)
*libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_loader.*(.text .text.* .literal .literal.*)
*libc.a:sq_remlast.*(.literal .text .literal.* .text.*)
*libc.a:arch_atomic.*(.literal .text .literal.* .text.*)
*(.wifirxiram .wifirxiram.*)
*(.wifirxiram .wifi0iram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
*(.phyiram .phyiram.*)
_iram_text_end = ABSOLUTE(.);
/* IRAM heap starts at the end of iram0_0_seg */
. = ALIGN (4);
_siramheap = ABSOLUTE(.);
} >iram0_0_seg AT>ROM
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
/* .bss initialized on power-up */
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
_sbss = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
KEEP (*(.bss))
*(.bss.*)
*(.share.mem)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(8);
_ebss = ABSOLUTE(.);
_bss_end = ABSOLUTE(.);
} >dram0_0_seg
.noinit (NOLOAD):
{
/* This section contains data that is not initialized during load,
* or during the application's initialization sequence.
*/
. = ALIGN(8);
*(.noinit)
*(".noinit.*")
. = ALIGN(8);
} >dram0_0_seg
.dram0.data :
{
/* .data initialized on power-up in ROMed configurations. */
_sdata = ABSOLUTE(.);
KEEP (*(.data))
KEEP (*(.data.*))
KEEP (*(.gnu.linkonce.d.*))
KEEP (*(.data1))
KEEP (*(.sdata))
KEEP (*(.sdata.*))
KEEP (*(.gnu.linkonce.s.*))
KEEP (*(.sdata2))
KEEP (*(.sdata2.*))
KEEP (*(.gnu.linkonce.s2.*))
KEEP (*(.jcr))
*(.dram1 .dram1.*)
esp32_start.*(.rodata .rodata.*)
*libarch.a:esp32_spiflash.*(.rodata .rodata.*)
*libarch.a:*esp_loader.*(.rodata .rodata.*)
*libarch.a:*mmu_hal.*(.rodata .rodata.*)
*libarch.a:*uart_hal.*(.rodata .rodata.*)
*libc.a:arch_atomic.*(.rodata .rodata.*)
_edata = ABSOLUTE(.);
. = ALIGN(4);
/* Heap starts at the end of .data */
_sheap = ABSOLUTE(.);
} >dram0_0_seg AT>ROM
/* External memory bss, from any global variable with EXT_RAM_ATTR attribute */
.extmem.bss (NOLOAD) :
{
_sbss_extmem = ABSOLUTE(.);
*(.extmem.bss .extmem.bss.*)
. = ALIGN(4);
_ebss_extmem = ABSOLUTE(.);
} >extmem_seg
_image_irom_vma = ADDR(.flash.text);
_image_irom_lma = LOADADDR(.flash.text);
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
/* The alignment of the ".flash.text" output section is forced to
* 0x00010000 (64KB) to ensure that it will be allocated at the beginning
* of the next available Flash block.
* This is required to meet the following constraint from the external
* flash MMU:
* VMA % 64KB == LMA % 64KB
* i.e. the lower 16 bits of both the virtual address (address seen by the
* CPU) and the load address (physical address of the external flash) must
* be equal.
*/
.flash.text : ALIGN(0x00010000)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram.*)
*(.wifiextrairam .wifiextrairam.*)
*(EXCLUDE_FILE(*libpp.a) .wifiorslpiram EXCLUDE_FILE(*libpp.a) .wifiorslpiram.*)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram.*)
. = ALIGN(4);
_text_end = ABSOLUTE(.);
_etext = .;
} >irom0_0_seg AT>ROM
.rtc.text :
{
. = ALIGN(4);
*(.rtc.literal .rtc.text)
} >rtc_iram_seg AT>ROM
.rtc.data :
{
*(.rtc.data)
*(.rtc.data.*)
*(.rtc.rodata)
*(.rtc.rodata.*)
/* Whatever is left from the RTC memory is used as a special heap. */
. = ALIGN (4);
_srtcheap = ABSOLUTE(.);
} >rtc_slow_seg AT>ROM
}
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