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a1x
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am335x
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arch/arm/include/amm335x: Trivial, cosmetic changes after review
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2019-01-08 08:15:04 -06:00 |
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arm
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Squashed commit of the following:
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2019-04-29 14:52:05 -06:00 |
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armv6-m
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Squashed commit of the following:
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2019-04-29 14:52:05 -06:00 |
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armv7-a
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Squashed commit of the following:
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2019-04-29 14:52:05 -06:00 |
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armv7-m
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arch/arm/include/armv7-m/syscall.h: ARM EABI specifies that the stack should be aligned by 8 on function calls, inside the function is not required to be aligned by 8. Since these functions call svc, compiler doesn't know that the svc is a function, therefore it does not do any stack management. This change pushes an even number of args to the stack and maintains an 8 byte alignment. I've checked the assembly and it doesn't cause any more overhead that the hand written assembly.
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2019-12-16 09:10:08 -06:00 |
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armv7-r
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Squashed commit of the following:
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2019-04-29 14:52:05 -06:00 |
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c5471
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cxd56xx
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arch/arm/include/cxd56xx/audio.h: Fix minor typos
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2020-01-14 20:57:29 -03:00 |
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dm320
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efm32
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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imx1
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imx6
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Fix lots of typos in C comments and Kconfig help text
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2018-07-08 18:24:45 -06:00 |
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imxrt
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Merged imxrt1020 into master
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2019-04-30 16:08:46 -06:00 |
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kinetis
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Merged in dagar/nuttx/pr-kinetic_minor_fix (pull request #820)
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2019-01-19 15:39:46 +00:00 |
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kl
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arch/: Clean up some naming and spacing.
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2018-06-20 15:38:06 -06:00 |
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lc823450
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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lpc17xx_40xx
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Merged in jjlange/nuttx/lpc40xx (pull request #946)
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2019-07-11 16:50:00 +00:00 |
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lpc31xx
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lpc43xx
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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lpc54xx
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symtab/Makefile: When system wide locale is set (i.e. en_US.UTF-8) then 'read' is ordered after 'readdir' even if separator is set to quotation mark and key set to 2. When C locale is used result is correct.
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2019-08-14 11:02:30 -06:00 |
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lpc214x
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lpc2378
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max326xx
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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moxart
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nrf52
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Merged in raiden00/nuttx_nrf52 (pull request #1098)
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2019-12-19 15:40:56 +00:00 |
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nuc1xx
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Cosmetic changes to spacing and comments.
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2017-04-20 14:08:08 -06:00 |
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s32k1xx
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arch/arm/src/s32k1xx: This commit brings in the LPSPI and LPI2C peripheral drivers from the i.MXRT which used the identical IP.
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2019-08-21 11:18:40 -06:00 |
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sam34
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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sama5
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samd2l2
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arch/arm/include/samd2l2/sam_adc.h: I was wrong... this header file does belong in the samd2l2 include directory. It contains IOCTL definitions that are needed by applications. Usage of a chip-specific header file is, however, not really a good portable design because it requires that the application know that it is running on a specific chip. But still, if we are going to do that, the include directory is where the header file belongs. My apologies for the bad judgement.
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2019-12-16 03:53:05 -06:00 |
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samd5e5
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Author: Gregory Nutt <gnutt@nuttx.org>
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2020-01-02 12:35:45 -06:00 |
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samv7
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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stm32
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Merged in raiden00/nuttx_pe (pull request #796)
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2019-01-02 12:12:28 +00:00 |
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stm32f0l0g0
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Add support for STM32G070xx
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2019-09-17 11:10:38 -06:00 |
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stm32f7
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Fixed a compilation error, with irq debugging for stm32f7 and stm32h7 archs.
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2020-01-05 21:24:16 +00:00 |
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stm32h7
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Squashed commit of the following:
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2020-01-02 12:17:16 -03:00 |
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stm32l4
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Fixed STM32L4_NUSART for STM32L433XX. (#9)
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2019-12-31 07:47:06 -06:00 |
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str71x
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tiva
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arch/arm/include/tiva/tm4c_irq.h: Fix wrong IRQ vector number.
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2019-11-06 20:43:51 -06:00 |
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tms570
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arch/arm/include/tms570, arm/src/armv7-r, and arm/src/tms570: Adds support for the TMS570LS3137ZWT and corrects seversl ARMv7-R and TMS570 issues
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2018-04-18 08:58:36 -06:00 |
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xmc4
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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.gitignore
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arch.h
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elf.h
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arch/arm/include/syscall.h: Add missing inclusion of arch/armv7-r/syscall.h for CortexR.
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2019-01-26 07:43:31 -06:00 |
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inttypes.h
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Add architecture-specific inttypes.h
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2016-10-27 16:01:38 -04:00 |
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irq.h
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arch/arm: Add the initial cortex-a7 archtiecture support
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2019-03-19 11:51:29 -06:00 |
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limits.h
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setjmp.h
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arch/arm/include/setjmp.h: Add prototypes for setjmp/longjmp functions.
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2019-11-17 08:48:17 -06:00 |
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spinlock.h
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Fix some typos
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2019-09-17 10:46:23 -06:00 |
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stdarg.h
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syscall.h
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arch/arm: Add the initial cortex-a7 archtiecture support
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2019-03-19 11:51:29 -06:00 |
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tls.h
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types.h
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