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a0fcbb7957
Rewrite arch_memcpy.S and arch_memset.S to be register-width aware on both RV32 and RV64 using REG_L/REG_S/SZREG macros from asm.h. memcpy gains: - 16xSZREG unrolled main loop (128B/iter on RV64, 64B on RV32). - Shift-merge path for misaligned src: reads two aligned words straddling each output word and shifts them together, so no load or store is ever misaligned. - Single SZREG and byte loops for remainder and small copies. memset gains: - 32xSZREG unrolled main loop (256B/iter on RV64, 128B on RV32) using Duff's device for non-power-of-two remainders. - .option norvc ensures fixed 4-byte instruction width for correct jump offset calculation in the Duff's device entry. - Zero-length input handled correctly (branch to guarded tail). The old memcpy always used lw/sw even on RV64, wasting half the memory bandwidth. The old memset unrolled only 16 bytes per iteration. Signed-off-by: ganjing <ganjing@xiaomi.com>
132 lines
2.9 KiB
ArmAsm
132 lines
2.9 KiB
ArmAsm
/****************************************************************************
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* libs/libc/machine/risc-v/arch_memset.S
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*
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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* SPDX-FileCopyrightText: 2017 SiFive Inc. All rights reserved.
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*
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* This copyrighted material is made available to anyone wishing to use,
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* modify, copy, or redistribute it subject to the terms and conditions
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* of the FreeBSD License. This program is distributed in the hope that
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* it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
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* including the implied warranties of MERCHANTABILITY or FITNESS FOR
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* A PARTICULAR PURPOSE. A copy of this license is available at
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* http://www.opensource.org/licenses.
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*
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****************************************************************************/
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#include "libc.h"
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#ifdef LIBC_BUILD_MEMSET
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#include "asm.h"
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.text
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.global ARCH_LIBCFUN(memset)
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.type ARCH_LIBCFUN(memset), @function
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.align 2
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/************************************************************************************
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* Name: memset
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*
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* void *memset(void *s, int c, size_t n)
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*
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* Optimized with 32xSZREG unrolled loop and .option norvc.
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************************************************************************************/
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ARCH_LIBCFUN(memset):
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.cfi_sections .debug_frame
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.cfi_startproc
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mv t0, a0
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li t1, 2*SZREG
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bleu a2, t1, .Lbyte_tail
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andi a1, a1, 0xff
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slli t1, a1, 8
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or a1, a1, t1
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slli t1, a1, 16
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or a1, a1, t1
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#ifdef CONFIG_ARCH_RV64
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slli t1, a1, 32
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or a1, a1, t1
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#endif
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andi t1, t0, SZREG-1
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beqz t1, .Laligned
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sub t2, zero, t1
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addi t2, t2, SZREG
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sub a2, a2, t2
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.Lalign_head:
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sb a1, 0(t0)
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addi t0, t0, 1
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addi t2, t2, -1
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bnez t2, .Lalign_head
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.Laligned:
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li t3, 32*SZREG
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bltu a2, t3, .Lword_tail
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.align 3
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.Lblock_loop:
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.option push
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.option norvc
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REG_S a1, 0*SZREG(t0)
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REG_S a1, 1*SZREG(t0)
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REG_S a1, 2*SZREG(t0)
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REG_S a1, 3*SZREG(t0)
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REG_S a1, 4*SZREG(t0)
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REG_S a1, 5*SZREG(t0)
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REG_S a1, 6*SZREG(t0)
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REG_S a1, 7*SZREG(t0)
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REG_S a1, 8*SZREG(t0)
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REG_S a1, 9*SZREG(t0)
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REG_S a1, 10*SZREG(t0)
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REG_S a1, 11*SZREG(t0)
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REG_S a1, 12*SZREG(t0)
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REG_S a1, 13*SZREG(t0)
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REG_S a1, 14*SZREG(t0)
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REG_S a1, 15*SZREG(t0)
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REG_S a1, 16*SZREG(t0)
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REG_S a1, 17*SZREG(t0)
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REG_S a1, 18*SZREG(t0)
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REG_S a1, 19*SZREG(t0)
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REG_S a1, 20*SZREG(t0)
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REG_S a1, 21*SZREG(t0)
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REG_S a1, 22*SZREG(t0)
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REG_S a1, 23*SZREG(t0)
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REG_S a1, 24*SZREG(t0)
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REG_S a1, 25*SZREG(t0)
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REG_S a1, 26*SZREG(t0)
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REG_S a1, 27*SZREG(t0)
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REG_S a1, 28*SZREG(t0)
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REG_S a1, 29*SZREG(t0)
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REG_S a1, 30*SZREG(t0)
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REG_S a1, 31*SZREG(t0)
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.option pop
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addi t0, t0, 32*SZREG
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sub a2, a2, t3
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bgeu a2, t3, .Lblock_loop
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.Lword_tail:
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andi t1, a2, ~(SZREG-1)
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beqz t1, .Lbyte_tail
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add t2, t0, t1
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.Lword_loop:
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REG_S a1, 0(t0)
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addi t0, t0, SZREG
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bltu t0, t2, .Lword_loop
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andi a2, a2, SZREG-1
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.Lbyte_tail:
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beqz a2, .Ldone
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.Lbyte_fill:
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sb a1, 0(t0)
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addi t0, t0, 1
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addi a2, a2, -1
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bnez a2, .Lbyte_fill
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.Ldone:
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ret
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.cfi_endproc
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.size ARCH_LIBCFUN(memset), .-ARCH_LIBCFUN(memset)
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#endif
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