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ba63a4d234
when we build with greenhills compiler, if the exception_common function is put into a separate section: ".text.exception_common", then the address of exception_common function is an even number, for example "0x16a6c", in this case, it will trigger the UsageFaults:INVSTATE error. The reason for this error is that in the GHS compiler, a section declared through the ".section" directive must specify at least the "a" attribute. Otherwise, this section will not be linked into the final file, and this is why the address of exception_common function is invalid. The following is the official explanation in the GHS compiler documentation: "The reason for this error is that in the GHS compiler, a section declared through the .section directive must specify at least the "a" attribute. Otherwise, this section will not be linked into the final file. The following is the official explanation in the documentation: "Sections that are intended be part of the final linked output should have at least the `a` attribute" and for GHS compiler, the .text section is recommended specify the attribute of `ax`. Signed-off-by: guoshichao <guoshichao@xiaomi.com>
418 lines
9.9 KiB
ArmAsm
418 lines
9.9 KiB
ArmAsm
/****************************************************************************
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* libs/libc/machine/arm/armv7-m/arch_strcmp.S
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-FileCopyrightText: 2012-2014 ARM Ltd
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#include "libc.h"
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#ifdef LIBC_BUILD_STRCMP
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/* Very similar to the generic code, but uses Thumb2 as implemented
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in ARMv7-M. */
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#ifdef __ARM_BIG_ENDIAN
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#define S2LO lsl
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#define S2LOEQ lsleq
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#define S2HI lsr
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#define MSB 0x000000ff
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#define LSB 0xff000000
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#define BYTE0_OFFSET 24
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#define BYTE1_OFFSET 16
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#define BYTE2_OFFSET 8
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#define BYTE3_OFFSET 0
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#else /* not __ARM_BIG_ENDIAN */
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#define S2LO lsr
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#define S2LOEQ lsreq
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#define S2HI lsl
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#define BYTE0_OFFSET 0
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#define BYTE1_OFFSET 8
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#define BYTE2_OFFSET 16
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#define BYTE3_OFFSET 24
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#define MSB 0xff000000
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#define LSB 0x000000ff
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#endif /* not __ARM_BIG_ENDIAN */
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/* Parameters and result. */
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#define src1 r0
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#define src2 r1
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#define result r0 /* Overlaps src1. */
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/* Internal variables. */
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#define data1 r2
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#define data2 r3
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#define tmp2 r5
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#define tmp1 r12
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#define syndrome r12 /* Overlaps tmp1 */
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.macro def_fn f p2align=0
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.text
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.section .text.strcmp, "ax"
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.p2align \p2align
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.global \f
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.type \f, %function
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\f:
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.endm
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.thumb
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.syntax unified
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def_fn ARCH_LIBCFUN(strcmp)
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.cfi_sections .debug_frame
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.cfi_startproc
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eor tmp1, src1, src2
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tst tmp1, #3
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/* Strings not at same byte offset from a word boundary. */
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bne .Lstrcmp_unaligned
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ands tmp1, src1, #3
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bic src1, src1, #3
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bic src2, src2, #3
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ldr data1, [src1], #4
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it eq
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ldreq data2, [src2], #4
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beq 4f
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/* Although s1 and s2 have identical initial alignment, they are
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not currently word aligned. Rather than comparing bytes,
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make sure that any bytes fetched from before the addressed
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bytes are forced to 0xff. Then they will always compare
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equal. */
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eor tmp1, tmp1, #3
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mvn data2, #MSB
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lsl tmp1, tmp1, #3
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S2LO tmp1, data2, tmp1
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ldr data2, [src2], #4
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orr data1, data1, tmp1
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orr data2, data2, tmp1
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.p2align 2
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/* Critical loop. */
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4:
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sub syndrome, data1, #0x01010101
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cmp data1, data2
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/* check for any zero bytes in first word */
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itttt eq
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biceq syndrome, syndrome, data1
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tsteq syndrome, #0x80808080
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ldreq data1, [src1], #4
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ldreq data2, [src2], #4
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beq 4b
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2:
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/* There's a zero or a different byte in the word */
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S2HI result, data1, #24
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S2LO data1, data1, #8
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cmp result, #1
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it cs
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cmpcs result, data2, S2HI #24
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it eq
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S2LOEQ data2, data2, #8
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beq 2b
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/* On a big-endian machine, RESULT contains the desired byte in bits
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0-7; on a little-endian machine they are in bits 24-31. In
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both cases the other bits in RESULT are all zero. For DATA2 the
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interesting byte is at the other end of the word, but the
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other bits are not necessarily zero. We need a signed result
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representing the difference in the unsigned bytes, so for the
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little-endian case we can't just shift the interesting bits
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up. */
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#ifdef __ARM_BIG_ENDIAN
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sub result, result, data2, lsr #24
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#else
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and data2, data2, #255
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lsrs result, result, #24
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subs result, result, data2
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#endif
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bx lr
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#if 0
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/* The assembly code below is based on the following algorithm. */
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#ifdef __ARM_BIG_ENDIAN
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#define RSHIFT <<
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#define LSHIFT >>
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#else
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#define RSHIFT >>
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#define LSHIFT <<
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#endif
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#define body(shift) \
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mask = 0xffffffffU RSHIFT shift; \
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data1 = *src1++; \
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data2 = *src2++; \
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do \
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{ \
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tmp2 = data1 & mask; \
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if (__builtin_expect(tmp2 != data2 RSHIFT shift, 0)) \
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{ \
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data2 RSHIFT= shift; \
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break; \
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} \
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if (__builtin_expect(((data1 - b1) & ~data1) & (b1 << 7), 0)) \
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{ \
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/* See comment in assembler below re syndrome on big-endian */\
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if ((((data1 - b1) & ~data1) & (b1 << 7)) & mask) \
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data2 RSHIFT= shift; \
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else \
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{ \
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data2 = *src2; \
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tmp2 = data1 RSHIFT (32 - shift); \
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data2 = (data2 LSHIFT (32 - shift)) RSHIFT (32 - shift); \
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} \
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break; \
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} \
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data2 = *src2++; \
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tmp2 ^= data1; \
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if (__builtin_expect(tmp2 != data2 LSHIFT (32 - shift), 0)) \
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{ \
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tmp2 = data1 >> (32 - shift); \
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data2 = (data2 << (32 - shift)) RSHIFT (32 - shift); \
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break; \
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} \
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data1 = *src1++; \
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} while (1)
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const unsigned* src1;
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const unsigned* src2;
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unsigned data1, data2;
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unsigned mask;
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unsigned shift;
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unsigned b1 = 0x01010101;
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char c1, c2;
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unsigned tmp2;
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while (((unsigned) s1) & 3)
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{
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c1 = *s1++;
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c2 = *s2++;
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if (c1 == 0 || c1 != c2)
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return c1 - (int)c2;
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}
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src1 = (unsigned*) (((unsigned)s1) & ~3);
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src2 = (unsigned*) (((unsigned)s2) & ~3);
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tmp2 = ((unsigned) s2) & 3;
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if (tmp2 == 1)
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{
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body(8);
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}
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else if (tmp2 == 2)
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{
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body(16);
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}
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else
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{
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body (24);
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}
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do
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{
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#ifdef __ARM_BIG_ENDIAN
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c1 = (char) tmp2 >> 24;
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c2 = (char) data2 >> 24;
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#else /* not __ARM_BIG_ENDIAN */
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c1 = (char) tmp2;
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c2 = (char) data2;
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#endif /* not __ARM_BIG_ENDIAN */
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tmp2 RSHIFT= 8;
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data2 RSHIFT= 8;
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} while (c1 != 0 && c1 == c2);
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return c1 - c2;
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#endif /* 0 */
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/* First of all, compare bytes until src1(sp1) is word-aligned. */
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.Lstrcmp_unaligned:
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tst src1, #3
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beq 2f
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ldrb data1, [src1], #1
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ldrb data2, [src2], #1
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cmp data1, #1
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it cs
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cmpcs data1, data2
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beq .Lstrcmp_unaligned
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sub result, data1, data2
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bx lr
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2:
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stmfd sp!, {r5}
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.cfi_def_cfa_offset 4
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.cfi_offset 5, -4
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ldr data1, [src1], #4
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and tmp2, src2, #3
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bic src2, src2, #3
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ldr data2, [src2], #4
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cmp tmp2, #2
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beq .Loverlap2
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bhi .Loverlap1
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/* Critical inner Loop: Block with 3 bytes initial overlap */
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.p2align 2
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.Loverlap3:
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bic tmp2, data1, #MSB
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cmp tmp2, data2, S2LO #8
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sub syndrome, data1, #0x01010101
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bic syndrome, syndrome, data1
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bne 4f
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ands syndrome, syndrome, #0x80808080
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it eq
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ldreq data2, [src2], #4
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bne 5f
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eor tmp2, tmp2, data1
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cmp tmp2, data2, S2HI #24
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bne 6f
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ldr data1, [src1], #4
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b .Loverlap3
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4:
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S2LO data2, data2, #8
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b .Lstrcmp_tail
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5:
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#ifdef __ARM_BIG_ENDIAN
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/* The syndrome value may contain false ones if the string ends
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with the bytes 0x01 0x00. */
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tst data1, #0xff000000
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itt ne
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tstne data1, #0x00ff0000
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tstne data1, #0x0000ff00
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beq .Lstrcmp_done_equal
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#else
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bics syndrome, syndrome, #0xff000000
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bne .Lstrcmp_done_equal
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#endif
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ldrb data2, [src2]
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S2LO tmp2, data1, #24
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#ifdef __ARM_BIG_ENDIAN
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lsl data2, data2, #24
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#endif
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b .Lstrcmp_tail
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6:
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S2LO tmp2, data1, #24
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and data2, data2, #LSB
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b .Lstrcmp_tail
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/* Critical inner Loop: Block with 2 bytes initial overlap. */
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.p2align 2
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.Loverlap2:
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S2HI tmp2, data1, #16
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sub syndrome, data1, #0x01010101
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S2LO tmp2, tmp2, #16
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bic syndrome, syndrome, data1
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cmp tmp2, data2, S2LO #16
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bne 4f
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ands syndrome, syndrome, #0x80808080
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it eq
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ldreq data2, [src2], #4
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bne 5f
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eor tmp2, tmp2, data1
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cmp tmp2, data2, S2HI #16
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bne 6f
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ldr data1, [src1], #4
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b .Loverlap2
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5:
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#ifdef __ARM_BIG_ENDIAN
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/* The syndrome value may contain false ones if the string ends
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with the bytes 0x01 0x00 */
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tst data1, #0xff000000
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it ne
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tstne data1, #0x00ff0000
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beq .Lstrcmp_done_equal
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#else
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lsls syndrome, syndrome, #16
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bne .Lstrcmp_done_equal
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#endif
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ldrh data2, [src2]
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S2LO tmp2, data1, #16
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#ifdef __ARM_BIG_ENDIAN
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lsl data2, data2, #16
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#endif
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b .Lstrcmp_tail
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6:
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S2HI data2, data2, #16
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S2LO tmp2, data1, #16
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4:
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S2LO data2, data2, #16
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b .Lstrcmp_tail
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/* Critical inner Loop: Block with 1 byte initial overlap. */
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.p2align 2
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.Loverlap1:
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and tmp2, data1, #LSB
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cmp tmp2, data2, S2LO #24
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sub syndrome, data1, #0x01010101
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bic syndrome, syndrome, data1
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bne 4f
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ands syndrome, syndrome, #0x80808080
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it eq
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ldreq data2, [src2], #4
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bne 5f
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eor tmp2, tmp2, data1
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cmp tmp2, data2, S2HI #8
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bne 6f
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ldr data1, [src1], #4
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b .Loverlap1
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4:
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S2LO data2, data2, #24
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b .Lstrcmp_tail
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5:
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/* The syndrome value may contain false ones if the string ends
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with the bytes 0x01 0x00. */
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tst data1, #LSB
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beq .Lstrcmp_done_equal
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ldr data2, [src2], #4
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6:
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S2LO tmp2, data1, #8
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bic data2, data2, #MSB
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b .Lstrcmp_tail
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.Lstrcmp_done_equal:
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mov result, #0
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.cfi_remember_state
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ldmfd sp!, {r5}
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.cfi_restore 5
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.cfi_def_cfa_offset 0
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bx lr
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.Lstrcmp_tail:
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.cfi_restore_state
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and r2, tmp2, #LSB
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and result, data2, #LSB
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cmp result, #1
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it cs
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cmpcs result, r2
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itt eq
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S2LOEQ tmp2, tmp2, #8
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S2LOEQ data2, data2, #8
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beq .Lstrcmp_tail
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sub result, r2, result
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ldmfd sp!, {r5}
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.cfi_restore 5
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.cfi_def_cfa_offset 0
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bx lr
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.cfi_endproc
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.size ARCH_LIBCFUN(strcmp), . - ARCH_LIBCFUN(strcmp)
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#endif
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