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nuttx/boards/arm/stm32f1/maple/include/board.h
raiden00pl e9ac37e427 !arch/arm/src/stm32: unify the timer input clock board options 
Replace the divergent board conventions for the timer input clock
frequency with a single uniform convention provided by every board:

- STM32_APBx_TIMn_CLKIN and BOARD_TIMn_FREQUENCY -> STM32_TIMn_CLKIN
- STM32_APBx_LPTIMn_CLKIN, BOARD_LPTIMn_FREQUENCY and
  STM32_LPTIMn_FREQUENCY -> STM32_LPTIMn_CLKIN
- STM32_APB1_THRTIM1_CLKIN and BOARD_HRTIM1_FREQUENCY ->
  STM32_HRTIM1_CLKIN

All STM32 consumers (tim/lptim/pwm/adc/dac/capture/sdadc/dfsdm/
pulsecount) updated to match; the timer input clock is now bus-agnostic
in the drivers.

Boards that carried the same timer clock in more than one convention now
define STM32_TIMn_CLKIN exactly once, derived from the APB bus clock
(PCLKx with the x2 doubler when the APB prescaler is greater than 1),
instead of redefining it with a second, sometimes different, value.

BREAKING CHANGE: The timer input-clock board macros STM32_APBx_TIMn_CLKIN,
BOARD_TIMn_FREQUENCY, STM32_APBx_LPTIMn_CLKIN, BOARD_LPTIMn_FREQUENCY,
STM32_LPTIMn_FREQUENCY, STM32_APB1_THRTIM1_CLKIN and
BOARD_HRTIM1_FREQUENCY are removed in favor of STM32_TIMn_CLKIN,
STM32_LPTIMn_CLKIN and STM32_HRTIM1_CLKIN.  Out-of-tree boards must
define the new macros (drop the APB bus from the name, keep the value),
and out-of-tree drivers referencing the old names must be updated.

Signed-off-by: raiden00pl <raiden00@railab.me>
2026-07-04 16:31:29 -03:00

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/****************************************************************************
* boards/arm/stm32f1/maple/include/board.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H
#define __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* On-board crystal frequency is 8MHz (HSE) */
#define STM32_BOARD_XTAL 8000000ul
/* PLL source is HSE/1, PLL multiplier is 9:
* PLL frequency is 8MHz (XTAL) x 9 = 72MHz
*/
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
#define STM32_CFGR_PLLXTPRE 0
#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
/* Use the PLL and set the SYSCLK source to be the PLL */
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
/* AHB clock (HCLK) is SYSCLK (72MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
/* APB2 clock (PCLK2) is HCLK (72MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
/* APB2 timers 1 and 8 will receive PCLK2. */
#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* APB1 timers 2-7 will be twice PCLK1 */
#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* USB divider -- Divide PLL clock by 1.5 */
#define STM32_CFGR_USBPRE 0
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
* to service FIFOs in interrupt driven mode. These values have not been
* tuned!!!
*
* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
*/
#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* LED definitions **********************************************************/
/* The board has only one controllable LED */
#define LED_STARTED 0 /* No LEDs */
#define LED_HEAPALLOCATE 1 /* LED1 on */
#define LED_IRQSENABLED 2 /* LED2 on */
#define LED_STACKCREATED 3 /* LED1 on */
#define LED_INIRQ 4 /* LED1 off */
#define LED_SIGNAL 5 /* LED2 on */
#define LED_ASSERTION 6 /* LED1 + LED2 */
#define LED_PANIC 7 /* LED1 / LED2 blinking */
/* Alternate function pin selections (auto-aliased for new pinmap) */
/* USART1 */
#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz)
#define GPIO_USART1_RX GPIO_USART1_RX_0
/* SPI1 */
#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz)
#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz)
#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz)
#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz)
/* I2C1 */
#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz)
#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz)
/* I2C2 */
#define GPIO_I2C2_SCL GPIO_ADJUST_MODE(GPIO_I2C2_SCL_0, GPIO_MODE_50MHz)
#define GPIO_I2C2_SDA GPIO_ADJUST_MODE(GPIO_I2C2_SDA_0, GPIO_MODE_50MHz)
/* USB */
#define GPIO_USB_DM GPIO_USB_DM_0
#define GPIO_USB_DP GPIO_USB_DP_0
/* TIM2 */
#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0
#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz)
#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0
#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz)
#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0
#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz)
#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0
#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz)
#endif /* __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H */
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