raiden00pl 7e5bf155b5 arch/intel64: don't clear the oneshot handler from the HPET ISR ... intel64_oneshot_handler() cleared oneshot->handler and oneshot->arg after picking them up, without holding g_oneshot_spin, while intel64_oneshot_start() re-arms the timer under that lock from another CPU. Now that the HPET ISR stays attached across a re-arm, a stale interrupt can interleave with start(): it reads the freshly installed handler, clears it, and start() then sets running = true again, so the genuine expiry that follows finds running == true with a NULL handler and jumps to address zero from interrupt context (page fault at RIP 0 in the CPU0 IDLE task while the LTP lio_listio tests were running), or the alarm is simply lost and the tickless system stops. The handler and its argument are owned by start() and cancel(); the ISR only needs to read them. Leave them alone in the ISR and skip the call if none is installed. The remaining effect of a stale interrupt is an early invocation of the alarm callback, which is harmless: the tickless scheduler re-evaluates its expirations and re-arms the timer. Assisted-by: Claude Code Signed-off-by: raiden00pl <raiden00@railab.me>		2026-09-10 10:23:46 +08:00
..
include	arch/atomic: remove up_testset in spinlock	2026-09-08 08:58:54 +08:00
src	arch/intel64: don't clear the oneshot handler from the HPET ISR	2026-09-10 10:23:46 +08:00
CMakeLists.txt	arch/x86_64: migrate to SPDX identifier	2024-12-02 17:23:25 +08:00
Kconfig	arch/x86_64: add support for xAPIC	2026-09-02 18:22:34 +08:00