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ab59b095a7
1. replace __mtcr/mfcr with arch's tricore_mtcr/tricore_mfcr, donot dependon illd 2. Simplify header files 3. define registers address self Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
358 lines
11 KiB
C
358 lines
11 KiB
C
/****************************************************************************
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* arch/tricore/include/irq.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_TRICORE_INCLUDE_IRQ_H
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#define __ARCH_TRICORE_INCLUDE_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <sys/types.h>
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#ifndef __ASSEMBLY__
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# include <stdbool.h>
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# include <syscall.h>
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#endif
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/* Include NuttX-specific IRQ definitions */
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#include <nuttx/irq.h>
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/* Include chip-specific IRQ definitions (including IRQ numbers) */
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#include <arch/chip/irq.h>
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#include <arch/arch.h>
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#include <IfxCpu_Intrinsics.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Address <--> Context Save Areas */
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#define tricore_csa2addr(csa) ((uintptr_t *)((((csa) & 0x000F0000) << 12) \
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| (((csa) & 0x0000FFFF) << 6)))
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#define tricore_addr2csa(addr) ((uintptr_t)(((((uintptr_t)(addr)) & 0xF0000000) >> 12) \
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| (((uintptr_t)(addr) & 0x003FFFC0) >> 6)))
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/* Upper CSA */
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#define REG_UPCXI 0
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#define REG_PSW 1
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#define REG_A10 2
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#define REG_UA11 3
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#define REG_D8 4
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#define REG_D9 5
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#define REG_D10 6
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#define REG_D11 7
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#define REG_A12 8
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#define REG_A13 9
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#define REG_A14 10
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#define REG_A15 11
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#define REG_D12 12
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#define REG_D13 13
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#define REG_D14 14
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#define REG_D15 15
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/* Lower CSA */
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#define REG_LPCXI 0
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#define REG_LA11 1
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#define REG_A2 2
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#define REG_A3 3
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#define REG_D0 4
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#define REG_D1 5
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#define REG_D2 6
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#define REG_D3 7
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#define REG_A4 8
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#define REG_A5 9
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#define REG_A6 10
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#define REG_A7 11
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#define REG_D4 12
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#define REG_D5 13
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#define REG_D6 14
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#define REG_D7 15
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#define REG_RA REG_UA11
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#define REG_SP REG_A10
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#define REG_UPC REG_UA11
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#define REG_LPC REG_LA11
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#define TC_CONTEXT_REGS (16)
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#define TC_CONTEXT_SIZE (sizeof(void *) * TC_CONTEXT_REGS)
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#define XCPTCONTEXT_REGS (TC_CONTEXT_REGS * 2)
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#define XCPTCONTEXT_SIZE (sizeof(void *) * XCPTCONTEXT_REGS)
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#define NR_IRQS (2048)
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/* PSW: Program Status Word Register */
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#define PSW_CDE (1 << 7) /* Bits 7: Call Depth Count Enable */
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#define PSW_IS (1 << 9) /* Bits 9: Interrupt Stack Control */
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#define PSW_IO (10) /* Bits 10-11: Access Privilege Level Control (I/O Privilege) */
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# define PSW_IO_USER0 (0 << PSW_IO)
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# define PSW_IO_USER1 (1 << PSW_IO)
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# define PSW_IO_SUPERVISOR (2 << PSW_IO)
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/* PCXI: Previous Context Information and Pointer Register */
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#define PCXI_UL (1 << 20) /* Bits 20: Upper or Lower Context Tag */
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#define PCXI_PIE (1 << 21) /* Bits 21: Previous Interrupt Enable */
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/* FCX: Free CSA List Head Pointer Register */
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#define FCX_FCXO (0) /* Bits 0-15: FCX Offset Address */
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#define FCX_FCXS (16) /* Bits 16-19: FCX Segment Address */
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#define FCX_FCXO_MASK (0xffff << FCX_FCXO)
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#define FCX_FCXS_MASK (0xf << FCX_FCXS)
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#define FCX_FREE (FCX_FCXS_MASK | FCX_FCXO_MASK) /* Free CSA manipulation */
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#define TRICORE_SRCNUM_PER_GPSR 8
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#define TRICORE_SRC2IRQ(src_addr) \
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(((uintptr_t)(src_addr) - (uintptr_t)&MODULE_SRC) / 4)
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#define TRICORE_GPSR_IRQNUM(src_cpu, dest_cpu) \
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TRICORE_SRC2IRQ(&SRC_GPSR00 + src_cpu * 8 + dest_cpu)
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/* For use with EABI and floating point, the stack must be aligned to 8-byte
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* addresses.
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*/
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#define STACKFRAME_ALIGN 8
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/* FPU registers */
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#ifdef CONFIG_ARCH_TC1V6
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# define FPU_SYNC_TRAP_REG 0xA000
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# define FPU_ASYNC_TRAP_REG 0xA000
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#else
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# define FPU_SYNC_TRAP_REG 0xA030
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# define FPU_ASYNC_TRAP_REG 0xA000
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#endif
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#define FPU_TRAP_FZE_SHIFT 20
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#define FPU_TRAP_TCL_SHIFT 1
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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struct xcptcontext
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{
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#ifdef CONFIG_ENABLE_ALL_SIGNALS
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/* These are saved copies of the context used during
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* signal processing.
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*/
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uintptr_t *saved_regs;
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#endif
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/* Register save area with XCPTCONTEXT_SIZE, only valid when:
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* 1.The task isn't running or
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* 2.The task is interrupted
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* otherwise task is running, and regs contain the stale value.
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*/
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uintptr_t *regs;
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};
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* g_interrupt_context store irq status */
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EXTERN volatile bool g_interrupt_context[CONFIG_SMP_NCPUS];
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: up_cpu_index
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*
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* Description:
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* Return the real core number regardless CONFIG_SMP setting
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_HAVE_MULTICPU
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int up_cpu_index(void) noinstrument_function;
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#endif /* CONFIG_ARCH_HAVE_MULTICPU */
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/****************************************************************************
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* Name: up_irq_enable
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*
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* Description:
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* Enable interrupts globally.
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*
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****************************************************************************/
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void up_irq_enable(void);
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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noinstrument_function static inline_function uintptr_t up_getsp(void)
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{
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#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING
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return (uintptr_t)__get_sp();
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#else
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return (uintptr_t)__builtin_frame_address(0);
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#endif
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}
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/****************************************************************************
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* Name: up_irq_save
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*
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* Description:
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* Disable interrupts and return the previous value of the mstatus register
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*
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****************************************************************************/
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noinstrument_function static inline_function irqstate_t up_irq_save(void)
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{
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return __disable_and_save();
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}
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/****************************************************************************
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* Name: up_irq_restore
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*
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* Description:
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* Restore the value of the mstatus register
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*
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****************************************************************************/
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noinstrument_function static inline_function
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void up_irq_restore(irqstate_t flags)
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{
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__restore(flags);
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}
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_set_interrupt_context
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*
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* Description:
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* Set the interrupt handler context.
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*
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****************************************************************************/
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noinstrument_function
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static inline_function void up_set_interrupt_context(bool flag)
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{
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#ifdef CONFIG_SMP
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g_interrupt_context[up_this_cpu()] = flag;
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#else
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g_interrupt_context[0] = flag;
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#endif
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}
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/****************************************************************************
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* Name: up_interrupt_context
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*
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* Description:
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* Return true is we are currently executing in the interrupt
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* handler context.
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*
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****************************************************************************/
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noinstrument_function
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static inline_function bool up_interrupt_context(void)
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{
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#ifdef CONFIG_SMP
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irqstate_t flags = up_irq_save();
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bool ret = g_interrupt_context[up_this_cpu()];
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up_irq_restore(flags);
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return ret;
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#else
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return g_interrupt_context[0];
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#endif
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}
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/****************************************************************************
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* Name: up_getusrsp
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****************************************************************************/
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static inline_function uintptr_t up_getusrsp(void *regs)
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{
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uintptr_t *csaregs = (uintptr_t *)regs;
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if (csaregs[REG_LPCXI] & PCXI_UL)
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{
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csaregs = tricore_csa2addr(csaregs[REG_LPCXI]);
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}
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else
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{
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csaregs += TC_CONTEXT_REGS;
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}
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return csaregs[REG_SP];
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}
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Name: up_switch_context
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****************************************************************************/
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#define up_switch_context(tcb, rtcb) \
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do { \
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if (!up_interrupt_context()) \
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{ \
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sys_call0(SYS_switch_context); \
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} \
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UNUSED(rtcb); \
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} while (0)
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/****************************************************************************
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* Name: up_getusrpc
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****************************************************************************/
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#define up_getusrpc(regs) \
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(((uint32_t *)((regs) ? (regs) : running_regs()))[REG_UPC])
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ARCH_TRICORE_INCLUDE_IRQ_H */
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