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d2c91137e5
Replace the iLLD register structures (Ifx_CPU_PCON0/1/2, Ifx_CPU_DCON0/1/2) and the IfxCpu_cfg.h cache-size/line-size macros in the cache path with direct CSR accesses via tricore_mtcr()/tricore_mfcr() and locally defined PCON/DCON bit masks. Also switch __isync()/__dsync() to the UP_ISB()/ UP_DSB() barrier wrappers. This removes the arch/tricore cache path's dependency on the Infineon iLLD layer. No behavior change. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
31 lines
1.4 KiB
C
31 lines
1.4 KiB
C
/****************************************************************************
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* arch/tricore/include/barriers.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_TRICORE_INCLUDE_BARRIERS_H
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#define __ARCH_TRICORE_INCLUDE_BARRIERS_H
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#define UP_DSB() __asm__ volatile ("dsync" : : : "memory")
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#define UP_DMB() asm volatile ("" : : : "memory")
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#define UP_RMB() asm volatile ("" : : : "memory")
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#define UP_WMB() asm volatile ("" : : : "memory")
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#define UP_ISB() __asm__ volatile ("isync" : : : "memory")
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#endif /* __ARCH_TRICORE_INCLUDE_BARRIERS_H */
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