nuttx/arch/risc-v/include/barriers.h
Chengdong Wang 1924a96064 arch/riscv: Add CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI for fence.i
The fence.i instruction is only available when the Zifencei extension
(CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI) is supported by the hardware.

This commit adds a macro wrapper around fence.i usages to prevent
compilation errors on toolchains or targets where the Zifencei
extension is absent.

Signed-off-by: Chengdong Wang <wangcd91@gmail.com>
2026-06-28 02:17:03 +08:00

48 lines
1.7 KiB
C

/****************************************************************************
* arch/risc-v/include/barriers.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_BARRIERS_H
#define __ARCH_RISCV_INCLUDE_BARRIERS_H
/* Common memory barriers (p=predecessor, s=successor) */
#define __FENCE(p, s) __asm__ __volatile__ ("fence "#p", "#s ::: "memory")
/* UP_DMB() is used to flush local data caches (memory) */
#define UP_DMB() __FENCE(rw, rw)
#define UP_RMB() __FENCE(r, r)
#define UP_WMB() __FENCE(w, w)
/* UP_DSB() is a full memory barrier */
#define UP_DSB() __FENCE(iorw, iorw)
/* UP_ISB() is used to synchronize the instruction and data streams */
#ifdef CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI
# define UP_ISB() __asm__ __volatile__ ("fence.i" ::: "memory")
#else
# define UP_ISB()
#endif
#endif /* __ARCH_RISCV_INCLUDE_BARRIERS_H */