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On K3 SoCs the A53 cluster does not own device power, clocks, resets or interrupt routing; these are managed by the DM/TIFS firmware and requested over TISCI through the secure-proxy mailbox. Add: - a TISCI client (secure-proxy transport plus device/clock/reset helpers) - a GPIO driver for banks 0/1 with pad mux and TISCI power-on - an OMAP-I2C driver for the main-domain I2C controllers and wire them into the PocketBeagle2 and BeaglePlay bring-up. Tested on PocketBeagle2 (SYSFW 11.2.5) with the TechLab cape attached: nsh> i2c bus nsh> i2c dev -b 0 0x03 0x77 # I2C0 detects onboard 0x20 and 0x50 nsh> gpio -o 1 /dev/gpio3 # drives a user LED; read back with: nsh> gpio /dev/gpio3 Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
117 lines
4.5 KiB
C
117 lines
4.5 KiB
C
/****************************************************************************
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* arch/arm64/include/am62x/irq.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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/* Reference: AM62x TRM (SPRSP43), Chapter 9 — Interrupt Architecture
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*
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* The AM62x GIC-600 supports:
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* - 16 SGIs (Software Generated Interrupts) IRQ 0 – 15
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* - 16 PPIs (Private Peripheral Interrupts) IRQ 16 – 31
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* - 480 SPIs (Shared Peripheral Interrupts) IRQ 32 – 511
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*
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* Total: 512 interrupt lines.
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*
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* All INTIDs listed here are INTID = GIC_SPI_number + 32.
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* E.g. UART0 GIC_SPI 178 -> INTID 210.
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*/
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#ifndef __ARCH_ARM64_INCLUDE_AM62X_IRQ_H
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#define __ARCH_ARM64_INCLUDE_AM62X_IRQ_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Total number of interrupt IDs allocated in the GIC INTID space.
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* NuttX arrays are sized to NR_IRQS entries, so set this to the maximum
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* INTID we actually use + 1. 512 covers all AM62x SPIs.
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*/
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#define NR_IRQS 512
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/* SGI interrupts (per-core, software-generated) */
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#define AM62X_IRQ_SGI0 0
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#define AM62X_IRQ_SGI1 1
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#define AM62X_IRQ_SGI2 2
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#define AM62X_IRQ_SGI3 3
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#define AM62X_IRQ_SGI4 4
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#define AM62X_IRQ_SGI5 5
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#define AM62X_IRQ_SGI6 6
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#define AM62X_IRQ_SGI7 7
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#define AM62X_IRQ_SGI8 8
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#define AM62X_IRQ_SGI9 9
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#define AM62X_IRQ_SGI10 10
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#define AM62X_IRQ_SGI11 11
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#define AM62X_IRQ_SGI12 12
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#define AM62X_IRQ_SGI13 13
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#define AM62X_IRQ_SGI14 14
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#define AM62X_IRQ_SGI15 15
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/* PPI interrupts (per-core, private peripherals)
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*
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* Generic timer PPIs follow the architected GIC assignments:
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* - Hypervisor timer PPI 10 -> INTID 26
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* - Virtual timer PPI 11 -> INTID 27
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* - Secure physical timer PPI 13 -> INTID 29
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* - Non-secure physical timer PPI 14 -> INTID 30
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*/
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#define AM62X_IRQ_PPI_HYPTIMER 26 /* Hypervisor timer */
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#define AM62X_IRQ_PPI_VTIMER 27 /* Virtual timer (EL1) */
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#define AM62X_IRQ_PPI_PTIMER 30 /* Physical timer NS EL1/EL0 */
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#define AM62X_IRQ_PPI_PTIMER_S 29 /* Physical timer secure EL3 */
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#define AM62X_IRQ_PPI_PTIMER_NS 30 /* Physical timer NS EL1/EL0 */
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/* Main domain SPI interrupts (INTID = SPI_offset + 32).
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* Source: AM62x TRM Table 9-17 (Interrupt Map).
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*/
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/* UART (main domain, 16550-compatible)
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* Source: Linux arch/arm64/boot/dts/ti/k3-am62.dtsi
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* UART0 GIC_SPI 178 -> INTID 210, UART6 GIC_SPI 184 -> INTID 216
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*/
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#define AM62X_IRQ_UART0 210 /* GIC_SPI 178: UART0 main domain */
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#define AM62X_IRQ_UART1 211 /* GIC_SPI 179 */
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#define AM62X_IRQ_UART2 212 /* GIC_SPI 180 */
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#define AM62X_IRQ_UART3 213 /* GIC_SPI 181 */
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#define AM62X_IRQ_UART4 214 /* GIC_SPI 182 */
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#define AM62X_IRQ_UART5 215 /* GIC_SPI 183 */
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#define AM62X_IRQ_UART6 216 /* GIC_SPI 184 */
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/* GPIO */
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#define AM62X_IRQ_GPIO0 57
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#define AM62X_IRQ_GPIO1 58
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/* I2C */
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#define AM62X_IRQ_I2C0 193 /* GIC_SPI 161 */
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#define AM62X_IRQ_I2C1 194 /* GIC_SPI 162 */
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#define AM62X_IRQ_I2C2 195 /* GIC_SPI 163 */
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#define AM62X_IRQ_I2C3 196 /* GIC_SPI 164 */
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#endif /* __ARCH_ARM64_INCLUDE_AM62X_IRQ_H */
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