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da74440a20
add stm32u0 support Signed-off-by: raiden00pl <raiden00@railab.me> Assisted-by: Claude Code
106 lines
5 KiB
C
106 lines
5 KiB
C
/****************************************************************************
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* arch/arm/include/stm32u0/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32U0_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32U0_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Number of peripheral interrupts */
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#define ARMV6M_PERIPHERAL_INTERRUPTS 32
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/* Get the flash size for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_STM32U073C8) || \
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defined(CONFIG_ARCH_CHIP_STM32U073M8) || \
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defined(CONFIG_ARCH_CHIP_STM32U073R8)
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# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */
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#elif defined(CONFIG_ARCH_CHIP_STM32U073CB) || \
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defined(CONFIG_ARCH_CHIP_STM32U073MB) || \
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defined(CONFIG_ARCH_CHIP_STM32U073RB)
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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#elif defined(CONFIG_ARCH_CHIP_STM32U073CC) || \
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defined(CONFIG_ARCH_CHIP_STM32U073MC) || \
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defined(CONFIG_ARCH_CHIP_STM32U073RC) || \
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defined(CONFIG_ARCH_CHIP_STM32U083CC) || \
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defined(CONFIG_ARCH_CHIP_STM32U083MC) || \
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defined(CONFIG_ARCH_CHIP_STM32U083RC)
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# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */
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#endif
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/* Get customizations for each supported chip.
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* The STM32U073xx and STM32U083xx families share the same peripheral set
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* except for the AES accelerator which is available only on STM32U083xx.
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*/
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# define STM32_SRAM_SIZE (40 * 1024) /* 40Kb = 32Kb SRAM1 + 8Kb
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* backup SRAM2 (contiguous) */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM3,
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* TIM15-16 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timer TIM2 */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 */
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/* Three LPTIMER: LPTIM1-3 */
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# define STM32_NSPI 3 /* Three SPI modules SPI1-3 */
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# define STM32_NI2S 1 /* One I2S module (SPI1 or I2S1) */
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# define STM32_NI2C 4 /* Four I2C modules I2C1-4 */
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# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* Three LPUART: LPUART1-3 */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 1 /* One LCD controller */
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# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* (1) ADC1, 19-channels */
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# define STM32_NDAC 1 /* One DAC channel */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 1 /* One Touch sensing controller (TSC) */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value,
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* the greater the priority of the corresponding interrupt. The processor
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* implements only bits[7:6] of each field, bits[5:0] read as zero and
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* ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32U0_CHIP_H */
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